drivers/pci/host/pci-rcar-gen2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  pci-rcar-gen2: internal PCI bus support
   4  *
   5  * Copyright (C) 2013 Renesas Solutions Corp.
   6  * Copyright (C) 2013 Cogent Embedded, Inc.
   7  *
   8  * Author: Valentine Barshak <valentine.barshak@cogentembedded.com>
   9  */
  10
  11 #include <linux/delay.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/kernel.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/pci.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/sizes.h>
  22 #include <linux/slab.h>
  23
  24 /* AHB-PCI Bridge PCI communication registers */
  25 #define RCAR_AHBPCI_PCICOM_OFFSET       0x800
  26
  27 #define RCAR_PCIAHB_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
  28 #define RCAR_PCIAHB_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
  29 #define RCAR_PCIAHB_PREFETCH0           0x0
  30 #define RCAR_PCIAHB_PREFETCH4           0x1
  31 #define RCAR_PCIAHB_PREFETCH8           0x2
  32 #define RCAR_PCIAHB_PREFETCH16          0x3
  33
  34 #define RCAR_AHBPCI_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
  35 #define RCAR_AHBPCI_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
  36 #define RCAR_AHBPCI_WIN_CTR_MEM         (3 << 1)
  37 #define RCAR_AHBPCI_WIN_CTR_CFG         (5 << 1)
  38 #define RCAR_AHBPCI_WIN1_HOST           (1 << 30)
  39 #define RCAR_AHBPCI_WIN1_DEVICE         (1 << 31)
  40
  41 #define RCAR_PCI_INT_ENABLE_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
  42 #define RCAR_PCI_INT_STATUS_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
  43 #define RCAR_PCI_INT_SIGTABORT          (1 << 0)
  44 #define RCAR_PCI_INT_SIGRETABORT        (1 << 1)
  45 #define RCAR_PCI_INT_REMABORT           (1 << 2)
  46 #define RCAR_PCI_INT_PERR               (1 << 3)
  47 #define RCAR_PCI_INT_SIGSERR            (1 << 4)
  48 #define RCAR_PCI_INT_RESERR             (1 << 5)
  49 #define RCAR_PCI_INT_WIN1ERR            (1 << 12)
  50 #define RCAR_PCI_INT_WIN2ERR            (1 << 13)
  51 #define RCAR_PCI_INT_A                  (1 << 16)
  52 #define RCAR_PCI_INT_B                  (1 << 17)
  53 #define RCAR_PCI_INT_PME                (1 << 19)
  54 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT          | \
  55                                 RCAR_PCI_INT_SIGRETABORT        | \
  56                                 RCAR_PCI_INT_SIGRETABORT        | \
  57                                 RCAR_PCI_INT_REMABORT           | \
  58                                 RCAR_PCI_INT_PERR               | \
  59                                 RCAR_PCI_INT_SIGSERR            | \
  60                                 RCAR_PCI_INT_RESERR             | \
  61                                 RCAR_PCI_INT_WIN1ERR            | \
  62                                 RCAR_PCI_INT_WIN2ERR)
  63
  64 #define RCAR_AHB_BUS_CTR_REG            (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
  65 #define RCAR_AHB_BUS_MMODE_HTRANS       (1 << 0)
  66 #define RCAR_AHB_BUS_MMODE_BYTE_BURST   (1 << 1)
  67 #define RCAR_AHB_BUS_MMODE_WR_INCR      (1 << 2)
  68 #define RCAR_AHB_BUS_MMODE_HBUS_REQ     (1 << 7)
  69 #define RCAR_AHB_BUS_SMODE_READYCTR     (1 << 17)
  70 #define RCAR_AHB_BUS_MODE               (RCAR_AHB_BUS_MMODE_HTRANS |    \
  71                                         RCAR_AHB_BUS_MMODE_BYTE_BURST | \
  72                                         RCAR_AHB_BUS_MMODE_WR_INCR |    \
  73                                         RCAR_AHB_BUS_MMODE_HBUS_REQ |   \
  74                                         RCAR_AHB_BUS_SMODE_READYCTR)
  75
  76 #define RCAR_USBCTR_REG                 (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
  77 #define RCAR_USBCTR_USBH_RST            (1 << 0)
  78 #define RCAR_USBCTR_PCICLK_MASK         (1 << 1)
  79 #define RCAR_USBCTR_PLL_RST             (1 << 2)
  80 #define RCAR_USBCTR_DIRPD               (1 << 8)
  81 #define RCAR_USBCTR_PCIAHB_WIN2_EN      (1 << 9)
  82 #define RCAR_USBCTR_PCIAHB_WIN1_256M    (0 << 10)
  83 #define RCAR_USBCTR_PCIAHB_WIN1_512M    (1 << 10)
  84 #define RCAR_USBCTR_PCIAHB_WIN1_1G      (2 << 10)
  85 #define RCAR_USBCTR_PCIAHB_WIN1_2G      (3 << 10)
  86 #define RCAR_USBCTR_PCIAHB_WIN1_MASK    (3 << 10)
  87
  88 #define RCAR_PCI_ARBITER_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
  89 #define RCAR_PCI_ARBITER_PCIREQ0        (1 << 0)
  90 #define RCAR_PCI_ARBITER_PCIREQ1        (1 << 1)
  91 #define RCAR_PCI_ARBITER_PCIBP_MODE     (1 << 12)
  92
  93 #define RCAR_PCI_UNIT_REV_REG           (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
  94
  95 struct rcar_pci_priv {
  96         struct device *dev;
  97         void __iomem *reg;
  98         struct resource mem_res;
  99         struct resource *cfg_res;
 100         unsigned busnr;
 101         int irq;
 102         unsigned long window_size;
 103         unsigned long window_addr;
 104         unsigned long window_pci;
 105 };
 106
 107 /* PCI configuration space operations */
 108 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
 109                                        int where)
 110 {
 111         struct pci_sys_data *sys = bus->sysdata;
 112         struct rcar_pci_priv *priv = sys->private_data;
 113         int slot, val;
 114
 115         if (sys->busnr != bus->number || PCI_FUNC(devfn))
 116                 return NULL;
 117
 118         /* Only one EHCI/OHCI device built-in */
 119         slot = PCI_SLOT(devfn);
 120         if (slot > 2)
 121                 return NULL;
 122
 123         /* bridge logic only has registers to 0x40 */
 124         if (slot == 0x0 && where >= 0x40)
 125                 return NULL;
 126
 127         val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
 128                      RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
 129
 130         iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
 131         return priv->reg + (slot >> 1) * 0x100 + where;
 132 }
 133
 134 /* PCI interrupt mapping */
 135 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 136 {
 137         struct pci_sys_data *sys = dev->bus->sysdata;
 138         struct rcar_pci_priv *priv = sys->private_data;
 139         int irq;
 140
 141         irq = of_irq_parse_and_map_pci(dev, slot, pin);
 142         if (!irq)
 143                 irq = priv->irq;
 144
 145         return irq;
 146 }
 147
 148 #ifdef CONFIG_PCI_DEBUG
 149 /* if debug enabled, then attach an error handler irq to the bridge */
 150
 151 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
 152 {
 153         struct rcar_pci_priv *priv = pw;
 154         struct device *dev = priv->dev;
 155         u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
 156
 157         if (status & RCAR_PCI_INT_ALLERRORS) {
 158                 dev_err(dev, "error irq: status %08x\n", status);
 159
 160                 /* clear the error(s) */
 161                 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
 162                           priv->reg + RCAR_PCI_INT_STATUS_REG);
 163                 return IRQ_HANDLED;
 164         }
 165
 166         return IRQ_NONE;
 167 }
 168
 169 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
 170 {
 171         struct device *dev = priv->dev;
 172         int ret;
 173         u32 val;
 174
 175         ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq,
 176                                IRQF_SHARED, "error irq", priv);
 177         if (ret) {
 178                 dev_err(dev, "cannot claim IRQ for error handling\n");
 179                 return;
 180         }
 181
 182         val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
 183         val |= RCAR_PCI_INT_ALLERRORS;
 184         iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
 185 }
 186 #else
 187 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
 188 #endif
 189
 190 /* PCI host controller setup */
 191 static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
 192 {
 193         struct rcar_pci_priv *priv = sys->private_data;
 194         struct device *dev = priv->dev;
 195         void __iomem *reg = priv->reg;
 196         u32 val;
 197         int ret;
 198
 199         pm_runtime_enable(dev);
 200         pm_runtime_get_sync(dev);
 201
 202         val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
 203         dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val);
 204
 205         /* Disable Direct Power Down State and assert reset */
 206         val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
 207         val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
 208         iowrite32(val, reg + RCAR_USBCTR_REG);
 209         udelay(4);
 210
 211         /* De-assert reset and reset PCIAHB window1 size */
 212         val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
 213                  RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
 214
 215         /* Setup PCIAHB window1 size */
 216         switch (priv->window_size) {
 217         case SZ_2G:
 218                 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
 219                 break;
 220         case SZ_1G:
 221                 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
 222                 break;
 223         case SZ_512M:
 224                 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
 225                 break;
 226         default:
 227                 pr_warn("unknown window size %ld - defaulting to 256M\n",
 228                         priv->window_size);
 229                 priv->window_size = SZ_256M;
 230                 /* fall-through */
 231         case SZ_256M:
 232                 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
 233                 break;
 234         }
 235         iowrite32(val, reg + RCAR_USBCTR_REG);
 236
 237         /* Configure AHB master and slave modes */
 238         iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
 239
 240         /* Configure PCI arbiter */
 241         val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
 242         val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
 243                RCAR_PCI_ARBITER_PCIBP_MODE;
 244         iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
 245
 246         /* PCI-AHB mapping */
 247         iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
 248                   reg + RCAR_PCIAHB_WIN1_CTR_REG);
 249
 250         /* AHB-PCI mapping: OHCI/EHCI registers */
 251         val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
 252         iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
 253
 254         /* Enable AHB-PCI bridge PCI configuration access */
 255         iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
 256                   reg + RCAR_AHBPCI_WIN1_CTR_REG);
 257         /* Set PCI-AHB Window1 address */
 258         iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
 259                   reg + PCI_BASE_ADDRESS_1);
 260         /* Set AHB-PCI bridge PCI communication area address */
 261         val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
 262         iowrite32(val, reg + PCI_BASE_ADDRESS_0);
 263
 264         val = ioread32(reg + PCI_COMMAND);
 265         val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 266                PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 267         iowrite32(val, reg + PCI_COMMAND);
 268
 269         /* Enable PCI interrupts */
 270         iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
 271                   reg + RCAR_PCI_INT_ENABLE_REG);
 272
 273         if (priv->irq > 0)
 274                 rcar_pci_setup_errirq(priv);
 275
 276         /* Add PCI resources */
 277         pci_add_resource(&sys->resources, &priv->mem_res);
 278         ret = devm_request_pci_bus_resources(dev, &sys->resources);
 279         if (ret < 0)
 280                 return ret;
 281
 282         /* Setup bus number based on platform device id / of bus-range */
 283         sys->busnr = priv->busnr;
 284         return 1;
 285 }
 286
 287 static struct pci_ops rcar_pci_ops = {
 288         .map_bus = rcar_pci_cfg_base,
 289         .read   = pci_generic_config_read,
 290         .write  = pci_generic_config_write,
 291 };
 292
 293 static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
 294                                          struct device_node *np)
 295 {
 296         struct device *dev = pci->dev;
 297         struct of_pci_range range;
 298         struct of_pci_range_parser parser;
 299         int index = 0;
 300
 301         /* Failure to parse is ok as we fall back to defaults */
 302         if (of_pci_dma_range_parser_init(&parser, np))
 303                 return 0;
 304
 305         /* Get the dma-ranges from DT */
 306         for_each_of_pci_range(&parser, &range) {
 307                 /* Hardware only allows one inbound 32-bit range */
 308                 if (index)
 309                         return -EINVAL;
 310
 311                 pci->window_addr = (unsigned long)range.cpu_addr;
 312                 pci->window_pci = (unsigned long)range.pci_addr;
 313                 pci->window_size = (unsigned long)range.size;
 314
 315                 /* Catch HW limitations */
 316                 if (!(range.flags & IORESOURCE_PREFETCH)) {
 317                         dev_err(dev, "window must be prefetchable\n");
 318                         return -EINVAL;
 319                 }
 320                 if (pci->window_addr) {
 321                         u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
 322
 323                         if (lowaddr < pci->window_size) {
 324                                 dev_err(dev, "invalid window size/addr\n");
 325                                 return -EINVAL;
 326                         }
 327                 }
 328                 index++;
 329         }
 330
 331         return 0;
 332 }
 333
 334 static int rcar_pci_probe(struct platform_device *pdev)
 335 {
 336         struct device *dev = &pdev->dev;
 337         struct resource *cfg_res, *mem_res;
 338         struct rcar_pci_priv *priv;
 339         void __iomem *reg;
 340         struct hw_pci hw;
 341         void *hw_private[1];
 342
 343         cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 344         reg = devm_ioremap_resource(dev, cfg_res);
 345         if (IS_ERR(reg))
 346                 return PTR_ERR(reg);
 347
 348         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 349         if (!mem_res || !mem_res->start)
 350                 return -ENODEV;
 351
 352         if (mem_res->start & 0xFFFF)
 353                 return -EINVAL;
 354
 355         priv = devm_kzalloc(dev, sizeof(struct rcar_pci_priv), GFP_KERNEL);
 356         if (!priv)
 357                 return -ENOMEM;
 358
 359         priv->mem_res = *mem_res;
 360         priv->cfg_res = cfg_res;
 361
 362         priv->irq = platform_get_irq(pdev, 0);
 363         priv->reg = reg;
 364         priv->dev = dev;
 365
 366         if (priv->irq < 0) {
 367                 dev_err(dev, "no valid irq found\n");
 368                 return priv->irq;
 369         }
 370
 371         /* default window addr and size if not specified in DT */
 372         priv->window_addr = 0x40000000;
 373         priv->window_pci = 0x40000000;
 374         priv->window_size = SZ_1G;
 375
 376         if (dev->of_node) {
 377                 struct resource busnr;
 378                 int ret;
 379
 380                 ret = of_pci_parse_bus_range(dev->of_node, &busnr);
 381                 if (ret < 0) {
 382                         dev_err(dev, "failed to parse bus-range\n");
 383                         return ret;
 384                 }
 385
 386                 priv->busnr = busnr.start;
 387                 if (busnr.end != busnr.start)
 388                         dev_warn(dev, "only one bus number supported\n");
 389
 390                 ret = rcar_pci_parse_map_dma_ranges(priv, dev->of_node);
 391                 if (ret < 0) {
 392                         dev_err(dev, "failed to parse dma-range\n");
 393                         return ret;
 394                 }
 395         } else {
 396                 priv->busnr = pdev->id;
 397         }
 398
 399         hw_private[0] = priv;
 400         memset(&hw, 0, sizeof(hw));
 401         hw.nr_controllers = ARRAY_SIZE(hw_private);
 402         hw.io_optional = 1;
 403         hw.private_data = hw_private;
 404         hw.map_irq = rcar_pci_map_irq;
 405         hw.ops = &rcar_pci_ops;
 406         hw.setup = rcar_pci_setup;
 407         pci_common_init_dev(dev, &hw);
 408         return 0;
 409 }
 410
 411 static const struct of_device_id rcar_pci_of_match[] = {
 412         { .compatible = "renesas,pci-r8a7790", },
 413         { .compatible = "renesas,pci-r8a7791", },
 414         { .compatible = "renesas,pci-r8a7794", },
 415         { .compatible = "renesas,pci-rcar-gen2", },
 416         { },
 417 };
 418
 419 static struct platform_driver rcar_pci_driver = {
 420         .driver = {
 421                 .name = "pci-rcar-gen2",
 422                 .suppress_bind_attrs = true,
 423                 .of_match_table = rcar_pci_of_match,
 424         },
 425         .probe = rcar_pci_probe,
 426 };
 427 builtin_platform_driver(rcar_pci_driver);