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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / pci / host / pci-tegra.c
blobdd9b3bcc41c38f66a667bf608fbfa499c535a709
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCIe host controller driver for Tegra SoCs
4 *
5 * Copyright (c) 2010, CompuLab, Ltd.
6 * Author: Mike Rapoport <mike@compulab.co.il>
7 *
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
10 *
11 * Bits taken from arch/arm/mach-dove/pcie.c
12 *
13 * Author: Thierry Reding <treding@nvidia.com>
14 */
15
16 #include <linux/clk.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/export.h>
20 #include <linux/interrupt.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/msi.h>
26 #include <linux/of_address.h>
27 #include <linux/of_pci.h>
28 #include <linux/of_platform.h>
29 #include <linux/pci.h>
30 #include <linux/phy/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/reset.h>
33 #include <linux/sizes.h>
34 #include <linux/slab.h>
35 #include <linux/vmalloc.h>
36 #include <linux/regulator/consumer.h>
37
38 #include <soc/tegra/cpuidle.h>
39 #include <soc/tegra/pmc.h>
40
41 #define INT_PCI_MSI_NR (8 * 32)
42
43 /* register definitions */
44
45 #define AFI_AXI_BAR0_SZ 0x00
46 #define AFI_AXI_BAR1_SZ 0x04
47 #define AFI_AXI_BAR2_SZ 0x08
48 #define AFI_AXI_BAR3_SZ 0x0c
49 #define AFI_AXI_BAR4_SZ 0x10
50 #define AFI_AXI_BAR5_SZ 0x14
51
52 #define AFI_AXI_BAR0_START 0x18
53 #define AFI_AXI_BAR1_START 0x1c
54 #define AFI_AXI_BAR2_START 0x20
55 #define AFI_AXI_BAR3_START 0x24
56 #define AFI_AXI_BAR4_START 0x28
57 #define AFI_AXI_BAR5_START 0x2c
58
59 #define AFI_FPCI_BAR0 0x30
60 #define AFI_FPCI_BAR1 0x34
61 #define AFI_FPCI_BAR2 0x38
62 #define AFI_FPCI_BAR3 0x3c
63 #define AFI_FPCI_BAR4 0x40
64 #define AFI_FPCI_BAR5 0x44
65
66 #define AFI_CACHE_BAR0_SZ 0x48
67 #define AFI_CACHE_BAR0_ST 0x4c
68 #define AFI_CACHE_BAR1_SZ 0x50
69 #define AFI_CACHE_BAR1_ST 0x54
70
71 #define AFI_MSI_BAR_SZ 0x60
72 #define AFI_MSI_FPCI_BAR_ST 0x64
73 #define AFI_MSI_AXI_BAR_ST 0x68
74
75 #define AFI_MSI_VEC0 0x6c
76 #define AFI_MSI_VEC1 0x70
77 #define AFI_MSI_VEC2 0x74
78 #define AFI_MSI_VEC3 0x78
79 #define AFI_MSI_VEC4 0x7c
80 #define AFI_MSI_VEC5 0x80
81 #define AFI_MSI_VEC6 0x84
82 #define AFI_MSI_VEC7 0x88
83
84 #define AFI_MSI_EN_VEC0 0x8c
85 #define AFI_MSI_EN_VEC1 0x90
86 #define AFI_MSI_EN_VEC2 0x94
87 #define AFI_MSI_EN_VEC3 0x98
88 #define AFI_MSI_EN_VEC4 0x9c
89 #define AFI_MSI_EN_VEC5 0xa0
90 #define AFI_MSI_EN_VEC6 0xa4
91 #define AFI_MSI_EN_VEC7 0xa8
92
93 #define AFI_CONFIGURATION 0xac
94 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
95
96 #define AFI_FPCI_ERROR_MASKS 0xb0
97
98 #define AFI_INTR_MASK 0xb4
99 #define AFI_INTR_MASK_INT_MASK (1 << 0)
100 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
101
102 #define AFI_INTR_CODE 0xb8
103 #define AFI_INTR_CODE_MASK 0xf
104 #define AFI_INTR_INI_SLAVE_ERROR 1
105 #define AFI_INTR_INI_DECODE_ERROR 2
106 #define AFI_INTR_TARGET_ABORT 3
107 #define AFI_INTR_MASTER_ABORT 4
108 #define AFI_INTR_INVALID_WRITE 5
109 #define AFI_INTR_LEGACY 6
110 #define AFI_INTR_FPCI_DECODE_ERROR 7
111 #define AFI_INTR_AXI_DECODE_ERROR 8
112 #define AFI_INTR_FPCI_TIMEOUT 9
113 #define AFI_INTR_PE_PRSNT_SENSE 10
114 #define AFI_INTR_PE_CLKREQ_SENSE 11
115 #define AFI_INTR_CLKCLAMP_SENSE 12
116 #define AFI_INTR_RDY4PD_SENSE 13
117 #define AFI_INTR_P2P_ERROR 14
118
119 #define AFI_INTR_SIGNATURE 0xbc
120 #define AFI_UPPER_FPCI_ADDRESS 0xc0
121 #define AFI_SM_INTR_ENABLE 0xc4
122 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
123 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
124 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
125 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
126 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
127 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
128 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
129 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
130
131 #define AFI_AFI_INTR_ENABLE 0xc8
132 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
133 #define AFI_INTR_EN_INI_DECERR (1 << 1)
134 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
135 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
136 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
137 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
138 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
139 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
140 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
141
142 #define AFI_PCIE_CONFIG 0x0f8
143 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
144 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
145 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
146 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
147 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
148 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
149 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401 (0x0 << 20)
150 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
151 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
152 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
153 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211 (0x1 << 20)
154 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
155 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111 (0x2 << 20)
156
157 #define AFI_FUSE 0x104
158 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
159
160 #define AFI_PEX0_CTRL 0x110
161 #define AFI_PEX1_CTRL 0x118
162 #define AFI_PEX2_CTRL 0x128
163 #define AFI_PEX_CTRL_RST (1 << 0)
164 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
165 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
166 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
167
168 #define AFI_PLLE_CONTROL 0x160
169 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
170 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
171
172 #define AFI_PEXBIAS_CTRL_0 0x168
173
174 #define RP_VEND_XP 0x00000f00
175 #define RP_VEND_XP_DL_UP (1 << 30)
176
177 #define RP_VEND_CTL2 0x00000fa8
178 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
179
180 #define RP_PRIV_MISC 0x00000fe0
181 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xe << 0)
182 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xf << 0)
183
184 #define RP_LINK_CONTROL_STATUS 0x00000090
185 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
186 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
187
188 #define PADS_CTL_SEL 0x0000009c
189
190 #define PADS_CTL 0x000000a0
191 #define PADS_CTL_IDDQ_1L (1 << 0)
192 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
193 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
194
195 #define PADS_PLL_CTL_TEGRA20 0x000000b8
196 #define PADS_PLL_CTL_TEGRA30 0x000000b4
197 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
198 #define PADS_PLL_CTL_LOCKDET (1 << 8)
199 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
200 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
201 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
202 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
203 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
204 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
205 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
206 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
207
208 #define PADS_REFCLK_CFG0 0x000000c8
209 #define PADS_REFCLK_CFG1 0x000000cc
210 #define PADS_REFCLK_BIAS 0x000000d0
211
212 /*
213 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
214 * entries, one entry per PCIe port. These field definitions and desired
215 * values aren't in the TRM, but do come from NVIDIA.
216 */
217 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
218 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
219 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
220 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
221
222 struct tegra_msi {
223 struct msi_controller chip;
224 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
225 struct irq_domain *domain;
226 unsigned long pages;
227 struct mutex lock;
228 u64 phys;
229 int irq;
230 };
231
232 /* used to differentiate between Tegra SoC generations */
233 struct tegra_pcie_soc {
234 unsigned int num_ports;
235 unsigned int msi_base_shift;
236 u32 pads_pll_ctl;
237 u32 tx_ref_sel;
238 u32 pads_refclk_cfg0;
239 u32 pads_refclk_cfg1;
240 bool has_pex_clkreq_en;
241 bool has_pex_bias_ctrl;
242 bool has_intr_prsnt_sense;
243 bool has_cml_clk;
244 bool has_gen2;
245 bool force_pca_enable;
246 bool program_uphy;
247 };
248
249 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
250 {
251 return container_of(chip, struct tegra_msi, chip);
252 }
253
254 struct tegra_pcie {
255 struct device *dev;
256
257 void __iomem *pads;
258 void __iomem *afi;
259 void __iomem *cfg;
260 int irq;
261
262 struct resource cs;
263 struct resource io;
264 struct resource pio;
265 struct resource mem;
266 struct resource prefetch;
267 struct resource busn;
268
269 struct {
270 resource_size_t mem;
271 resource_size_t io;
272 } offset;
273
274 struct clk *pex_clk;
275 struct clk *afi_clk;
276 struct clk *pll_e;
277 struct clk *cml_clk;
278
279 struct reset_control *pex_rst;
280 struct reset_control *afi_rst;
281 struct reset_control *pcie_xrst;
282
283 bool legacy_phy;
284 struct phy *phy;
285
286 struct tegra_msi msi;
287
288 struct list_head ports;
289 u32 xbar_config;
290
291 struct regulator_bulk_data *supplies;
292 unsigned int num_supplies;
293
294 const struct tegra_pcie_soc *soc;
295 struct dentry *debugfs;
296 };
297
298 struct tegra_pcie_port {
299 struct tegra_pcie *pcie;
300 struct device_node *np;
301 struct list_head list;
302 struct resource regs;
303 void __iomem *base;
304 unsigned int index;
305 unsigned int lanes;
306
307 struct phy **phys;
308 };
309
310 struct tegra_pcie_bus {
311 struct list_head list;
312 unsigned int nr;
313 };
314
315 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
316 unsigned long offset)
317 {
318 writel(value, pcie->afi + offset);
319 }
320
321 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
322 {
323 return readl(pcie->afi + offset);
324 }
325
326 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
327 unsigned long offset)
328 {
329 writel(value, pcie->pads + offset);
330 }
331
332 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
333 {
334 return readl(pcie->pads + offset);
335 }
336
337 /*
338 * The configuration space mapping on Tegra is somewhat similar to the ECAM
339 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
340 * register accesses are mapped:
341 *
342 * [27:24] extended register number
343 * [23:16] bus number
344 * [15:11] device number
345 * [10: 8] function number
346 * [ 7: 0] register number
347 *
348 * Mapping the whole extended configuration space would require 256 MiB of
349 * virtual address space, only a small part of which will actually be used.
350 *
351 * To work around this, a 4 KiB region is used to generate the required
352 * configuration transaction with relevant B:D:F and register offset values.
353 * This is achieved by dynamically programming base address and size of
354 * AFI_AXI_BAR used for end point config space mapping to make sure that the
355 * address (access to which generates correct config transaction) falls in
356 * this 4 KiB region.
357 */
358 static unsigned int tegra_pcie_conf_offset(u8 bus, unsigned int devfn,
359 unsigned int where)
360 {
361 return ((where & 0xf00) << 16) | (bus << 16) | (PCI_SLOT(devfn) << 11) |
362 (PCI_FUNC(devfn) << 8) | (where & 0xff);
363 }
364
365 static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
366 unsigned int devfn,
367 int where)
368 {
369 struct tegra_pcie *pcie = bus->sysdata;
370 void __iomem *addr = NULL;
371
372 if (bus->number == 0) {
373 unsigned int slot = PCI_SLOT(devfn);
374 struct tegra_pcie_port *port;
375
376 list_for_each_entry(port, &pcie->ports, list) {
377 if (port->index + 1 == slot) {
378 addr = port->base + (where & ~3);
379 break;
380 }
381 }
382 } else {
383 unsigned int offset;
384 u32 base;
385
386 offset = tegra_pcie_conf_offset(bus->number, devfn, where);
387
388 /* move 4 KiB window to offset within the FPCI region */
389 base = 0xfe100000 + ((offset & ~(SZ_4K - 1)) >> 8);
390 afi_writel(pcie, base, AFI_FPCI_BAR0);
391
392 /* move to correct offset within the 4 KiB page */
393 addr = pcie->cfg + (offset & (SZ_4K - 1));
394 }
395
396 return addr;
397 }
398
399 static int tegra_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
400 int where, int size, u32 *value)
401 {
402 if (bus->number == 0)
403 return pci_generic_config_read32(bus, devfn, where, size,
404 value);
405
406 return pci_generic_config_read(bus, devfn, where, size, value);
407 }
408
409 static int tegra_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
410 int where, int size, u32 value)
411 {
412 if (bus->number == 0)
413 return pci_generic_config_write32(bus, devfn, where, size,
414 value);
415
416 return pci_generic_config_write(bus, devfn, where, size, value);
417 }
418
419 static struct pci_ops tegra_pcie_ops = {
420 .map_bus = tegra_pcie_map_bus,
421 .read = tegra_pcie_config_read,
422 .write = tegra_pcie_config_write,
423 };
424
425 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
426 {
427 unsigned long ret = 0;
428
429 switch (port->index) {
430 case 0:
431 ret = AFI_PEX0_CTRL;
432 break;
433
434 case 1:
435 ret = AFI_PEX1_CTRL;
436 break;
437
438 case 2:
439 ret = AFI_PEX2_CTRL;
440 break;
441 }
442
443 return ret;
444 }
445
446 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
447 {
448 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
449 unsigned long value;
450
451 /* pulse reset signal */
452 value = afi_readl(port->pcie, ctrl);
453 value &= ~AFI_PEX_CTRL_RST;
454 afi_writel(port->pcie, value, ctrl);
455
456 usleep_range(1000, 2000);
457
458 value = afi_readl(port->pcie, ctrl);
459 value |= AFI_PEX_CTRL_RST;
460 afi_writel(port->pcie, value, ctrl);
461 }
462
463 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
464 {
465 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
466 const struct tegra_pcie_soc *soc = port->pcie->soc;
467 unsigned long value;
468
469 /* enable reference clock */
470 value = afi_readl(port->pcie, ctrl);
471 value |= AFI_PEX_CTRL_REFCLK_EN;
472
473 if (soc->has_pex_clkreq_en)
474 value |= AFI_PEX_CTRL_CLKREQ_EN;
475
476 value |= AFI_PEX_CTRL_OVERRIDE_EN;
477
478 afi_writel(port->pcie, value, ctrl);
479
480 tegra_pcie_port_reset(port);
481
482 if (soc->force_pca_enable) {
483 value = readl(port->base + RP_VEND_CTL2);
484 value |= RP_VEND_CTL2_PCA_ENABLE;
485 writel(value, port->base + RP_VEND_CTL2);
486 }
487 }
488
489 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
490 {
491 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
492 const struct tegra_pcie_soc *soc = port->pcie->soc;
493 unsigned long value;
494
495 /* assert port reset */
496 value = afi_readl(port->pcie, ctrl);
497 value &= ~AFI_PEX_CTRL_RST;
498 afi_writel(port->pcie, value, ctrl);
499
500 /* disable reference clock */
501 value = afi_readl(port->pcie, ctrl);
502
503 if (soc->has_pex_clkreq_en)
504 value &= ~AFI_PEX_CTRL_CLKREQ_EN;
505
506 value &= ~AFI_PEX_CTRL_REFCLK_EN;
507 afi_writel(port->pcie, value, ctrl);
508 }
509
510 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
511 {
512 struct tegra_pcie *pcie = port->pcie;
513 struct device *dev = pcie->dev;
514
515 devm_iounmap(dev, port->base);
516 devm_release_mem_region(dev, port->regs.start,
517 resource_size(&port->regs));
518 list_del(&port->list);
519 devm_kfree(dev, port);
520 }
521
522 /* Tegra PCIE root complex wrongly reports device class */
523 static void tegra_pcie_fixup_class(struct pci_dev *dev)
524 {
525 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
526 }
527 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
528 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
529 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
530 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
531
532 /* Tegra PCIE requires relaxed ordering */
533 static void tegra_pcie_relax_enable(struct pci_dev *dev)
534 {
535 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
536 }
537 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
538
539 static int tegra_pcie_request_resources(struct tegra_pcie *pcie)
540 {
541 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
542 struct list_head *windows = &host->windows;
543 struct device *dev = pcie->dev;
544 int err;
545
546 pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
547 pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
548 pci_add_resource_offset(windows, &pcie->prefetch, pcie->offset.mem);
549 pci_add_resource(windows, &pcie->busn);
550
551 err = devm_request_pci_bus_resources(dev, windows);
552 if (err < 0)
553 return err;
554
555 pci_remap_iospace(&pcie->pio, pcie->io.start);
556
557 return 0;
558 }
559
560 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
561 {
562 struct tegra_pcie *pcie = pdev->bus->sysdata;
563 int irq;
564
565 tegra_cpuidle_pcie_irqs_in_use();
566
567 irq = of_irq_parse_and_map_pci(pdev, slot, pin);
568 if (!irq)
569 irq = pcie->irq;
570
571 return irq;
572 }
573
574 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
575 {
576 const char *err_msg[] = {
577 "Unknown",
578 "AXI slave error",
579 "AXI decode error",
580 "Target abort",
581 "Master abort",
582 "Invalid write",
583 "Legacy interrupt",
584 "Response decoding error",
585 "AXI response decoding error",
586 "Transaction timeout",
587 "Slot present pin change",
588 "Slot clock request change",
589 "TMS clock ramp change",
590 "TMS ready for power down",
591 "Peer2Peer error",
592 };
593 struct tegra_pcie *pcie = arg;
594 struct device *dev = pcie->dev;
595 u32 code, signature;
596
597 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
598 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
599 afi_writel(pcie, 0, AFI_INTR_CODE);
600
601 if (code == AFI_INTR_LEGACY)
602 return IRQ_NONE;
603
604 if (code >= ARRAY_SIZE(err_msg))
605 code = 0;
606
607 /*
608 * do not pollute kernel log with master abort reports since they
609 * happen a lot during enumeration
610 */
611 if (code == AFI_INTR_MASTER_ABORT)
612 dev_dbg(dev, "%s, signature: %08x\n", err_msg[code], signature);
613 else
614 dev_err(dev, "%s, signature: %08x\n", err_msg[code], signature);
615
616 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
617 code == AFI_INTR_FPCI_DECODE_ERROR) {
618 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
619 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
620
621 if (code == AFI_INTR_MASTER_ABORT)
622 dev_dbg(dev, " FPCI address: %10llx\n", address);
623 else
624 dev_err(dev, " FPCI address: %10llx\n", address);
625 }
626
627 return IRQ_HANDLED;
628 }
629
630 /*
631 * FPCI map is as follows:
632 * - 0xfdfc000000: I/O space
633 * - 0xfdfe000000: type 0 configuration space
634 * - 0xfdff000000: type 1 configuration space
635 * - 0xfe00000000: type 0 extended configuration space
636 * - 0xfe10000000: type 1 extended configuration space
637 */
638 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
639 {
640 u32 fpci_bar, size, axi_address;
641
642 /* Bar 0: type 1 extended configuration space */
643 size = resource_size(&pcie->cs);
644 afi_writel(pcie, pcie->cs.start, AFI_AXI_BAR0_START);
645 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
646
647 /* Bar 1: downstream IO bar */
648 fpci_bar = 0xfdfc0000;
649 size = resource_size(&pcie->io);
650 axi_address = pcie->io.start;
651 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
652 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
653 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
654
655 /* Bar 2: prefetchable memory BAR */
656 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
657 size = resource_size(&pcie->prefetch);
658 axi_address = pcie->prefetch.start;
659 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
660 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
661 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
662
663 /* Bar 3: non prefetchable memory BAR */
664 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
665 size = resource_size(&pcie->mem);
666 axi_address = pcie->mem.start;
667 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
668 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
669 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
670
671 /* NULL out the remaining BARs as they are not used */
672 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
673 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
674 afi_writel(pcie, 0, AFI_FPCI_BAR4);
675
676 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
677 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
678 afi_writel(pcie, 0, AFI_FPCI_BAR5);
679
680 /* map all upstream transactions as uncached */
681 afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
682 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
683 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
684 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
685
686 /* MSI translations are setup only when needed */
687 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
688 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
689 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
690 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
691 }
692
693 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
694 {
695 const struct tegra_pcie_soc *soc = pcie->soc;
696 u32 value;
697
698 timeout = jiffies + msecs_to_jiffies(timeout);
699
700 while (time_before(jiffies, timeout)) {
701 value = pads_readl(pcie, soc->pads_pll_ctl);
702 if (value & PADS_PLL_CTL_LOCKDET)
703 return 0;
704 }
705
706 return -ETIMEDOUT;
707 }
708
709 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
710 {
711 struct device *dev = pcie->dev;
712 const struct tegra_pcie_soc *soc = pcie->soc;
713 u32 value;
714 int err;
715
716 /* initialize internal PHY, enable up to 16 PCIE lanes */
717 pads_writel(pcie, 0x0, PADS_CTL_SEL);
718
719 /* override IDDQ to 1 on all 4 lanes */
720 value = pads_readl(pcie, PADS_CTL);
721 value |= PADS_CTL_IDDQ_1L;
722 pads_writel(pcie, value, PADS_CTL);
723
724 /*
725 * Set up PHY PLL inputs select PLLE output as refclock,
726 * set TX ref sel to div10 (not div5).
727 */
728 value = pads_readl(pcie, soc->pads_pll_ctl);
729 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
730 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
731 pads_writel(pcie, value, soc->pads_pll_ctl);
732
733 /* reset PLL */
734 value = pads_readl(pcie, soc->pads_pll_ctl);
735 value &= ~PADS_PLL_CTL_RST_B4SM;
736 pads_writel(pcie, value, soc->pads_pll_ctl);
737
738 usleep_range(20, 100);
739
740 /* take PLL out of reset */
741 value = pads_readl(pcie, soc->pads_pll_ctl);
742 value |= PADS_PLL_CTL_RST_B4SM;
743 pads_writel(pcie, value, soc->pads_pll_ctl);
744
745 /* wait for the PLL to lock */
746 err = tegra_pcie_pll_wait(pcie, 500);
747 if (err < 0) {
748 dev_err(dev, "PLL failed to lock: %d\n", err);
749 return err;
750 }
751
752 /* turn off IDDQ override */
753 value = pads_readl(pcie, PADS_CTL);
754 value &= ~PADS_CTL_IDDQ_1L;
755 pads_writel(pcie, value, PADS_CTL);
756
757 /* enable TX/RX data */
758 value = pads_readl(pcie, PADS_CTL);
759 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
760 pads_writel(pcie, value, PADS_CTL);
761
762 return 0;
763 }
764
765 static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
766 {
767 const struct tegra_pcie_soc *soc = pcie->soc;
768 u32 value;
769
770 /* disable TX/RX data */
771 value = pads_readl(pcie, PADS_CTL);
772 value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
773 pads_writel(pcie, value, PADS_CTL);
774
775 /* override IDDQ */
776 value = pads_readl(pcie, PADS_CTL);
777 value |= PADS_CTL_IDDQ_1L;
778 pads_writel(pcie, value, PADS_CTL);
779
780 /* reset PLL */
781 value = pads_readl(pcie, soc->pads_pll_ctl);
782 value &= ~PADS_PLL_CTL_RST_B4SM;
783 pads_writel(pcie, value, soc->pads_pll_ctl);
784
785 usleep_range(20, 100);
786
787 return 0;
788 }
789
790 static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
791 {
792 struct device *dev = port->pcie->dev;
793 unsigned int i;
794 int err;
795
796 for (i = 0; i < port->lanes; i++) {
797 err = phy_power_on(port->phys[i]);
798 if (err < 0) {
799 dev_err(dev, "failed to power on PHY#%u: %d\n", i, err);
800 return err;
801 }
802 }
803
804 return 0;
805 }
806
807 static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
808 {
809 struct device *dev = port->pcie->dev;
810 unsigned int i;
811 int err;
812
813 for (i = 0; i < port->lanes; i++) {
814 err = phy_power_off(port->phys[i]);
815 if (err < 0) {
816 dev_err(dev, "failed to power off PHY#%u: %d\n", i,
817 err);
818 return err;
819 }
820 }
821
822 return 0;
823 }
824
825 static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
826 {
827 struct device *dev = pcie->dev;
828 const struct tegra_pcie_soc *soc = pcie->soc;
829 struct tegra_pcie_port *port;
830 int err;
831
832 if (pcie->legacy_phy) {
833 if (pcie->phy)
834 err = phy_power_on(pcie->phy);
835 else
836 err = tegra_pcie_phy_enable(pcie);
837
838 if (err < 0)
839 dev_err(dev, "failed to power on PHY: %d\n", err);
840
841 return err;
842 }
843
844 list_for_each_entry(port, &pcie->ports, list) {
845 err = tegra_pcie_port_phy_power_on(port);
846 if (err < 0) {
847 dev_err(dev,
848 "failed to power on PCIe port %u PHY: %d\n",
849 port->index, err);
850 return err;
851 }
852 }
853
854 /* Configure the reference clock driver */
855 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
856
857 if (soc->num_ports > 2)
858 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
859
860 return 0;
861 }
862
863 static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
864 {
865 struct device *dev = pcie->dev;
866 struct tegra_pcie_port *port;
867 int err;
868
869 if (pcie->legacy_phy) {
870 if (pcie->phy)
871 err = phy_power_off(pcie->phy);
872 else
873 err = tegra_pcie_phy_disable(pcie);
874
875 if (err < 0)
876 dev_err(dev, "failed to power off PHY: %d\n", err);
877
878 return err;
879 }
880
881 list_for_each_entry(port, &pcie->ports, list) {
882 err = tegra_pcie_port_phy_power_off(port);
883 if (err < 0) {
884 dev_err(dev,
885 "failed to power off PCIe port %u PHY: %d\n",
886 port->index, err);
887 return err;
888 }
889 }
890
891 return 0;
892 }
893
894 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
895 {
896 struct device *dev = pcie->dev;
897 const struct tegra_pcie_soc *soc = pcie->soc;
898 struct tegra_pcie_port *port;
899 unsigned long value;
900 int err;
901
902 /* enable PLL power down */
903 if (pcie->phy) {
904 value = afi_readl(pcie, AFI_PLLE_CONTROL);
905 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
906 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
907 afi_writel(pcie, value, AFI_PLLE_CONTROL);
908 }
909
910 /* power down PCIe slot clock bias pad */
911 if (soc->has_pex_bias_ctrl)
912 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
913
914 /* configure mode and disable all ports */
915 value = afi_readl(pcie, AFI_PCIE_CONFIG);
916 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
917 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
918
919 list_for_each_entry(port, &pcie->ports, list)
920 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
921
922 afi_writel(pcie, value, AFI_PCIE_CONFIG);
923
924 if (soc->has_gen2) {
925 value = afi_readl(pcie, AFI_FUSE);
926 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
927 afi_writel(pcie, value, AFI_FUSE);
928 } else {
929 value = afi_readl(pcie, AFI_FUSE);
930 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
931 afi_writel(pcie, value, AFI_FUSE);
932 }
933
934 if (soc->program_uphy) {
935 err = tegra_pcie_phy_power_on(pcie);
936 if (err < 0) {
937 dev_err(dev, "failed to power on PHY(s): %d\n", err);
938 return err;
939 }
940 }
941
942 /* take the PCIe interface module out of reset */
943 reset_control_deassert(pcie->pcie_xrst);
944
945 /* finally enable PCIe */
946 value = afi_readl(pcie, AFI_CONFIGURATION);
947 value |= AFI_CONFIGURATION_EN_FPCI;
948 afi_writel(pcie, value, AFI_CONFIGURATION);
949
950 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
951 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
952 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
953
954 if (soc->has_intr_prsnt_sense)
955 value |= AFI_INTR_EN_PRSNT_SENSE;
956
957 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
958 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
959
960 /* don't enable MSI for now, only when needed */
961 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
962
963 /* disable all exceptions */
964 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
965
966 return 0;
967 }
968
969 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
970 {
971 struct device *dev = pcie->dev;
972 const struct tegra_pcie_soc *soc = pcie->soc;
973 int err;
974
975 /* TODO: disable and unprepare clocks? */
976
977 if (soc->program_uphy) {
978 err = tegra_pcie_phy_power_off(pcie);
979 if (err < 0)
980 dev_err(dev, "failed to power off PHY(s): %d\n", err);
981 }
982
983 reset_control_assert(pcie->pcie_xrst);
984 reset_control_assert(pcie->afi_rst);
985 reset_control_assert(pcie->pex_rst);
986
987 if (!dev->pm_domain)
988 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
989
990 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
991 if (err < 0)
992 dev_warn(dev, "failed to disable regulators: %d\n", err);
993 }
994
995 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
996 {
997 struct device *dev = pcie->dev;
998 const struct tegra_pcie_soc *soc = pcie->soc;
999 int err;
1000
1001 reset_control_assert(pcie->pcie_xrst);
1002 reset_control_assert(pcie->afi_rst);
1003 reset_control_assert(pcie->pex_rst);
1004
1005 if (!dev->pm_domain)
1006 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1007
1008 /* enable regulators */
1009 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
1010 if (err < 0)
1011 dev_err(dev, "failed to enable regulators: %d\n", err);
1012
1013 if (dev->pm_domain) {
1014 err = clk_prepare_enable(pcie->pex_clk);
1015 if (err) {
1016 dev_err(dev, "failed to enable PEX clock: %d\n", err);
1017 return err;
1018 }
1019 reset_control_deassert(pcie->pex_rst);
1020 } else {
1021 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
1022 pcie->pex_clk,
1023 pcie->pex_rst);
1024 if (err) {
1025 dev_err(dev, "powerup sequence failed: %d\n", err);
1026 return err;
1027 }
1028 }
1029
1030 reset_control_deassert(pcie->afi_rst);
1031
1032 err = clk_prepare_enable(pcie->afi_clk);
1033 if (err < 0) {
1034 dev_err(dev, "failed to enable AFI clock: %d\n", err);
1035 return err;
1036 }
1037
1038 if (soc->has_cml_clk) {
1039 err = clk_prepare_enable(pcie->cml_clk);
1040 if (err < 0) {
1041 dev_err(dev, "failed to enable CML clock: %d\n", err);
1042 return err;
1043 }
1044 }
1045
1046 err = clk_prepare_enable(pcie->pll_e);
1047 if (err < 0) {
1048 dev_err(dev, "failed to enable PLLE clock: %d\n", err);
1049 return err;
1050 }
1051
1052 return 0;
1053 }
1054
1055 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
1056 {
1057 struct device *dev = pcie->dev;
1058 const struct tegra_pcie_soc *soc = pcie->soc;
1059
1060 pcie->pex_clk = devm_clk_get(dev, "pex");
1061 if (IS_ERR(pcie->pex_clk))
1062 return PTR_ERR(pcie->pex_clk);
1063
1064 pcie->afi_clk = devm_clk_get(dev, "afi");
1065 if (IS_ERR(pcie->afi_clk))
1066 return PTR_ERR(pcie->afi_clk);
1067
1068 pcie->pll_e = devm_clk_get(dev, "pll_e");
1069 if (IS_ERR(pcie->pll_e))
1070 return PTR_ERR(pcie->pll_e);
1071
1072 if (soc->has_cml_clk) {
1073 pcie->cml_clk = devm_clk_get(dev, "cml");
1074 if (IS_ERR(pcie->cml_clk))
1075 return PTR_ERR(pcie->cml_clk);
1076 }
1077
1078 return 0;
1079 }
1080
1081 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1082 {
1083 struct device *dev = pcie->dev;
1084
1085 pcie->pex_rst = devm_reset_control_get_exclusive(dev, "pex");
1086 if (IS_ERR(pcie->pex_rst))
1087 return PTR_ERR(pcie->pex_rst);
1088
1089 pcie->afi_rst = devm_reset_control_get_exclusive(dev, "afi");
1090 if (IS_ERR(pcie->afi_rst))
1091 return PTR_ERR(pcie->afi_rst);
1092
1093 pcie->pcie_xrst = devm_reset_control_get_exclusive(dev, "pcie_x");
1094 if (IS_ERR(pcie->pcie_xrst))
1095 return PTR_ERR(pcie->pcie_xrst);
1096
1097 return 0;
1098 }
1099
1100 static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
1101 {
1102 struct device *dev = pcie->dev;
1103 int err;
1104
1105 pcie->phy = devm_phy_optional_get(dev, "pcie");
1106 if (IS_ERR(pcie->phy)) {
1107 err = PTR_ERR(pcie->phy);
1108 dev_err(dev, "failed to get PHY: %d\n", err);
1109 return err;
1110 }
1111
1112 err = phy_init(pcie->phy);
1113 if (err < 0) {
1114 dev_err(dev, "failed to initialize PHY: %d\n", err);
1115 return err;
1116 }
1117
1118 pcie->legacy_phy = true;
1119
1120 return 0;
1121 }
1122
1123 static struct phy *devm_of_phy_optional_get_index(struct device *dev,
1124 struct device_node *np,
1125 const char *consumer,
1126 unsigned int index)
1127 {
1128 struct phy *phy;
1129 char *name;
1130
1131 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index);
1132 if (!name)
1133 return ERR_PTR(-ENOMEM);
1134
1135 phy = devm_of_phy_get(dev, np, name);
1136 kfree(name);
1137
1138 if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV)
1139 phy = NULL;
1140
1141 return phy;
1142 }
1143
1144 static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
1145 {
1146 struct device *dev = port->pcie->dev;
1147 struct phy *phy;
1148 unsigned int i;
1149 int err;
1150
1151 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
1152 if (!port->phys)
1153 return -ENOMEM;
1154
1155 for (i = 0; i < port->lanes; i++) {
1156 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1157 if (IS_ERR(phy)) {
1158 dev_err(dev, "failed to get PHY#%u: %ld\n", i,
1159 PTR_ERR(phy));
1160 return PTR_ERR(phy);
1161 }
1162
1163 err = phy_init(phy);
1164 if (err < 0) {
1165 dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
1166 err);
1167 return err;
1168 }
1169
1170 port->phys[i] = phy;
1171 }
1172
1173 return 0;
1174 }
1175
1176 static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
1177 {
1178 const struct tegra_pcie_soc *soc = pcie->soc;
1179 struct device_node *np = pcie->dev->of_node;
1180 struct tegra_pcie_port *port;
1181 int err;
1182
1183 if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL)
1184 return tegra_pcie_phys_get_legacy(pcie);
1185
1186 list_for_each_entry(port, &pcie->ports, list) {
1187 err = tegra_pcie_port_get_phys(port);
1188 if (err < 0)
1189 return err;
1190 }
1191
1192 return 0;
1193 }
1194
1195 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1196 {
1197 struct device *dev = pcie->dev;
1198 struct platform_device *pdev = to_platform_device(dev);
1199 struct resource *pads, *afi, *res;
1200 const struct tegra_pcie_soc *soc = pcie->soc;
1201 int err;
1202
1203 err = tegra_pcie_clocks_get(pcie);
1204 if (err) {
1205 dev_err(dev, "failed to get clocks: %d\n", err);
1206 return err;
1207 }
1208
1209 err = tegra_pcie_resets_get(pcie);
1210 if (err) {
1211 dev_err(dev, "failed to get resets: %d\n", err);
1212 return err;
1213 }
1214
1215 if (soc->program_uphy) {
1216 err = tegra_pcie_phys_get(pcie);
1217 if (err < 0) {
1218 dev_err(dev, "failed to get PHYs: %d\n", err);
1219 return err;
1220 }
1221 }
1222
1223 err = tegra_pcie_power_on(pcie);
1224 if (err) {
1225 dev_err(dev, "failed to power up: %d\n", err);
1226 return err;
1227 }
1228
1229 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1230 pcie->pads = devm_ioremap_resource(dev, pads);
1231 if (IS_ERR(pcie->pads)) {
1232 err = PTR_ERR(pcie->pads);
1233 goto poweroff;
1234 }
1235
1236 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1237 pcie->afi = devm_ioremap_resource(dev, afi);
1238 if (IS_ERR(pcie->afi)) {
1239 err = PTR_ERR(pcie->afi);
1240 goto poweroff;
1241 }
1242
1243 /* request configuration space, but remap later, on demand */
1244 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
1245 if (!res) {
1246 err = -EADDRNOTAVAIL;
1247 goto poweroff;
1248 }
1249
1250 pcie->cs = *res;
1251
1252 /* constrain configuration space to 4 KiB */
1253 pcie->cs.end = pcie->cs.start + SZ_4K - 1;
1254
1255 pcie->cfg = devm_ioremap_resource(dev, &pcie->cs);
1256 if (IS_ERR(pcie->cfg)) {
1257 err = PTR_ERR(pcie->cfg);
1258 goto poweroff;
1259 }
1260
1261 /* request interrupt */
1262 err = platform_get_irq_byname(pdev, "intr");
1263 if (err < 0) {
1264 dev_err(dev, "failed to get IRQ: %d\n", err);
1265 goto poweroff;
1266 }
1267
1268 pcie->irq = err;
1269
1270 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1271 if (err) {
1272 dev_err(dev, "failed to register IRQ: %d\n", err);
1273 goto poweroff;
1274 }
1275
1276 return 0;
1277
1278 poweroff:
1279 tegra_pcie_power_off(pcie);
1280 return err;
1281 }
1282
1283 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1284 {
1285 struct device *dev = pcie->dev;
1286 const struct tegra_pcie_soc *soc = pcie->soc;
1287 int err;
1288
1289 if (pcie->irq > 0)
1290 free_irq(pcie->irq, pcie);
1291
1292 tegra_pcie_power_off(pcie);
1293
1294 if (soc->program_uphy) {
1295 err = phy_exit(pcie->phy);
1296 if (err < 0)
1297 dev_err(dev, "failed to teardown PHY: %d\n", err);
1298 }
1299
1300 return 0;
1301 }
1302
1303 static int tegra_msi_alloc(struct tegra_msi *chip)
1304 {
1305 int msi;
1306
1307 mutex_lock(&chip->lock);
1308
1309 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1310 if (msi < INT_PCI_MSI_NR)
1311 set_bit(msi, chip->used);
1312 else
1313 msi = -ENOSPC;
1314
1315 mutex_unlock(&chip->lock);
1316
1317 return msi;
1318 }
1319
1320 static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1321 {
1322 struct device *dev = chip->chip.dev;
1323
1324 mutex_lock(&chip->lock);
1325
1326 if (!test_bit(irq, chip->used))
1327 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1328 else
1329 clear_bit(irq, chip->used);
1330
1331 mutex_unlock(&chip->lock);
1332 }
1333
1334 static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1335 {
1336 struct tegra_pcie *pcie = data;
1337 struct device *dev = pcie->dev;
1338 struct tegra_msi *msi = &pcie->msi;
1339 unsigned int i, processed = 0;
1340
1341 for (i = 0; i < 8; i++) {
1342 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1343
1344 while (reg) {
1345 unsigned int offset = find_first_bit(&reg, 32);
1346 unsigned int index = i * 32 + offset;
1347 unsigned int irq;
1348
1349 /* clear the interrupt */
1350 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1351
1352 irq = irq_find_mapping(msi->domain, index);
1353 if (irq) {
1354 if (test_bit(index, msi->used))
1355 generic_handle_irq(irq);
1356 else
1357 dev_info(dev, "unhandled MSI\n");
1358 } else {
1359 /*
1360 * that's weird who triggered this?
1361 * just clear it
1362 */
1363 dev_info(dev, "unexpected MSI\n");
1364 }
1365
1366 /* see if there's any more pending in this vector */
1367 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1368
1369 processed++;
1370 }
1371 }
1372
1373 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1374 }
1375
1376 static int tegra_msi_setup_irq(struct msi_controller *chip,
1377 struct pci_dev *pdev, struct msi_desc *desc)
1378 {
1379 struct tegra_msi *msi = to_tegra_msi(chip);
1380 struct msi_msg msg;
1381 unsigned int irq;
1382 int hwirq;
1383
1384 hwirq = tegra_msi_alloc(msi);
1385 if (hwirq < 0)
1386 return hwirq;
1387
1388 irq = irq_create_mapping(msi->domain, hwirq);
1389 if (!irq) {
1390 tegra_msi_free(msi, hwirq);
1391 return -EINVAL;
1392 }
1393
1394 irq_set_msi_desc(irq, desc);
1395
1396 msg.address_lo = lower_32_bits(msi->phys);
1397 msg.address_hi = upper_32_bits(msi->phys);
1398 msg.data = hwirq;
1399
1400 pci_write_msi_msg(irq, &msg);
1401
1402 return 0;
1403 }
1404
1405 static void tegra_msi_teardown_irq(struct msi_controller *chip,
1406 unsigned int irq)
1407 {
1408 struct tegra_msi *msi = to_tegra_msi(chip);
1409 struct irq_data *d = irq_get_irq_data(irq);
1410 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1411
1412 irq_dispose_mapping(irq);
1413 tegra_msi_free(msi, hwirq);
1414 }
1415
1416 static struct irq_chip tegra_msi_irq_chip = {
1417 .name = "Tegra PCIe MSI",
1418 .irq_enable = pci_msi_unmask_irq,
1419 .irq_disable = pci_msi_mask_irq,
1420 .irq_mask = pci_msi_mask_irq,
1421 .irq_unmask = pci_msi_unmask_irq,
1422 };
1423
1424 static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1425 irq_hw_number_t hwirq)
1426 {
1427 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1428 irq_set_chip_data(irq, domain->host_data);
1429
1430 tegra_cpuidle_pcie_irqs_in_use();
1431
1432 return 0;
1433 }
1434
1435 static const struct irq_domain_ops msi_domain_ops = {
1436 .map = tegra_msi_map,
1437 };
1438
1439 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1440 {
1441 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1442 struct platform_device *pdev = to_platform_device(pcie->dev);
1443 const struct tegra_pcie_soc *soc = pcie->soc;
1444 struct tegra_msi *msi = &pcie->msi;
1445 struct device *dev = pcie->dev;
1446 int err;
1447 u32 reg;
1448
1449 mutex_init(&msi->lock);
1450
1451 msi->chip.dev = dev;
1452 msi->chip.setup_irq = tegra_msi_setup_irq;
1453 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1454
1455 msi->domain = irq_domain_add_linear(dev->of_node, INT_PCI_MSI_NR,
1456 &msi_domain_ops, &msi->chip);
1457 if (!msi->domain) {
1458 dev_err(dev, "failed to create IRQ domain\n");
1459 return -ENOMEM;
1460 }
1461
1462 err = platform_get_irq_byname(pdev, "msi");
1463 if (err < 0) {
1464 dev_err(dev, "failed to get IRQ: %d\n", err);
1465 goto err;
1466 }
1467
1468 msi->irq = err;
1469
1470 err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
1471 tegra_msi_irq_chip.name, pcie);
1472 if (err < 0) {
1473 dev_err(dev, "failed to request IRQ: %d\n", err);
1474 goto err;
1475 }
1476
1477 /* setup AFI/FPCI range */
1478 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1479 msi->phys = virt_to_phys((void *)msi->pages);
1480
1481 afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1482 afi_writel(pcie, msi->phys, AFI_MSI_AXI_BAR_ST);
1483 /* this register is in 4K increments */
1484 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1485
1486 /* enable all MSI vectors */
1487 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1488 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1489 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1490 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1491 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1492 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1493 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1494 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1495
1496 /* and unmask the MSI interrupt */
1497 reg = afi_readl(pcie, AFI_INTR_MASK);
1498 reg |= AFI_INTR_MASK_MSI_MASK;
1499 afi_writel(pcie, reg, AFI_INTR_MASK);
1500
1501 host->msi = &msi->chip;
1502
1503 return 0;
1504
1505 err:
1506 irq_domain_remove(msi->domain);
1507 return err;
1508 }
1509
1510 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1511 {
1512 struct tegra_msi *msi = &pcie->msi;
1513 unsigned int i, irq;
1514 u32 value;
1515
1516 /* mask the MSI interrupt */
1517 value = afi_readl(pcie, AFI_INTR_MASK);
1518 value &= ~AFI_INTR_MASK_MSI_MASK;
1519 afi_writel(pcie, value, AFI_INTR_MASK);
1520
1521 /* disable all MSI vectors */
1522 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1523 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1524 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1525 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1526 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1527 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1528 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1529 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1530
1531 free_pages(msi->pages, 0);
1532
1533 if (msi->irq > 0)
1534 free_irq(msi->irq, pcie);
1535
1536 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1537 irq = irq_find_mapping(msi->domain, i);
1538 if (irq > 0)
1539 irq_dispose_mapping(irq);
1540 }
1541
1542 irq_domain_remove(msi->domain);
1543
1544 return 0;
1545 }
1546
1547 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1548 u32 *xbar)
1549 {
1550 struct device *dev = pcie->dev;
1551 struct device_node *np = dev->of_node;
1552
1553 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
1554 switch (lanes) {
1555 case 0x010004:
1556 dev_info(dev, "4x1, 1x1 configuration\n");
1557 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_401;
1558 return 0;
1559
1560 case 0x010102:
1561 dev_info(dev, "2x1, 1X1, 1x1 configuration\n");
1562 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;
1563 return 0;
1564
1565 case 0x010101:
1566 dev_info(dev, "1x1, 1x1, 1x1 configuration\n");
1567 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_111;
1568 return 0;
1569
1570 default:
1571 dev_info(dev, "wrong configuration updated in DT, "
1572 "switching to default 2x1, 1x1, 1x1 "
1573 "configuration\n");
1574 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;
1575 return 0;
1576 }
1577 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
1578 of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1579 switch (lanes) {
1580 case 0x0000104:
1581 dev_info(dev, "4x1, 1x1 configuration\n");
1582 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
1583 return 0;
1584
1585 case 0x0000102:
1586 dev_info(dev, "2x1, 1x1 configuration\n");
1587 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
1588 return 0;
1589 }
1590 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1591 switch (lanes) {
1592 case 0x00000204:
1593 dev_info(dev, "4x1, 2x1 configuration\n");
1594 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
1595 return 0;
1596
1597 case 0x00020202:
1598 dev_info(dev, "2x3 configuration\n");
1599 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
1600 return 0;
1601
1602 case 0x00010104:
1603 dev_info(dev, "4x1, 1x2 configuration\n");
1604 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
1605 return 0;
1606 }
1607 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1608 switch (lanes) {
1609 case 0x00000004:
1610 dev_info(dev, "single-mode configuration\n");
1611 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1612 return 0;
1613
1614 case 0x00000202:
1615 dev_info(dev, "dual-mode configuration\n");
1616 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1617 return 0;
1618 }
1619 }
1620
1621 return -EINVAL;
1622 }
1623
1624 /*
1625 * Check whether a given set of supplies is available in a device tree node.
1626 * This is used to check whether the new or the legacy device tree bindings
1627 * should be used.
1628 */
1629 static bool of_regulator_bulk_available(struct device_node *np,
1630 struct regulator_bulk_data *supplies,
1631 unsigned int num_supplies)
1632 {
1633 char property[32];
1634 unsigned int i;
1635
1636 for (i = 0; i < num_supplies; i++) {
1637 snprintf(property, 32, "%s-supply", supplies[i].supply);
1638
1639 if (of_find_property(np, property, NULL) == NULL)
1640 return false;
1641 }
1642
1643 return true;
1644 }
1645
1646 /*
1647 * Old versions of the device tree binding for this device used a set of power
1648 * supplies that didn't match the hardware inputs. This happened to work for a
1649 * number of cases but is not future proof. However to preserve backwards-
1650 * compatibility with old device trees, this function will try to use the old
1651 * set of supplies.
1652 */
1653 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1654 {
1655 struct device *dev = pcie->dev;
1656 struct device_node *np = dev->of_node;
1657
1658 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1659 pcie->num_supplies = 3;
1660 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1661 pcie->num_supplies = 2;
1662
1663 if (pcie->num_supplies == 0) {
1664 dev_err(dev, "device %pOF not supported in legacy mode\n", np);
1665 return -ENODEV;
1666 }
1667
1668 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1669 sizeof(*pcie->supplies),
1670 GFP_KERNEL);
1671 if (!pcie->supplies)
1672 return -ENOMEM;
1673
1674 pcie->supplies[0].supply = "pex-clk";
1675 pcie->supplies[1].supply = "vdd";
1676
1677 if (pcie->num_supplies > 2)
1678 pcie->supplies[2].supply = "avdd";
1679
1680 return devm_regulator_bulk_get(dev, pcie->num_supplies, pcie->supplies);
1681 }
1682
1683 /*
1684 * Obtains the list of regulators required for a particular generation of the
1685 * IP block.
1686 *
1687 * This would've been nice to do simply by providing static tables for use
1688 * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky
1689 * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB)
1690 * and either seems to be optional depending on which ports are being used.
1691 */
1692 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
1693 {
1694 struct device *dev = pcie->dev;
1695 struct device_node *np = dev->of_node;
1696 unsigned int i = 0;
1697
1698 if (of_device_is_compatible(np, "nvidia,tegra186-pcie")) {
1699 pcie->num_supplies = 4;
1700
1701 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1702 sizeof(*pcie->supplies),
1703 GFP_KERNEL);
1704 if (!pcie->supplies)
1705 return -ENOMEM;
1706
1707 pcie->supplies[i++].supply = "dvdd-pex";
1708 pcie->supplies[i++].supply = "hvdd-pex-pll";
1709 pcie->supplies[i++].supply = "hvdd-pex";
1710 pcie->supplies[i++].supply = "vddio-pexctl-aud";
1711 } else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
1712 pcie->num_supplies = 6;
1713
1714 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1715 sizeof(*pcie->supplies),
1716 GFP_KERNEL);
1717 if (!pcie->supplies)
1718 return -ENOMEM;
1719
1720 pcie->supplies[i++].supply = "avdd-pll-uerefe";
1721 pcie->supplies[i++].supply = "hvddio-pex";
1722 pcie->supplies[i++].supply = "dvddio-pex";
1723 pcie->supplies[i++].supply = "dvdd-pex-pll";
1724 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1725 pcie->supplies[i++].supply = "vddio-pex-ctl";
1726 } else if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1727 pcie->num_supplies = 7;
1728
1729 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1730 sizeof(*pcie->supplies),
1731 GFP_KERNEL);
1732 if (!pcie->supplies)
1733 return -ENOMEM;
1734
1735 pcie->supplies[i++].supply = "avddio-pex";
1736 pcie->supplies[i++].supply = "dvddio-pex";
1737 pcie->supplies[i++].supply = "avdd-pex-pll";
1738 pcie->supplies[i++].supply = "hvdd-pex";
1739 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1740 pcie->supplies[i++].supply = "vddio-pex-ctl";
1741 pcie->supplies[i++].supply = "avdd-pll-erefe";
1742 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1743 bool need_pexa = false, need_pexb = false;
1744
1745 /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */
1746 if (lane_mask & 0x0f)
1747 need_pexa = true;
1748
1749 /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */
1750 if (lane_mask & 0x30)
1751 need_pexb = true;
1752
1753 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
1754 (need_pexb ? 2 : 0);
1755
1756 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1757 sizeof(*pcie->supplies),
1758 GFP_KERNEL);
1759 if (!pcie->supplies)
1760 return -ENOMEM;
1761
1762 pcie->supplies[i++].supply = "avdd-pex-pll";
1763 pcie->supplies[i++].supply = "hvdd-pex";
1764 pcie->supplies[i++].supply = "vddio-pex-ctl";
1765 pcie->supplies[i++].supply = "avdd-plle";
1766
1767 if (need_pexa) {
1768 pcie->supplies[i++].supply = "avdd-pexa";
1769 pcie->supplies[i++].supply = "vdd-pexa";
1770 }
1771
1772 if (need_pexb) {
1773 pcie->supplies[i++].supply = "avdd-pexb";
1774 pcie->supplies[i++].supply = "vdd-pexb";
1775 }
1776 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1777 pcie->num_supplies = 5;
1778
1779 pcie->supplies = devm_kcalloc(dev, pcie->num_supplies,
1780 sizeof(*pcie->supplies),
1781 GFP_KERNEL);
1782 if (!pcie->supplies)
1783 return -ENOMEM;
1784
1785 pcie->supplies[0].supply = "avdd-pex";
1786 pcie->supplies[1].supply = "vdd-pex";
1787 pcie->supplies[2].supply = "avdd-pex-pll";
1788 pcie->supplies[3].supply = "avdd-plle";
1789 pcie->supplies[4].supply = "vddio-pex-clk";
1790 }
1791
1792 if (of_regulator_bulk_available(dev->of_node, pcie->supplies,
1793 pcie->num_supplies))
1794 return devm_regulator_bulk_get(dev, pcie->num_supplies,
1795 pcie->supplies);
1796
1797 /*
1798 * If not all regulators are available for this new scheme, assume
1799 * that the device tree complies with an older version of the device
1800 * tree binding.
1801 */
1802 dev_info(dev, "using legacy DT binding for power supplies\n");
1803
1804 devm_kfree(dev, pcie->supplies);
1805 pcie->num_supplies = 0;
1806
1807 return tegra_pcie_get_legacy_regulators(pcie);
1808 }
1809
1810 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1811 {
1812 struct device *dev = pcie->dev;
1813 struct device_node *np = dev->of_node, *port;
1814 const struct tegra_pcie_soc *soc = pcie->soc;
1815 struct of_pci_range_parser parser;
1816 struct of_pci_range range;
1817 u32 lanes = 0, mask = 0;
1818 unsigned int lane = 0;
1819 struct resource res;
1820 int err;
1821
1822 if (of_pci_range_parser_init(&parser, np)) {
1823 dev_err(dev, "missing \"ranges\" property\n");
1824 return -EINVAL;
1825 }
1826
1827 for_each_of_pci_range(&parser, &range) {
1828 err = of_pci_range_to_resource(&range, np, &res);
1829 if (err < 0)
1830 return err;
1831
1832 switch (res.flags & IORESOURCE_TYPE_BITS) {
1833 case IORESOURCE_IO:
1834 /* Track the bus -> CPU I/O mapping offset. */
1835 pcie->offset.io = res.start - range.pci_addr;
1836
1837 memcpy(&pcie->pio, &res, sizeof(res));
1838 pcie->pio.name = np->full_name;
1839
1840 /*
1841 * The Tegra PCIe host bridge uses this to program the
1842 * mapping of the I/O space to the physical address,
1843 * so we override the .start and .end fields here that
1844 * of_pci_range_to_resource() converted to I/O space.
1845 * We also set the IORESOURCE_MEM type to clarify that
1846 * the resource is in the physical memory space.
1847 */
1848 pcie->io.start = range.cpu_addr;
1849 pcie->io.end = range.cpu_addr + range.size - 1;
1850 pcie->io.flags = IORESOURCE_MEM;
1851 pcie->io.name = "I/O";
1852
1853 memcpy(&res, &pcie->io, sizeof(res));
1854 break;
1855
1856 case IORESOURCE_MEM:
1857 /*
1858 * Track the bus -> CPU memory mapping offset. This
1859 * assumes that the prefetchable and non-prefetchable
1860 * regions will be the last of type IORESOURCE_MEM in
1861 * the ranges property.
1862 * */
1863 pcie->offset.mem = res.start - range.pci_addr;
1864
1865 if (res.flags & IORESOURCE_PREFETCH) {
1866 memcpy(&pcie->prefetch, &res, sizeof(res));
1867 pcie->prefetch.name = "prefetchable";
1868 } else {
1869 memcpy(&pcie->mem, &res, sizeof(res));
1870 pcie->mem.name = "non-prefetchable";
1871 }
1872 break;
1873 }
1874 }
1875
1876 err = of_pci_parse_bus_range(np, &pcie->busn);
1877 if (err < 0) {
1878 dev_err(dev, "failed to parse ranges property: %d\n", err);
1879 pcie->busn.name = np->name;
1880 pcie->busn.start = 0;
1881 pcie->busn.end = 0xff;
1882 pcie->busn.flags = IORESOURCE_BUS;
1883 }
1884
1885 /* parse root ports */
1886 for_each_child_of_node(np, port) {
1887 struct tegra_pcie_port *rp;
1888 unsigned int index;
1889 u32 value;
1890
1891 err = of_pci_get_devfn(port);
1892 if (err < 0) {
1893 dev_err(dev, "failed to parse address: %d\n", err);
1894 return err;
1895 }
1896
1897 index = PCI_SLOT(err);
1898
1899 if (index < 1 || index > soc->num_ports) {
1900 dev_err(dev, "invalid port number: %d\n", index);
1901 return -EINVAL;
1902 }
1903
1904 index--;
1905
1906 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1907 if (err < 0) {
1908 dev_err(dev, "failed to parse # of lanes: %d\n",
1909 err);
1910 return err;
1911 }
1912
1913 if (value > 16) {
1914 dev_err(dev, "invalid # of lanes: %u\n", value);
1915 return -EINVAL;
1916 }
1917
1918 lanes |= value << (index << 3);
1919
1920 if (!of_device_is_available(port)) {
1921 lane += value;
1922 continue;
1923 }
1924
1925 mask |= ((1 << value) - 1) << lane;
1926 lane += value;
1927
1928 rp = devm_kzalloc(dev, sizeof(*rp), GFP_KERNEL);
1929 if (!rp)
1930 return -ENOMEM;
1931
1932 err = of_address_to_resource(port, 0, &rp->regs);
1933 if (err < 0) {
1934 dev_err(dev, "failed to parse address: %d\n", err);
1935 return err;
1936 }
1937
1938 INIT_LIST_HEAD(&rp->list);
1939 rp->index = index;
1940 rp->lanes = value;
1941 rp->pcie = pcie;
1942 rp->np = port;
1943
1944 rp->base = devm_pci_remap_cfg_resource(dev, &rp->regs);
1945 if (IS_ERR(rp->base))
1946 return PTR_ERR(rp->base);
1947
1948 list_add_tail(&rp->list, &pcie->ports);
1949 }
1950
1951 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1952 if (err < 0) {
1953 dev_err(dev, "invalid lane configuration\n");
1954 return err;
1955 }
1956
1957 err = tegra_pcie_get_regulators(pcie, mask);
1958 if (err < 0)
1959 return err;
1960
1961 return 0;
1962 }
1963
1964 /*
1965 * FIXME: If there are no PCIe cards attached, then calling this function
1966 * can result in the increase of the bootup time as there are big timeout
1967 * loops.
1968 */
1969 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1970 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1971 {
1972 struct device *dev = port->pcie->dev;
1973 unsigned int retries = 3;
1974 unsigned long value;
1975
1976 /* override presence detection */
1977 value = readl(port->base + RP_PRIV_MISC);
1978 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
1979 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
1980 writel(value, port->base + RP_PRIV_MISC);
1981
1982 do {
1983 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1984
1985 do {
1986 value = readl(port->base + RP_VEND_XP);
1987
1988 if (value & RP_VEND_XP_DL_UP)
1989 break;
1990
1991 usleep_range(1000, 2000);
1992 } while (--timeout);
1993
1994 if (!timeout) {
1995 dev_err(dev, "link %u down, retrying\n", port->index);
1996 goto retry;
1997 }
1998
1999 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
2000
2001 do {
2002 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2003
2004 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2005 return true;
2006
2007 usleep_range(1000, 2000);
2008 } while (--timeout);
2009
2010 retry:
2011 tegra_pcie_port_reset(port);
2012 } while (--retries);
2013
2014 return false;
2015 }
2016
2017 static void tegra_pcie_enable_ports(struct tegra_pcie *pcie)
2018 {
2019 struct device *dev = pcie->dev;
2020 struct tegra_pcie_port *port, *tmp;
2021
2022 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2023 dev_info(dev, "probing port %u, using %u lanes\n",
2024 port->index, port->lanes);
2025
2026 tegra_pcie_port_enable(port);
2027
2028 if (tegra_pcie_port_check_link(port))
2029 continue;
2030
2031 dev_info(dev, "link %u down, ignoring\n", port->index);
2032
2033 tegra_pcie_port_disable(port);
2034 tegra_pcie_port_free(port);
2035 }
2036 }
2037
2038 static const struct tegra_pcie_soc tegra20_pcie = {
2039 .num_ports = 2,
2040 .msi_base_shift = 0,
2041 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
2042 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
2043 .pads_refclk_cfg0 = 0xfa5cfa5c,
2044 .has_pex_clkreq_en = false,
2045 .has_pex_bias_ctrl = false,
2046 .has_intr_prsnt_sense = false,
2047 .has_cml_clk = false,
2048 .has_gen2 = false,
2049 .force_pca_enable = false,
2050 .program_uphy = true,
2051 };
2052
2053 static const struct tegra_pcie_soc tegra30_pcie = {
2054 .num_ports = 3,
2055 .msi_base_shift = 8,
2056 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2057 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2058 .pads_refclk_cfg0 = 0xfa5cfa5c,
2059 .pads_refclk_cfg1 = 0xfa5cfa5c,
2060 .has_pex_clkreq_en = true,
2061 .has_pex_bias_ctrl = true,
2062 .has_intr_prsnt_sense = true,
2063 .has_cml_clk = true,
2064 .has_gen2 = false,
2065 .force_pca_enable = false,
2066 .program_uphy = true,
2067 };
2068
2069 static const struct tegra_pcie_soc tegra124_pcie = {
2070 .num_ports = 2,
2071 .msi_base_shift = 8,
2072 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2073 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2074 .pads_refclk_cfg0 = 0x44ac44ac,
2075 .has_pex_clkreq_en = true,
2076 .has_pex_bias_ctrl = true,
2077 .has_intr_prsnt_sense = true,
2078 .has_cml_clk = true,
2079 .has_gen2 = true,
2080 .force_pca_enable = false,
2081 .program_uphy = true,
2082 };
2083
2084 static const struct tegra_pcie_soc tegra210_pcie = {
2085 .num_ports = 2,
2086 .msi_base_shift = 8,
2087 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2088 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2089 .pads_refclk_cfg0 = 0x90b890b8,
2090 .has_pex_clkreq_en = true,
2091 .has_pex_bias_ctrl = true,
2092 .has_intr_prsnt_sense = true,
2093 .has_cml_clk = true,
2094 .has_gen2 = true,
2095 .force_pca_enable = true,
2096 .program_uphy = true,
2097 };
2098
2099 static const struct tegra_pcie_soc tegra186_pcie = {
2100 .num_ports = 3,
2101 .msi_base_shift = 8,
2102 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2103 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2104 .pads_refclk_cfg0 = 0x80b880b8,
2105 .pads_refclk_cfg1 = 0x000480b8,
2106 .has_pex_clkreq_en = true,
2107 .has_pex_bias_ctrl = true,
2108 .has_intr_prsnt_sense = true,
2109 .has_cml_clk = false,
2110 .has_gen2 = true,
2111 .force_pca_enable = false,
2112 .program_uphy = false,
2113 };
2114
2115 static const struct of_device_id tegra_pcie_of_match[] = {
2116 { .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
2117 { .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
2118 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
2119 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
2120 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },
2121 { },
2122 };
2123
2124 static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos)
2125 {
2126 struct tegra_pcie *pcie = s->private;
2127
2128 if (list_empty(&pcie->ports))
2129 return NULL;
2130
2131 seq_printf(s, "Index Status\n");
2132
2133 return seq_list_start(&pcie->ports, *pos);
2134 }
2135
2136 static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos)
2137 {
2138 struct tegra_pcie *pcie = s->private;
2139
2140 return seq_list_next(v, &pcie->ports, pos);
2141 }
2142
2143 static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v)
2144 {
2145 }
2146
2147 static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v)
2148 {
2149 bool up = false, active = false;
2150 struct tegra_pcie_port *port;
2151 unsigned int value;
2152
2153 port = list_entry(v, struct tegra_pcie_port, list);
2154
2155 value = readl(port->base + RP_VEND_XP);
2156
2157 if (value & RP_VEND_XP_DL_UP)
2158 up = true;
2159
2160 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2161
2162 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2163 active = true;
2164
2165 seq_printf(s, "%2u ", port->index);
2166
2167 if (up)
2168 seq_printf(s, "up");
2169
2170 if (active) {
2171 if (up)
2172 seq_printf(s, ", ");
2173
2174 seq_printf(s, "active");
2175 }
2176
2177 seq_printf(s, "\n");
2178 return 0;
2179 }
2180
2181 static const struct seq_operations tegra_pcie_ports_seq_ops = {
2182 .start = tegra_pcie_ports_seq_start,
2183 .next = tegra_pcie_ports_seq_next,
2184 .stop = tegra_pcie_ports_seq_stop,
2185 .show = tegra_pcie_ports_seq_show,
2186 };
2187
2188 static int tegra_pcie_ports_open(struct inode *inode, struct file *file)
2189 {
2190 struct tegra_pcie *pcie = inode->i_private;
2191 struct seq_file *s;
2192 int err;
2193
2194 err = seq_open(file, &tegra_pcie_ports_seq_ops);
2195 if (err)
2196 return err;
2197
2198 s = file->private_data;
2199 s->private = pcie;
2200
2201 return 0;
2202 }
2203
2204 static const struct file_operations tegra_pcie_ports_ops = {
2205 .owner = THIS_MODULE,
2206 .open = tegra_pcie_ports_open,
2207 .read = seq_read,
2208 .llseek = seq_lseek,
2209 .release = seq_release,
2210 };
2211
2212 static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
2213 {
2214 struct dentry *file;
2215
2216 pcie->debugfs = debugfs_create_dir("pcie", NULL);
2217 if (!pcie->debugfs)
2218 return -ENOMEM;
2219
2220 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs,
2221 pcie, &tegra_pcie_ports_ops);
2222 if (!file)
2223 goto remove;
2224
2225 return 0;
2226
2227 remove:
2228 debugfs_remove_recursive(pcie->debugfs);
2229 pcie->debugfs = NULL;
2230 return -ENOMEM;
2231 }
2232
2233 static int tegra_pcie_probe(struct platform_device *pdev)
2234 {
2235 struct device *dev = &pdev->dev;
2236 struct pci_host_bridge *host;
2237 struct tegra_pcie *pcie;
2238 struct pci_bus *child;
2239 int err;
2240
2241 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
2242 if (!host)
2243 return -ENOMEM;
2244
2245 pcie = pci_host_bridge_priv(host);
2246 host->sysdata = pcie;
2247
2248 pcie->soc = of_device_get_match_data(dev);
2249 INIT_LIST_HEAD(&pcie->ports);
2250 pcie->dev = dev;
2251
2252 err = tegra_pcie_parse_dt(pcie);
2253 if (err < 0)
2254 return err;
2255
2256 err = tegra_pcie_get_resources(pcie);
2257 if (err < 0) {
2258 dev_err(dev, "failed to request resources: %d\n", err);
2259 return err;
2260 }
2261
2262 err = tegra_pcie_enable_controller(pcie);
2263 if (err)
2264 goto put_resources;
2265
2266 err = tegra_pcie_request_resources(pcie);
2267 if (err)
2268 goto put_resources;
2269
2270 /* setup the AFI address translations */
2271 tegra_pcie_setup_translations(pcie);
2272
2273 if (IS_ENABLED(CONFIG_PCI_MSI)) {
2274 err = tegra_pcie_enable_msi(pcie);
2275 if (err < 0) {
2276 dev_err(dev, "failed to enable MSI support: %d\n", err);
2277 goto put_resources;
2278 }
2279 }
2280
2281 tegra_pcie_enable_ports(pcie);
2282
2283 host->busnr = pcie->busn.start;
2284 host->dev.parent = &pdev->dev;
2285 host->ops = &tegra_pcie_ops;
2286 host->map_irq = tegra_pcie_map_irq;
2287 host->swizzle_irq = pci_common_swizzle;
2288
2289 err = pci_scan_root_bus_bridge(host);
2290 if (err < 0) {
2291 dev_err(dev, "failed to register host: %d\n", err);
2292 goto disable_msi;
2293 }
2294
2295 pci_bus_size_bridges(host->bus);
2296 pci_bus_assign_resources(host->bus);
2297
2298 list_for_each_entry(child, &host->bus->children, node)
2299 pcie_bus_configure_settings(child);
2300
2301 pci_bus_add_devices(host->bus);
2302
2303 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2304 err = tegra_pcie_debugfs_init(pcie);
2305 if (err < 0)
2306 dev_err(dev, "failed to setup debugfs: %d\n", err);
2307 }
2308
2309 return 0;
2310
2311 disable_msi:
2312 if (IS_ENABLED(CONFIG_PCI_MSI))
2313 tegra_pcie_disable_msi(pcie);
2314 put_resources:
2315 tegra_pcie_put_resources(pcie);
2316 return err;
2317 }
2318
2319 static struct platform_driver tegra_pcie_driver = {
2320 .driver = {
2321 .name = "tegra-pcie",
2322 .of_match_table = tegra_pcie_of_match,
2323 .suppress_bind_attrs = true,
2324 },
2325 .probe = tegra_pcie_probe,
2326 };
2327 builtin_platform_driver(tegra_pcie_driver);
CRIS linux kernel tree