| blob | 18aeee592fdcf24694909230c15974696f8b4a43 |
1 /*
2 * R8A7795 ES2.0+ processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
11 #include <linux/kernel.h>
12 #include <linux/sys_soc.h>
17 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
21 #define CPU_ALL_PORT(fn, sfx) \
22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
34 /*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
39 /* GPSR0 */
40 #define GPSR0_15 F_(D15, IP7_11_8)
41 #define GPSR0_14 F_(D14, IP7_7_4)
42 #define GPSR0_13 F_(D13, IP7_3_0)
43 #define GPSR0_12 F_(D12, IP6_31_28)
44 #define GPSR0_11 F_(D11, IP6_27_24)
45 #define GPSR0_10 F_(D10, IP6_23_20)
46 #define GPSR0_9 F_(D9, IP6_19_16)
47 #define GPSR0_8 F_(D8, IP6_15_12)
48 #define GPSR0_7 F_(D7, IP6_11_8)
49 #define GPSR0_6 F_(D6, IP6_7_4)
50 #define GPSR0_5 F_(D5, IP6_3_0)
51 #define GPSR0_4 F_(D4, IP5_31_28)
52 #define GPSR0_3 F_(D3, IP5_27_24)
53 #define GPSR0_2 F_(D2, IP5_23_20)
54 #define GPSR0_1 F_(D1, IP5_19_16)
55 #define GPSR0_0 F_(D0, IP5_15_12)
57 /* GPSR1 */
58 #define GPSR1_28 FM(CLKOUT)
59 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
60 #define GPSR1_26 F_(WE1_N, IP5_7_4)
61 #define GPSR1_25 F_(WE0_N, IP5_3_0)
62 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
63 #define GPSR1_23 F_(RD_N, IP4_27_24)
64 #define GPSR1_22 F_(BS_N, IP4_23_20)
65 #define GPSR1_21 F_(CS1_N, IP4_19_16)
66 #define GPSR1_20 F_(CS0_N, IP4_15_12)
67 #define GPSR1_19 F_(A19, IP4_11_8)
68 #define GPSR1_18 F_(A18, IP4_7_4)
69 #define GPSR1_17 F_(A17, IP4_3_0)
70 #define GPSR1_16 F_(A16, IP3_31_28)
71 #define GPSR1_15 F_(A15, IP3_27_24)
72 #define GPSR1_14 F_(A14, IP3_23_20)
73 #define GPSR1_13 F_(A13, IP3_19_16)
74 #define GPSR1_12 F_(A12, IP3_15_12)
75 #define GPSR1_11 F_(A11, IP3_11_8)
76 #define GPSR1_10 F_(A10, IP3_7_4)
77 #define GPSR1_9 F_(A9, IP3_3_0)
78 #define GPSR1_8 F_(A8, IP2_31_28)
79 #define GPSR1_7 F_(A7, IP2_27_24)
80 #define GPSR1_6 F_(A6, IP2_23_20)
81 #define GPSR1_5 F_(A5, IP2_19_16)
82 #define GPSR1_4 F_(A4, IP2_15_12)
83 #define GPSR1_3 F_(A3, IP2_11_8)
84 #define GPSR1_2 F_(A2, IP2_7_4)
85 #define GPSR1_1 F_(A1, IP2_3_0)
86 #define GPSR1_0 F_(A0, IP1_31_28)
88 /* GPSR2 */
89 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
90 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
91 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
92 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
93 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
94 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
95 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
96 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
97 #define GPSR2_6 F_(PWM0, IP1_19_16)
98 #define GPSR2_5 F_(IRQ5, IP1_15_12)
99 #define GPSR2_4 F_(IRQ4, IP1_11_8)
100 #define GPSR2_3 F_(IRQ3, IP1_7_4)
101 #define GPSR2_2 F_(IRQ2, IP1_3_0)
102 #define GPSR2_1 F_(IRQ1, IP0_31_28)
103 #define GPSR2_0 F_(IRQ0, IP0_27_24)
105 /* GPSR3 */
106 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
107 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
108 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
109 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
110 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
111 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
112 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
113 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
114 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
115 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
116 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
117 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
118 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
119 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
120 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
121 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
123 /* GPSR4 */
124 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
125 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
126 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
127 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
128 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
129 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
130 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
131 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
132 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
133 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
134 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
135 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
136 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
137 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
138 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
139 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
140 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
141 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
143 /* GPSR5 */
144 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
145 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
146 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
147 #define GPSR5_22 FM(MSIOF0_RXD)
148 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
149 #define GPSR5_20 FM(MSIOF0_TXD)
150 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
151 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
152 #define GPSR5_17 FM(MSIOF0_SCK)
153 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
154 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
155 #define GPSR5_14 F_(HTX0, IP13_19_16)
156 #define GPSR5_13 F_(HRX0, IP13_15_12)
157 #define GPSR5_12 F_(HSCK0, IP13_11_8)
158 #define GPSR5_11 F_(RX2_A, IP13_7_4)
159 #define GPSR5_10 F_(TX2_A, IP13_3_0)
160 #define GPSR5_9 F_(SCK2, IP12_31_28)
161 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
162 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
163 #define GPSR5_6 F_(TX1_A, IP12_19_16)
164 #define GPSR5_5 F_(RX1_A, IP12_15_12)
165 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
166 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
167 #define GPSR5_2 F_(TX0, IP12_3_0)
168 #define GPSR5_1 F_(RX0, IP11_31_28)
169 #define GPSR5_0 F_(SCK0, IP11_27_24)
171 /* GPSR6 */
172 #define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
173 #define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
174 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
175 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
176 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
177 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
178 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
179 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
180 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
181 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
182 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
183 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
184 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
185 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
186 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
187 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
188 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
189 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
190 #define GPSR6_13 FM(SSI_SDATA5)
191 #define GPSR6_12 FM(SSI_WS5)
192 #define GPSR6_11 FM(SSI_SCK5)
193 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
194 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
195 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
196 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
197 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
198 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
199 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
200 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
201 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
202 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
203 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
205 /* GPSR7 */
206 #define GPSR7_3 FM(HDMI1_CEC)
207 #define GPSR7_2 FM(HDMI0_CEC)
208 #define GPSR7_1 FM(AVS2)
209 #define GPSR7_0 FM(AVS1)
212 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
213 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
234 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
309 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
365 #define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
367 #define PINMUX_GPSR \
368 \
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
372 GPSR1_28 GPSR6_28 \
373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
402 #define PINMUX_IPSR \
403 \
404 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412 \
413 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
417 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421 \
422 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430 \
431 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439 \
440 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
450 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
451 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
455 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467 #define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
470 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472 #define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
473 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
483 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
484 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
494 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
497 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
501 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
502 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
503 #define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
504 #define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
505 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
507 #define PINMUX_MOD_SELS \
508 \
509 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
510 MOD_SEL2_30 \
511 MOD_SEL1_29_28_27 MOD_SEL2_29 \
512 MOD_SEL0_28_27 MOD_SEL2_28_27 \
513 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
514 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
515 MOD_SEL0_23 MOD_SEL1_23_22_21 \
516 MOD_SEL0_22 \
517 MOD_SEL0_21 MOD_SEL2_21 \
518 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
519 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
520 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
521 MOD_SEL2_17 \
522 MOD_SEL0_16 MOD_SEL1_16 \
523 MOD_SEL1_15_14 \
524 MOD_SEL0_14_13 \
525 MOD_SEL1_13 \
526 MOD_SEL0_12 MOD_SEL1_12 \
527 MOD_SEL0_11 MOD_SEL1_11 \
528 MOD_SEL0_10 MOD_SEL1_10 \
529 MOD_SEL0_9_8 MOD_SEL1_9 \
530 MOD_SEL0_7_6 \
531 MOD_SEL1_6 \
532 MOD_SEL0_5 MOD_SEL1_5 \
533 MOD_SEL0_4_3 MOD_SEL1_4 \
534 MOD_SEL1_3 \
535 MOD_SEL1_2 \
536 MOD_SEL1_1 \
537 MOD_SEL1_0 MOD_SEL2_0
539 /*
540 * These pins are not able to be muxed but have other properties
541 * that can be set, such as drive-strength or pull-up/pull-down enable.
542 */
543 #define PINMUX_STATIC \
544 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
545 FM(QSPI0_IO2) FM(QSPI0_IO3) \
546 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
547 FM(QSPI1_IO2) FM(QSPI1_IO3) \
548 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
549 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
550 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
551 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
552 FM(PRESETOUT) \
553 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
554 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559 PINMUX_DATA_BEGIN,
561 PINMUX_DATA_END,
563 #define F_(x, y)
564 #define FM(x) FN_##x,
565 PINMUX_FUNCTION_BEGIN,
567 PINMUX_GPSR
568 PINMUX_IPSR
569 PINMUX_MOD_SELS
570 PINMUX_FUNCTION_END,
571 #undef F_
572 #undef FM
574 #define F_(x, y)
575 #define FM(x) x##_MARK,
576 PINMUX_MARK_BEGIN,
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
580 PINMUX_STATIC
581 PINMUX_MARK_END,
582 #undef F_
583 #undef FM
584 };
604 /* IPSR0 */
645 /* IPSR1 */
696 /* IPSR2 */
757 /* IPSR3 */
811 /* IPSR4 */
857 /* IPSR5 */
907 /* IPSR6 */
959 /* IPSR7 */
1001 /* IPSR8 */
1050 /* IPSR9 */
1076 /* IPSR10 */
1104 /* IPSR11 */
1142 /* IPSR12 */
1203 /* IPSR13 */
1263 /* IPSR14 */
1304 /* IPSR15 */
1351 /* IPSR16 */
1406 /* IPSR17 */
1473 /* IPSR18 */
1494 /*
1495 * Static pins can not be muxed between different functions but
1496 * still needs a mark entry in the pinmux list. Add each static
1497 * pin to the list without an associated function. The sh-pfc
1498 * core will do the right thing and skip trying to mux then pin
1499 * while still applying configuration to it
1500 */
1501 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1502 PINMUX_STATIC
1503 #undef FM
1504 };
1506 /*
1507 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1508 * Physical layout rows: A - AW, cols: 1 - 39.
1509 */
1512 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1513 #define PIN_NONE U16_MAX
1518 /*
1519 * Pins not associated with a GPIO port.
1520 *
1521 * The pin positions are different between different r8a7795
1522 * packages, all that is needed for the pfc driver is a unique
1523 * number for each pin. To this end use the pin layout from
1524 * R-Car H3SiP to calculate a unique number for each pin.
1525 */
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 };
1572 /* - AUDIO CLOCK ------------------------------------------------------------ */
1574 /* CLK A */
1576 };
1578 AUDIO_CLKA_A_MARK,
1579 };
1581 /* CLK A */
1583 };
1585 AUDIO_CLKA_B_MARK,
1586 };
1588 /* CLK A */
1590 };
1592 AUDIO_CLKA_C_MARK,
1593 };
1595 /* CLK B */
1597 };
1599 AUDIO_CLKB_A_MARK,
1600 };
1602 /* CLK B */
1604 };
1606 AUDIO_CLKB_B_MARK,
1607 };
1609 /* CLK C */
1611 };
1613 AUDIO_CLKC_A_MARK,
1614 };
1616 /* CLK C */
1618 };
1620 AUDIO_CLKC_B_MARK,
1621 };
1623 /* CLKOUT */
1625 };
1627 AUDIO_CLKOUT_A_MARK,
1628 };
1630 /* CLKOUT */
1632 };
1634 AUDIO_CLKOUT_B_MARK,
1635 };
1637 /* CLKOUT */
1639 };
1641 AUDIO_CLKOUT_C_MARK,
1642 };
1644 /* CLKOUT */
1646 };
1648 AUDIO_CLKOUT_D_MARK,
1649 };
1651 /* CLKOUT1 */
1653 };
1655 AUDIO_CLKOUT1_A_MARK,
1656 };
1658 /* CLKOUT1 */
1660 };
1662 AUDIO_CLKOUT1_B_MARK,
1663 };
1665 /* CLKOUT2 */
1667 };
1669 AUDIO_CLKOUT2_A_MARK,
1670 };
1672 /* CLKOUT2 */
1674 };
1676 AUDIO_CLKOUT2_B_MARK,
1677 };
1679 /* CLKOUT3 */
1681 };
1683 AUDIO_CLKOUT3_A_MARK,
1684 };
1686 /* CLKOUT3 */
1688 };
1690 AUDIO_CLKOUT3_B_MARK,
1691 };
1693 /* - EtherAVB --------------------------------------------------------------- */
1695 /* AVB_LINK */
1697 };
1699 AVB_LINK_MARK,
1700 };
1702 /* AVB_MAGIC_ */
1704 };
1706 AVB_MAGIC_MARK,
1707 };
1709 /* AVB_PHY_INT */
1711 };
1713 AVB_PHY_INT_MARK,
1714 };
1716 /* AVB_MDC, AVB_MDIO */
1718 };
1721 };
1723 /*
1724 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1725 * AVB_TD1, AVB_TD2, AVB_TD3,
1726 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1727 * AVB_RD1, AVB_RD2, AVB_RD3,
1728 * AVB_TXCREFCLK
1729 */
1736 };
1742 AVB_TXCREFCLK_MARK,
1743 };
1745 /* AVB_AVTP_PPS */
1747 };
1749 AVB_AVTP_PPS_MARK,
1750 };
1752 /* AVB_AVTP_MATCH_A */
1754 };
1756 AVB_AVTP_MATCH_A_MARK,
1757 };
1759 /* AVB_AVTP_CAPTURE_A */
1761 };
1763 AVB_AVTP_CAPTURE_A_MARK,
1764 };
1766 /* AVB_AVTP_MATCH_B */
1768 };
1770 AVB_AVTP_MATCH_B_MARK,
1771 };
1773 /* AVB_AVTP_CAPTURE_B */
1775 };
1777 AVB_AVTP_CAPTURE_B_MARK,
1778 };
1780 /* - CAN ------------------------------------------------------------------ */
1782 /* TX, RX */
1784 };
1787 };
1789 /* TX, RX */
1791 };
1794 };
1796 /* TX, RX */
1798 };
1801 };
1803 /* - CAN Clock -------------------------------------------------------------- */
1805 /* CLK */
1807 };
1809 CAN_CLK_MARK,
1810 };
1812 /* - CAN FD --------------------------------------------------------------- */
1814 /* TX, RX */
1816 };
1819 };
1821 /* TX, RX */
1823 };
1826 };
1828 /* TX, RX */
1830 };
1833 };
1835 /* - DRIF0 --------------------------------------------------------------- */
1837 /* CLK, SYNC */
1839 };
1842 };
1844 /* D0 */
1846 };
1848 RIF0_D0_A_MARK,
1849 };
1851 /* D1 */
1853 };
1855 RIF0_D1_A_MARK,
1856 };
1858 /* CLK, SYNC */
1860 };
1863 };
1865 /* D0 */
1867 };
1869 RIF0_D0_B_MARK,
1870 };
1872 /* D1 */
1874 };
1876 RIF0_D1_B_MARK,
1877 };
1879 /* CLK, SYNC */
1881 };
1884 };
1886 /* D0 */
1888 };
1890 RIF0_D0_C_MARK,
1891 };
1893 /* D1 */
1895 };
1897 RIF0_D1_C_MARK,
1898 };
1899 /* - DRIF1 --------------------------------------------------------------- */
1901 /* CLK, SYNC */
1903 };
1906 };
1908 /* D0 */
1910 };
1912 RIF1_D0_A_MARK,
1913 };
1915 /* D1 */
1917 };
1919 RIF1_D1_A_MARK,
1920 };
1922 /* CLK, SYNC */
1924 };
1927 };
1929 /* D0 */
1931 };
1933 RIF1_D0_B_MARK,
1934 };
1936 /* D1 */
1938 };
1940 RIF1_D1_B_MARK,
1941 };
1943 /* CLK, SYNC */
1945 };
1948 };
1950 /* D0 */
1952 };
1954 RIF1_D0_C_MARK,
1955 };
1957 /* D1 */
1959 };
1961 RIF1_D1_C_MARK,
1962 };
1963 /* - DRIF2 --------------------------------------------------------------- */
1965 /* CLK, SYNC */
1967 };
1970 };
1972 /* D0 */
1974 };
1976 RIF2_D0_A_MARK,
1977 };
1979 /* D1 */
1981 };
1983 RIF2_D1_A_MARK,
1984 };
1986 /* CLK, SYNC */
1988 };
1991 };
1993 /* D0 */
1995 };
1997 RIF2_D0_B_MARK,
1998 };
2000 /* D1 */
2002 };
2004 RIF2_D1_B_MARK,
2005 };
2006 /* - DRIF3 --------------------------------------------------------------- */
2008 /* CLK, SYNC */
2010 };
2013 };
2015 /* D0 */
2017 };
2019 RIF3_D0_A_MARK,
2020 };
2022 /* D1 */
2024 };
2026 RIF3_D1_A_MARK,
2027 };
2029 /* CLK, SYNC */
2031 };
2034 };
2036 /* D0 */
2038 };
2040 RIF3_D0_B_MARK,
2041 };
2043 /* D1 */
2045 };
2047 RIF3_D1_B_MARK,
2048 };
2050 /* - DU --------------------------------------------------------------------- */
2052 /* R[7:2], G[7:2], B[7:2] */
2059 };
2067 };
2069 /* R[7:0], G[7:0], B[7:0] */
2079 };
2087 };
2089 /* CLKOUT */
2091 };
2093 DU_DOTCLKOUT0_MARK
2094 };
2096 /* CLKOUT */
2098 };
2100 DU_DOTCLKOUT1_MARK
2101 };
2103 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2105 };
2107 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2108 };
2110 /* EXDISP/EXODDF/EXCDE */
2112 };
2114 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2115 };
2117 /* CDE */
2119 };
2121 DU_CDE_MARK,
2122 };
2124 /* DISP */
2126 };
2128 DU_DISP_MARK,
2129 };
2131 /* - HSCIF0 ----------------------------------------------------------------- */
2133 /* RX, TX */
2135 };
2138 };
2140 /* SCK */
2142 };
2144 HSCK0_MARK,
2145 };
2147 /* RTS, CTS */
2149 };
2152 };
2153 /* - HSCIF1 ----------------------------------------------------------------- */
2155 /* RX, TX */
2157 };
2160 };
2162 /* SCK */
2164 };
2166 HSCK1_A_MARK,
2167 };
2169 /* RTS, CTS */
2171 };
2174 };
2177 /* RX, TX */
2179 };
2182 };
2184 /* SCK */
2186 };
2188 HSCK1_B_MARK,
2189 };
2191 /* RTS, CTS */
2193 };
2196 };
2197 /* - HSCIF2 ----------------------------------------------------------------- */
2199 /* RX, TX */
2201 };
2204 };
2206 /* SCK */
2208 };
2210 HSCK2_A_MARK,
2211 };
2213 /* RTS, CTS */
2215 };
2218 };
2221 /* RX, TX */
2223 };
2226 };
2228 /* SCK */
2230 };
2232 HSCK2_B_MARK,
2233 };
2235 /* RTS, CTS */
2237 };
2240 };
2243 /* RX, TX */
2245 };
2248 };
2250 /* SCK */
2252 };
2254 HSCK2_C_MARK,
2255 };
2257 /* RTS, CTS */
2259 };
2262 };
2263 /* - HSCIF3 ----------------------------------------------------------------- */
2265 /* RX, TX */
2267 };
2270 };
2272 /* SCK */
2274 };
2276 HSCK3_MARK,
2277 };
2279 /* RTS, CTS */
2281 };
2284 };
2287 /* RX, TX */
2289 };
2292 };
2294 /* RX, TX */
2296 };
2299 };
2301 /* RX, TX */
2303 };
2306 };
2307 /* - HSCIF4 ----------------------------------------------------------------- */
2309 /* RX, TX */
2311 };
2314 };
2316 /* SCK */
2318 };
2320 HSCK4_MARK,
2321 };
2323 /* RTS, CTS */
2325 };
2328 };
2331 /* RX, TX */
2333 };
2336 };
2338 /* - I2C -------------------------------------------------------------------- */
2340 /* SDA, SCL */
2342 };
2345 };
2347 /* SDA, SCL */
2349 };
2352 };
2354 /* SDA, SCL */
2356 };
2359 };
2361 /* SDA, SCL */
2363 };
2366 };
2368 /* SDA, SCL */
2370 };
2373 };
2375 /* SDA, SCL */
2377 };
2380 };
2382 /* SDA, SCL */
2384 };
2387 };
2389 /* - INTC-EX ---------------------------------------------------------------- */
2391 /* IRQ0 */
2393 };
2395 IRQ0_MARK,
2396 };
2398 /* IRQ1 */
2400 };
2402 IRQ1_MARK,
2403 };
2405 /* IRQ2 */
2407 };
2409 IRQ2_MARK,
2410 };
2412 /* IRQ3 */
2414 };
2416 IRQ3_MARK,
2417 };
2419 /* IRQ4 */
2421 };
2423 IRQ4_MARK,
2424 };
2426 /* IRQ5 */
2428 };
2430 IRQ5_MARK,
2431 };
2433 /* - MSIOF0 ----------------------------------------------------------------- */
2435 /* SCK */
2437 };
2439 MSIOF0_SCK_MARK,
2440 };
2442 /* SYNC */
2444 };
2446 MSIOF0_SYNC_MARK,
2447 };
2449 /* SS1 */
2451 };
2453 MSIOF0_SS1_MARK,
2454 };
2456 /* SS2 */
2458 };
2460 MSIOF0_SS2_MARK,
2461 };
2463 /* TXD */
2465 };
2467 MSIOF0_TXD_MARK,
2468 };
2470 /* RXD */
2472 };
2474 MSIOF0_RXD_MARK,
2475 };
2476 /* - MSIOF1 ----------------------------------------------------------------- */
2478 /* SCK */
2480 };
2482 MSIOF1_SCK_A_MARK,
2483 };
2485 /* SYNC */
2487 };
2489 MSIOF1_SYNC_A_MARK,
2490 };
2492 /* SS1 */
2494 };
2496 MSIOF1_SS1_A_MARK,
2497 };
2499 /* SS2 */
2501 };
2503 MSIOF1_SS2_A_MARK,
2504 };
2506 /* TXD */
2508 };
2510 MSIOF1_TXD_A_MARK,
2511 };
2513 /* RXD */
2515 };
2517 MSIOF1_RXD_A_MARK,
2518 };
2520 /* SCK */
2522 };
2524 MSIOF1_SCK_B_MARK,
2525 };
2527 /* SYNC */
2529 };
2531 MSIOF1_SYNC_B_MARK,
2532 };
2534 /* SS1 */
2536 };
2538 MSIOF1_SS1_B_MARK,
2539 };
2541 /* SS2 */
2543 };
2545 MSIOF1_SS2_B_MARK,
2546 };
2548 /* TXD */
2550 };
2552 MSIOF1_TXD_B_MARK,
2553 };
2555 /* RXD */
2557 };
2559 MSIOF1_RXD_B_MARK,
2560 };
2562 /* SCK */
2564 };
2566 MSIOF1_SCK_C_MARK,
2567 };
2569 /* SYNC */
2571 };
2573 MSIOF1_SYNC_C_MARK,
2574 };
2576 /* SS1 */
2578 };
2580 MSIOF1_SS1_C_MARK,
2581 };
2583 /* SS2 */
2585 };
2587 MSIOF1_SS2_C_MARK,
2588 };
2590 /* TXD */
2592 };
2594 MSIOF1_TXD_C_MARK,
2595 };
2597 /* RXD */
2599 };
2601 MSIOF1_RXD_C_MARK,
2602 };
2604 /* SCK */
2606 };
2608 MSIOF1_SCK_D_MARK,
2609 };
2611 /* SYNC */
2613 };
2615 MSIOF1_SYNC_D_MARK,
2616 };
2618 /* SS1 */
2620 };
2622 MSIOF1_SS1_D_MARK,
2623 };
2625 /* SS2 */
2627 };
2629 MSIOF1_SS2_D_MARK,
2630 };
2632 /* TXD */
2634 };
2636 MSIOF1_TXD_D_MARK,
2637 };
2639 /* RXD */
2641 };
2643 MSIOF1_RXD_D_MARK,
2644 };
2646 /* SCK */
2648 };
2650 MSIOF1_SCK_E_MARK,
2651 };
2653 /* SYNC */
2655 };
2657 MSIOF1_SYNC_E_MARK,
2658 };
2660 /* SS1 */
2662 };
2664 MSIOF1_SS1_E_MARK,
2665 };
2667 /* SS2 */
2669 };
2671 MSIOF1_SS2_E_MARK,
2672 };
2674 /* TXD */
2676 };
2678 MSIOF1_TXD_E_MARK,
2679 };
2681 /* RXD */
2683 };
2685 MSIOF1_RXD_E_MARK,
2686 };
2688 /* SCK */
2690 };
2692 MSIOF1_SCK_F_MARK,
2693 };
2695 /* SYNC */
2697 };
2699 MSIOF1_SYNC_F_MARK,
2700 };
2702 /* SS1 */
2704 };
2706 MSIOF1_SS1_F_MARK,
2707 };
2709 /* SS2 */
2711 };
2713 MSIOF1_SS2_F_MARK,
2714 };
2716 /* TXD */
2718 };
2720 MSIOF1_TXD_F_MARK,
2721 };
2723 /* RXD */
2725 };
2727 MSIOF1_RXD_F_MARK,
2728 };
2730 /* SCK */
2732 };
2734 MSIOF1_SCK_G_MARK,
2735 };
2737 /* SYNC */
2739 };
2741 MSIOF1_SYNC_G_MARK,
2742 };
2744 /* SS1 */
2746 };
2748 MSIOF1_SS1_G_MARK,
2749 };
2751 /* SS2 */
2753 };
2755 MSIOF1_SS2_G_MARK,
2756 };
2758 /* TXD */
2760 };
2762 MSIOF1_TXD_G_MARK,
2763 };
2765 /* RXD */
2767 };
2769 MSIOF1_RXD_G_MARK,
2770 };
2771 /* - MSIOF2 ----------------------------------------------------------------- */
2773 /* SCK */
2775 };
2777 MSIOF2_SCK_A_MARK,
2778 };
2780 /* SYNC */
2782 };
2784 MSIOF2_SYNC_A_MARK,
2785 };
2787 /* SS1 */
2789 };
2791 MSIOF2_SS1_A_MARK,
2792 };
2794 /* SS2 */
2796 };
2798 MSIOF2_SS2_A_MARK,
2799 };
2801 /* TXD */
2803 };
2805 MSIOF2_TXD_A_MARK,
2806 };
2808 /* RXD */
2810 };
2812 MSIOF2_RXD_A_MARK,
2813 };
2815 /* SCK */
2817 };
2819 MSIOF2_SCK_B_MARK,
2820 };
2822 /* SYNC */
2824 };
2826 MSIOF2_SYNC_B_MARK,
2827 };
2829 /* SS1 */
2831 };
2833 MSIOF2_SS1_B_MARK,
2834 };
2836 /* SS2 */
2838 };
2840 MSIOF2_SS2_B_MARK,
2841 };
2843 /* TXD */
2845 };
2847 MSIOF2_TXD_B_MARK,
2848 };
2850 /* RXD */
2852 };
2854 MSIOF2_RXD_B_MARK,
2855 };
2857 /* SCK */
2859 };
2861 MSIOF2_SCK_C_MARK,
2862 };
2864 /* SYNC */
2866 };
2868 MSIOF2_SYNC_C_MARK,
2869 };
2871 /* SS1 */
2873 };
2875 MSIOF2_SS1_C_MARK,
2876 };
2878 /* SS2 */
2880 };
2882 MSIOF2_SS2_C_MARK,
2883 };
2885 /* TXD */
2887 };
2889 MSIOF2_TXD_C_MARK,
2890 };
2892 /* RXD */
2894 };
2896 MSIOF2_RXD_C_MARK,
2897 };
2899 /* SCK */
2901 };
2903 MSIOF2_SCK_D_MARK,
2904 };
2906 /* SYNC */
2908 };
2910 MSIOF2_SYNC_D_MARK,
2911 };
2913 /* SS1 */
2915 };
2917 MSIOF2_SS1_D_MARK,
2918 };
2920 /* SS2 */
2922 };
2924 MSIOF2_SS2_D_MARK,
2925 };
2927 /* TXD */
2929 };
2931 MSIOF2_TXD_D_MARK,
2932 };
2934 /* RXD */
2936 };
2938 MSIOF2_RXD_D_MARK,
2939 };
2940 /* - MSIOF3 ----------------------------------------------------------------- */
2942 /* SCK */
2944 };
2946 MSIOF3_SCK_A_MARK,
2947 };
2949 /* SYNC */
2951 };
2953 MSIOF3_SYNC_A_MARK,
2954 };
2956 /* SS1 */
2958 };
2960 MSIOF3_SS1_A_MARK,
2961 };
2963 /* SS2 */
2965 };
2967 MSIOF3_SS2_A_MARK,
2968 };
2970 /* TXD */
2972 };
2974 MSIOF3_TXD_A_MARK,
2975 };
2977 /* RXD */
2979 };
2981 MSIOF3_RXD_A_MARK,
2982 };
2984 /* SCK */
2986 };
2988 MSIOF3_SCK_B_MARK,
2989 };
2991 /* SYNC */
2993 };
2995 MSIOF3_SYNC_B_MARK,
2996 };
2998 /* SS1 */
3000 };
3002 MSIOF3_SS1_B_MARK,
3003 };
3005 /* SS2 */
3007 };
3009 MSIOF3_SS2_B_MARK,
3010 };
3012 /* TXD */
3014 };
3016 MSIOF3_TXD_B_MARK,
3017 };
3019 /* RXD */
3021 };
3023 MSIOF3_RXD_B_MARK,
3024 };
3026 /* SCK */
3028 };
3030 MSIOF3_SCK_C_MARK,
3031 };
3033 /* SYNC */
3035 };
3037 MSIOF3_SYNC_C_MARK,
3038 };
3040 /* TXD */
3042 };
3044 MSIOF3_TXD_C_MARK,
3045 };
3047 /* RXD */
3049 };
3051 MSIOF3_RXD_C_MARK,
3052 };
3054 /* SCK */
3056 };
3058 MSIOF3_SCK_D_MARK,
3059 };
3061 /* SYNC */
3063 };
3065 MSIOF3_SYNC_D_MARK,
3066 };
3068 /* SS1 */
3070 };
3072 MSIOF3_SS1_D_MARK,
3073 };
3075 /* TXD */
3077 };
3079 MSIOF3_TXD_D_MARK,
3080 };
3082 /* RXD */
3084 };
3086 MSIOF3_RXD_D_MARK,
3087 };
3089 /* SCK */
3091 };
3093 MSIOF3_SCK_E_MARK,
3094 };
3096 /* SYNC */
3098 };
3100 MSIOF3_SYNC_E_MARK,
3101 };
3103 /* SS1 */
3105 };
3107 MSIOF3_SS1_E_MARK,
3108 };
3110 /* SS1 */
3112 };
3114 MSIOF3_SS2_E_MARK,
3115 };
3117 /* TXD */
3119 };
3121 MSIOF3_TXD_E_MARK,
3122 };
3124 /* RXD */
3126 };
3128 MSIOF3_RXD_E_MARK,
3129 };
3131 /* - PWM0 --------------------------------------------------------------------*/
3133 /* PWM */
3135 };
3137 PWM0_MARK,
3138 };
3139 /* - PWM1 --------------------------------------------------------------------*/
3141 /* PWM */
3143 };
3145 PWM1_A_MARK,
3146 };
3148 /* PWM */
3150 };
3152 PWM1_B_MARK,
3153 };
3154 /* - PWM2 --------------------------------------------------------------------*/
3156 /* PWM */
3158 };
3160 PWM2_A_MARK,
3161 };
3163 /* PWM */
3165 };
3167 PWM2_B_MARK,
3168 };
3169 /* - PWM3 --------------------------------------------------------------------*/
3171 /* PWM */
3173 };
3175 PWM3_A_MARK,
3176 };
3178 /* PWM */
3180 };
3182 PWM3_B_MARK,
3183 };
3184 /* - PWM4 --------------------------------------------------------------------*/
3186 /* PWM */
3188 };
3190 PWM4_A_MARK,
3191 };
3193 /* PWM */
3195 };
3197 PWM4_B_MARK,
3198 };
3199 /* - PWM5 --------------------------------------------------------------------*/
3201 /* PWM */
3203 };
3205 PWM5_A_MARK,
3206 };
3208 /* PWM */
3210 };
3212 PWM5_B_MARK,
3213 };
3214 /* - PWM6 --------------------------------------------------------------------*/
3216 /* PWM */
3218 };
3220 PWM6_A_MARK,
3221 };
3223 /* PWM */
3225 };
3227 PWM6_B_MARK,
3228 };
3230 /* - SATA --------------------------------------------------------------------*/
3232 /* DEVSLP */
3234 };
3236 SATA_DEVSLP_A_MARK,
3237 };
3239 /* DEVSLP */
3241 };
3243 SATA_DEVSLP_B_MARK,
3244 };
3246 /* - SCIF0 ------------------------------------------------------------------ */
3248 /* RX, TX */
3250 };
3253 };
3255 /* SCK */
3257 };
3259 SCK0_MARK,
3260 };
3262 /* RTS, CTS */
3264 };
3267 };
3268 /* - SCIF1 ------------------------------------------------------------------ */
3270 /* RX, TX */
3272 };
3275 };
3277 /* SCK */
3279 };
3281 SCK1_MARK,
3282 };
3284 /* RTS, CTS */
3286 };
3289 };
3292 /* RX, TX */
3294 };
3297 };
3298 /* - SCIF2 ------------------------------------------------------------------ */
3300 /* RX, TX */
3302 };
3305 };
3307 /* SCK */
3309 };
3311 SCK2_MARK,
3312 };
3314 /* RX, TX */
3316 };
3319 };
3320 /* - SCIF3 ------------------------------------------------------------------ */
3322 /* RX, TX */
3324 };
3327 };
3329 /* SCK */
3331 };
3333 SCK3_MARK,
3334 };
3336 /* RTS, CTS */
3338 };
3341 };
3343 /* RX, TX */
3345 };
3348 };
3349 /* - SCIF4 ------------------------------------------------------------------ */
3351 /* RX, TX */
3353 };
3356 };
3358 /* SCK */
3360 };
3362 SCK4_A_MARK,
3363 };
3365 /* RTS, CTS */
3367 };
3370 };
3372 /* RX, TX */
3374 };
3377 };
3379 /* SCK */
3381 };
3383 SCK4_B_MARK,
3384 };
3386 /* RTS, CTS */
3388 };
3391 };
3393 /* RX, TX */
3395 };
3398 };
3400 /* SCK */
3402 };
3404 SCK4_C_MARK,
3405 };
3407 /* RTS, CTS */
3409 };
3412 };
3413 /* - SCIF5 ------------------------------------------------------------------ */
3415 /* RX, TX */
3417 };
3420 };
3422 /* SCK */
3424 };
3426 SCK5_A_MARK,
3427 };
3429 /* RX, TX */
3431 };
3434 };
3436 /* SCK */
3438 };
3440 SCK5_B_MARK,
3441 };
3443 /* - SCIF Clock ------------------------------------------------------------- */
3445 /* SCIF_CLK */
3447 };
3449 SCIF_CLK_A_MARK,
3450 };
3452 /* SCIF_CLK */
3454 };
3456 SCIF_CLK_B_MARK,
3457 };
3459 /* - SDHI0 ------------------------------------------------------------------ */
3461 /* D0 */
3463 };
3465 SD0_DAT0_MARK,
3466 };
3468 /* D[0:3] */
3471 };
3475 };
3477 /* CLK, CMD */
3479 };
3482 };
3484 /* CD */
3486 };
3488 SD0_CD_MARK,
3489 };
3491 /* WP */
3493 };
3495 SD0_WP_MARK,
3496 };
3497 /* - SDHI1 ------------------------------------------------------------------ */
3499 /* D0 */
3501 };
3503 SD1_DAT0_MARK,
3504 };
3506 /* D[0:3] */
3509 };
3513 };
3515 /* CLK, CMD */
3517 };
3520 };
3522 /* CD */
3524 };
3526 SD1_CD_MARK,
3527 };
3529 /* WP */
3531 };
3533 SD1_WP_MARK,
3534 };
3535 /* - SDHI2 ------------------------------------------------------------------ */
3537 /* D0 */
3539 };
3541 SD2_DAT0_MARK,
3542 };
3544 /* D[0:3] */
3547 };
3551 };
3553 /* D[0:7] */
3558 };
3564 };
3566 /* CLK, CMD */
3568 };
3571 };
3573 /* CD */
3575 };
3577 SD2_CD_A_MARK,
3578 };
3580 /* CD */
3582 };
3584 SD2_CD_B_MARK,
3585 };
3587 /* WP */
3589 };
3591 SD2_WP_A_MARK,
3592 };
3594 /* WP */
3596 };
3598 SD2_WP_B_MARK,
3599 };
3601 /* DS */
3603 };
3605 SD2_DS_MARK,
3606 };
3607 /* - SDHI3 ------------------------------------------------------------------ */
3609 /* D0 */
3611 };
3613 SD3_DAT0_MARK,
3614 };
3616 /* D[0:3] */
3619 };
3623 };
3625 /* D[0:7] */
3630 };
3636 };
3638 /* CLK, CMD */
3640 };
3643 };
3645 /* CD */
3647 };
3649 SD3_CD_MARK,
3650 };
3652 /* WP */
3654 };
3656 SD3_WP_MARK,
3657 };
3659 /* DS */
3661 };
3663 SD3_DS_MARK,
3664 };
3666 /* - SSI -------------------------------------------------------------------- */
3668 /* SDATA */
3670 };
3672 SSI_SDATA0_MARK,
3673 };
3675 /* SCK, WS */
3677 };
3680 };
3682 /* SDATA */
3684 };
3686 SSI_SDATA1_A_MARK,
3687 };
3689 /* SDATA */
3691 };
3693 SSI_SDATA1_B_MARK,
3694 };
3696 /* SCK, WS */
3698 };
3701 };
3703 /* SCK, WS */
3705 };
3708 };
3710 /* SDATA */
3712 };
3714 SSI_SDATA2_A_MARK,
3715 };
3717 /* SDATA */
3719 };
3721 SSI_SDATA2_B_MARK,
3722 };
3724 /* SCK, WS */
3726 };
3729 };
3731 /* SCK, WS */
3733 };
3736 };
3738 /* SDATA */
3740 };
3742 SSI_SDATA3_MARK,
3743 };
3745 /* SCK, WS */
3747 };
3750 };
3752 /* SDATA */
3754 };
3756 SSI_SDATA4_MARK,
3757 };
3759 /* SCK, WS */
3761 };
3764 };
3766 /* SDATA */
3768 };
3770 SSI_SDATA5_MARK,
3771 };
3773 /* SCK, WS */
3775 };
3778 };
3780 /* SDATA */
3782 };
3784 SSI_SDATA6_MARK,
3785 };
3787 /* SCK, WS */
3789 };
3792 };
3794 /* SDATA */
3796 };
3798 SSI_SDATA7_MARK,
3799 };
3801 /* SCK, WS */
3803 };
3806 };
3808 /* SDATA */
3810 };
3812 SSI_SDATA8_MARK,
3813 };
3815 /* SDATA */
3817 };
3819 SSI_SDATA9_A_MARK,
3820 };
3822 /* SDATA */
3824 };
3826 SSI_SDATA9_B_MARK,
3827 };
3829 /* SCK, WS */
3831 };
3834 };
3836 /* SCK, WS */
3838 };
3841 };
3843 /* - USB0 ------------------------------------------------------------------- */
3845 /* PWEN, OVC */
3847 };
3850 };
3851 /* - USB1 ------------------------------------------------------------------- */
3853 /* PWEN, OVC */
3855 };
3858 };
3859 /* - USB2 ------------------------------------------------------------------- */
3861 /* PWEN, OVC */
3863 };
3866 };
3867 /* - USB2_CH3 --------------------------------------------------------------- */
3869 /* PWEN, OVC */
3871 };
3874 };
3876 /* - USB30 ------------------------------------------------------------------ */
3878 /* PWEN, OVC */
3880 };
3883 };
4198 };
4218 };
4231 };
4236 };
4240 };
4244 };
4249 };
4253 };
4265 };
4277 };
4286 };
4295 };
4306 };
4312 };
4321 };
4333 };
4342 };
4349 };
4354 };
4359 };
4365 };
4374 };
4383 };
4428 };
4455 };
4485 };
4489 };
4494 };
4499 };
4504 };
4509 };
4514 };
4519 };
4524 };
4530 };
4537 };
4543 };
4550 };
4562 };
4569 };
4574 };
4582 };
4590 };
4602 };
4612 };
4640 };
4644 };
4648 };
4652 };
4656 };
4660 };
4713 };
4716 #define F_(x, y) FN_##y
4717 #define FM(x) FN_##x
4751 },
4785 },
4819 },
4853 },
4887 },
4921 },
4955 },
4989 },
4990 #undef F_
4991 #undef FM
4993 #define F_(x, y) x,
4994 #define FM(x) FN_##x,
4996 IP0_31_28
4997 IP0_27_24
4998 IP0_23_20
4999 IP0_19_16
5000 IP0_15_12
5001 IP0_11_8
5002 IP0_7_4
5003 IP0_3_0 }
5004 },
5006 IP1_31_28
5007 IP1_27_24
5008 IP1_23_20
5009 IP1_19_16
5010 IP1_15_12
5011 IP1_11_8
5012 IP1_7_4
5013 IP1_3_0 }
5014 },
5016 IP2_31_28
5017 IP2_27_24
5018 IP2_23_20
5019 IP2_19_16
5020 IP2_15_12
5021 IP2_11_8
5022 IP2_7_4
5023 IP2_3_0 }
5024 },
5026 IP3_31_28
5027 IP3_27_24
5028 IP3_23_20
5029 IP3_19_16
5030 IP3_15_12
5031 IP3_11_8
5032 IP3_7_4
5033 IP3_3_0 }
5034 },
5036 IP4_31_28
5037 IP4_27_24
5038 IP4_23_20
5039 IP4_19_16
5040 IP4_15_12
5041 IP4_11_8
5042 IP4_7_4
5043 IP4_3_0 }
5044 },
5046 IP5_31_28
5047 IP5_27_24
5048 IP5_23_20
5049 IP5_19_16
5050 IP5_15_12
5051 IP5_11_8
5052 IP5_7_4
5053 IP5_3_0 }
5054 },
5056 IP6_31_28
5057 IP6_27_24
5058 IP6_23_20
5059 IP6_19_16
5060 IP6_15_12
5061 IP6_11_8
5062 IP6_7_4
5063 IP6_3_0 }
5064 },
5066 IP7_31_28
5067 IP7_27_24
5068 IP7_23_20
5069 IP7_19_16
5071 IP7_11_8
5072 IP7_7_4
5073 IP7_3_0 }
5074 },
5076 IP8_31_28
5077 IP8_27_24
5078 IP8_23_20
5079 IP8_19_16
5080 IP8_15_12
5081 IP8_11_8
5082 IP8_7_4
5083 IP8_3_0 }
5084 },
5086 IP9_31_28
5087 IP9_27_24
5088 IP9_23_20
5089 IP9_19_16
5090 IP9_15_12
5091 IP9_11_8
5092 IP9_7_4
5093 IP9_3_0 }
5094 },
5096 IP10_31_28
5097 IP10_27_24
5098 IP10_23_20
5099 IP10_19_16
5100 IP10_15_12
5101 IP10_11_8
5102 IP10_7_4
5103 IP10_3_0 }
5104 },
5106 IP11_31_28
5107 IP11_27_24
5108 IP11_23_20
5109 IP11_19_16
5110 IP11_15_12
5111 IP11_11_8
5112 IP11_7_4
5113 IP11_3_0 }
5114 },
5116 IP12_31_28
5117 IP12_27_24
5118 IP12_23_20
5119 IP12_19_16
5120 IP12_15_12
5121 IP12_11_8
5122 IP12_7_4
5123 IP12_3_0 }
5124 },
5126 IP13_31_28
5127 IP13_27_24
5128 IP13_23_20
5129 IP13_19_16
5130 IP13_15_12
5131 IP13_11_8
5132 IP13_7_4
5133 IP13_3_0 }
5134 },
5136 IP14_31_28
5137 IP14_27_24
5138 IP14_23_20
5139 IP14_19_16
5140 IP14_15_12
5141 IP14_11_8
5142 IP14_7_4
5143 IP14_3_0 }
5144 },
5146 IP15_31_28
5147 IP15_27_24
5148 IP15_23_20
5149 IP15_19_16
5150 IP15_15_12
5151 IP15_11_8
5152 IP15_7_4
5153 IP15_3_0 }
5154 },
5156 IP16_31_28
5157 IP16_27_24
5158 IP16_23_20
5159 IP16_19_16
5160 IP16_15_12
5161 IP16_11_8
5162 IP16_7_4
5163 IP16_3_0 }
5164 },
5166 IP17_31_28
5167 IP17_27_24
5168 IP17_23_20
5169 IP17_19_16
5170 IP17_15_12
5171 IP17_11_8
5172 IP17_7_4
5173 IP17_3_0 }
5174 },
5182 IP18_7_4
5183 IP18_3_0 }
5184 },
5185 #undef F_
5186 #undef FM
5188 #define F_(x, y) x,
5189 #define FM(x) FN_##x,
5193 MOD_SEL0_31_30_29
5194 MOD_SEL0_28_27
5195 MOD_SEL0_26_25_24
5196 MOD_SEL0_23
5197 MOD_SEL0_22
5198 MOD_SEL0_21
5199 MOD_SEL0_20
5200 MOD_SEL0_19
5201 MOD_SEL0_18_17
5202 MOD_SEL0_16
5204 MOD_SEL0_14_13
5205 MOD_SEL0_12
5206 MOD_SEL0_11
5207 MOD_SEL0_10
5208 MOD_SEL0_9_8
5209 MOD_SEL0_7_6
5210 MOD_SEL0_5
5211 MOD_SEL0_4_3
5212 /* RESERVED 2, 1, 0 */
5214 },
5218 MOD_SEL1_31_30
5219 MOD_SEL1_29_28_27
5220 MOD_SEL1_26
5221 MOD_SEL1_25_24
5222 MOD_SEL1_23_22_21
5223 MOD_SEL1_20
5224 MOD_SEL1_19
5225 MOD_SEL1_18_17
5226 MOD_SEL1_16
5227 MOD_SEL1_15_14
5228 MOD_SEL1_13
5229 MOD_SEL1_12
5230 MOD_SEL1_11
5231 MOD_SEL1_10
5232 MOD_SEL1_9
5234 MOD_SEL1_6
5235 MOD_SEL1_5
5236 MOD_SEL1_4
5237 MOD_SEL1_3
5238 MOD_SEL1_2
5239 MOD_SEL1_1
5240 MOD_SEL1_0 }
5241 },
5245 MOD_SEL2_31
5246 MOD_SEL2_30
5247 MOD_SEL2_29
5248 MOD_SEL2_28_27
5249 MOD_SEL2_26
5250 MOD_SEL2_25_24_23
5251 /* RESERVED 22 */
5253 MOD_SEL2_21
5254 MOD_SEL2_20
5255 MOD_SEL2_19
5256 MOD_SEL2_18
5257 MOD_SEL2_17
5258 /* RESERVED 16 */
5260 /* RESERVED 15, 14, 13, 12 */
5263 /* RESERVED 11, 10, 9, 8 */
5266 /* RESERVED 7, 6, 5, 4 */
5269 /* RESERVED 3, 2, 1 */
5271 MOD_SEL2_0 }
5272 },
5273 { },
5274 };
5286 } },
5296 } },
5306 } },
5316 } },
5326 } },
5336 } },
5346 } },
5356 } },
5366 } },
5376 } },
5386 } },
5396 } },
5402 } },
5412 } },
5422 } },
5432 } },
5442 } },
5452 } },
5462 } },
5472 } },
5482 } },
5492 } },
5502 } },
5512 } },
5521 } },
5522 { },
5523 };
5526 POCCTRL,
5527 };
5532 };
5535 {
5547 }
5583 } },
5617 } },
5651 } },
5685 } },
5719 } },
5753 } },
5787 } },
5789 };
5793 {
5805 else
5807 }
5811 {
5830 }
5835 };
5838 {
5843 }
5850 };
5873 };