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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / pinctrl / sh-pfc / sh_pfc.h
blob5747ab0472df34826111ed4055b0dfa8de37fdd6
1 /*
2 * SuperH Pin Function Controller Support
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11 #ifndef __SH_PFC_H
12 #define __SH_PFC_H
13
14 #include <linux/bug.h>
15 #include <linux/pinctrl/pinconf-generic.h>
16 #include <linux/spinlock.h>
17 #include <linux/stringify.h>
18
19 enum {
20 PINMUX_TYPE_NONE,
21 PINMUX_TYPE_FUNCTION,
22 PINMUX_TYPE_GPIO,
23 PINMUX_TYPE_OUTPUT,
24 PINMUX_TYPE_INPUT,
25 };
26
27 #define SH_PFC_PIN_CFG_INPUT (1 << 0)
28 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
29 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
30 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
31 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
32 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
33 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
34
35 struct sh_pfc_pin {
36 u16 pin;
37 u16 enum_id;
38 const char *name;
39 unsigned int configs;
40 };
41
42 #define SH_PFC_PIN_GROUP(n) \
43 { \
44 .name = #n, \
45 .pins = n##_pins, \
46 .mux = n##_mux, \
47 .nr_pins = ARRAY_SIZE(n##_pins), \
48 }
49
50 struct sh_pfc_pin_group {
51 const char *name;
52 const unsigned int *pins;
53 const unsigned int *mux;
54 unsigned int nr_pins;
55 };
56
57 /*
58 * Using union vin_data saves memory occupied by the VIN data pins.
59 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
60 * in this case.
61 */
62 #define VIN_DATA_PIN_GROUP(n, s) \
63 { \
64 .name = #n#s, \
65 .pins = n##_pins.data##s, \
66 .mux = n##_mux.data##s, \
67 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
68 }
69
70 union vin_data {
71 unsigned int data24[24];
72 unsigned int data20[20];
73 unsigned int data16[16];
74 unsigned int data12[12];
75 unsigned int data10[10];
76 unsigned int data8[8];
77 unsigned int data4[4];
78 };
79
80 #define SH_PFC_FUNCTION(n) \
81 { \
82 .name = #n, \
83 .groups = n##_groups, \
84 .nr_groups = ARRAY_SIZE(n##_groups), \
85 }
86
87 struct sh_pfc_function {
88 const char *name;
89 const char * const *groups;
90 unsigned int nr_groups;
91 };
92
93 struct pinmux_func {
94 u16 enum_id;
95 const char *name;
96 };
97
98 struct pinmux_cfg_reg {
99 u32 reg;
100 u8 reg_width, field_width;
101 const u16 *enum_ids;
102 const u8 *var_field_width;
103 };
104
105 /*
106 * Describe a config register consisting of several fields of the same width
107 * - name: Register name (unused, for documentation purposes only)
108 * - r: Physical register address
109 * - r_width: Width of the register (in bits)
110 * - f_width: Width of the fixed-width register fields (in bits)
111 * This macro must be followed by initialization data: For each register field
112 * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
113 * one for each possible combination of the register field bit values.
114 */
115 #define PINMUX_CFG_REG(name, r, r_width, f_width) \
116 .reg = r, .reg_width = r_width, .field_width = f_width, \
117 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
118
119 /*
120 * Describe a config register consisting of several fields of different widths
121 * - name: Register name (unused, for documentation purposes only)
122 * - r: Physical register address
123 * - r_width: Width of the register (in bits)
124 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
125 * From left to right (i.e. MSB to LSB)
126 * This macro must be followed by initialization data: For each register field
127 * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
128 * one for each possible combination of the register field bit values.
129 */
130 #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
131 .reg = r, .reg_width = r_width, \
132 .var_field_width = (const u8 [r_width]) \
133 { var_fw0, var_fwn, 0 }, \
134 .enum_ids = (const u16 [])
135
136 struct pinmux_drive_reg_field {
137 u16 pin;
138 u8 offset;
139 u8 size;
140 };
141
142 struct pinmux_drive_reg {
143 u32 reg;
144 const struct pinmux_drive_reg_field fields[8];
145 };
146
147 #define PINMUX_DRIVE_REG(name, r) \
148 .reg = r, \
149 .fields =
150
151 struct pinmux_bias_reg {
152 u32 puen; /* Pull-enable or pull-up control register */
153 u32 pud; /* Pull-up/down control register (optional) */
154 const u16 pins[32];
155 };
156
157 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
158 .puen = r1, \
159 .pud = r2, \
160 .pins =
161
162 struct pinmux_ioctrl_reg {
163 u32 reg;
164 };
165
166 struct pinmux_data_reg {
167 u32 reg;
168 u8 reg_width;
169 const u16 *enum_ids;
170 };
171
172 /*
173 * Describe a data register
174 * - name: Register name (unused, for documentation purposes only)
175 * - r: Physical register address
176 * - r_width: Width of the register (in bits)
177 * This macro must be followed by initialization data: For each register bit
178 * (from left to right, i.e. MSB to LSB), one enum ID must be specified.
179 */
180 #define PINMUX_DATA_REG(name, r, r_width) \
181 .reg = r, .reg_width = r_width, \
182 .enum_ids = (const u16 [r_width]) \
183
184 struct pinmux_irq {
185 const short *gpios;
186 };
187
188 /*
189 * Describe the mapping from GPIOs to a single IRQ
190 * - ids...: List of GPIOs that are mapped to the same IRQ
191 */
192 #define PINMUX_IRQ(ids...) \
193 { .gpios = (const short []) { ids, -1 } }
194
195 struct pinmux_range {
196 u16 begin;
197 u16 end;
198 u16 force;
199 };
200
201 struct sh_pfc_window {
202 phys_addr_t phys;
203 void __iomem *virt;
204 unsigned long size;
205 };
206
207 struct sh_pfc_pin_range;
208
209 struct sh_pfc {
210 struct device *dev;
211 const struct sh_pfc_soc_info *info;
212 spinlock_t lock;
213
214 unsigned int num_windows;
215 struct sh_pfc_window *windows;
216 unsigned int num_irqs;
217 unsigned int *irqs;
218
219 struct sh_pfc_pin_range *ranges;
220 unsigned int nr_ranges;
221
222 unsigned int nr_gpio_pins;
223
224 struct sh_pfc_chip *gpio;
225 u32 *saved_regs;
226 };
227
228 struct sh_pfc_soc_operations {
229 int (*init)(struct sh_pfc *pfc);
230 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
231 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
232 unsigned int bias);
233 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
234 };
235
236 struct sh_pfc_soc_info {
237 const char *name;
238 const struct sh_pfc_soc_operations *ops;
239
240 struct pinmux_range input;
241 struct pinmux_range output;
242 struct pinmux_range function;
243
244 const struct sh_pfc_pin *pins;
245 unsigned int nr_pins;
246 const struct sh_pfc_pin_group *groups;
247 unsigned int nr_groups;
248 const struct sh_pfc_function *functions;
249 unsigned int nr_functions;
250
251 #ifdef CONFIG_SUPERH
252 const struct pinmux_func *func_gpios;
253 unsigned int nr_func_gpios;
254 #endif
255
256 const struct pinmux_cfg_reg *cfg_regs;
257 const struct pinmux_drive_reg *drive_regs;
258 const struct pinmux_bias_reg *bias_regs;
259 const struct pinmux_ioctrl_reg *ioctrl_regs;
260 const struct pinmux_data_reg *data_regs;
261
262 const u16 *pinmux_data;
263 unsigned int pinmux_data_size;
264
265 const struct pinmux_irq *gpio_irq;
266 unsigned int gpio_irq_size;
267
268 u32 unlock_reg;
269 };
270
271 extern const struct sh_pfc_soc_info emev2_pinmux_info;
272 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
273 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
274 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
275 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
276 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
277 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
278 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
279 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
280 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
281 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
282 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
283 extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
284 extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
285 extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
286 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
287 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
288 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
289 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
290 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
291 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
292 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
293 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
294 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
295 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
296 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
297 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
298 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
299 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
300 extern const struct sh_pfc_soc_info shx3_pinmux_info;
301
302 /* -----------------------------------------------------------------------------
303 * Helper macros to create pin and port lists
304 */
305
306 /*
307 * sh_pfc_soc_info pinmux_data array macros
308 */
309
310 /*
311 * Describe generic pinmux data
312 * - data_or_mark: *_DATA or *_MARK enum ID
313 * - ids...: List of enum IDs to associate with data_or_mark
314 */
315 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
316
317 /*
318 * Describe a pinmux configuration without GPIO function that needs
319 * configuration in a Peripheral Function Select Register (IPSR)
320 * - ipsr: IPSR field (unused, for documentation purposes only)
321 * - fn: Function name, referring to a field in the IPSR
322 */
323 #define PINMUX_IPSR_NOGP(ipsr, fn) \
324 PINMUX_DATA(fn##_MARK, FN_##fn)
325
326 /*
327 * Describe a pinmux configuration with GPIO function that needs configuration
328 * in both a Peripheral Function Select Register (IPSR) and in a
329 * GPIO/Peripheral Function Select Register (GPSR)
330 * - ipsr: IPSR field
331 * - fn: Function name, also referring to the IPSR field
332 */
333 #define PINMUX_IPSR_GPSR(ipsr, fn) \
334 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
335
336 /*
337 * Describe a pinmux configuration without GPIO function that needs
338 * configuration in a Peripheral Function Select Register (IPSR), and where the
339 * pinmux function has a representation in a Module Select Register (MOD_SEL).
340 * - ipsr: IPSR field (unused, for documentation purposes only)
341 * - fn: Function name, also referring to the IPSR field
342 * - msel: Module selector
343 */
344 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
345 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
346
347 /*
348 * Describe a pinmux configuration with GPIO function where the pinmux function
349 * has no representation in a Peripheral Function Select Register (IPSR), but
350 * instead solely depends on a group selection.
351 * - gpsr: GPSR field
352 * - fn: Function name, also referring to the GPSR field
353 * - gsel: Group selector
354 */
355 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
356 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
357
358 /*
359 * Describe a pinmux configuration with GPIO function that needs configuration
360 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
361 * Function Select Register (GPSR), and where the pinmux function has a
362 * representation in a Module Select Register (MOD_SEL).
363 * - ipsr: IPSR field
364 * - fn: Function name, also referring to the IPSR field
365 * - msel: Module selector
366 */
367 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
368 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
369
370 /*
371 * Describe a pinmux configuration for a single-function pin with GPIO
372 * capability.
373 * - fn: Function name
374 */
375 #define PINMUX_SINGLE(fn) \
376 PINMUX_DATA(fn##_MARK, FN_##fn)
377
378 /*
379 * GP port style (32 ports banks)
380 */
381
382 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
383 fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
384 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
385
386 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
387 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
388 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
389 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
390 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
391 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
392
393 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
394 PORT_GP_CFG_4(bank, fn, sfx, cfg), \
395 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
396 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
397 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
398
399 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
400 PORT_GP_CFG_6(bank, fn, sfx, cfg), \
401 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
402 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
403 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
404
405 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
406 PORT_GP_CFG_8(bank, fn, sfx, cfg), \
407 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
408 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
409
410 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
411 PORT_GP_CFG_9(bank, fn, sfx, cfg), \
412 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
413 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
414
415 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
416 PORT_GP_CFG_10(bank, fn, sfx, cfg), \
417 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
418 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
419 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
420
421 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
422 PORT_GP_CFG_12(bank, fn, sfx, cfg), \
423 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
424 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
425 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
426
427 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
428 PORT_GP_CFG_14(bank, fn, sfx, cfg), \
429 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
430 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
431
432 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
433 PORT_GP_CFG_15(bank, fn, sfx, cfg), \
434 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
435 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
436
437 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
438 PORT_GP_CFG_16(bank, fn, sfx, cfg), \
439 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
440 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
441
442 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
443 PORT_GP_CFG_17(bank, fn, sfx, cfg), \
444 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
445 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
446
447 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
448 PORT_GP_CFG_18(bank, fn, sfx, cfg), \
449 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
450 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
451 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
452
453 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
454 PORT_GP_CFG_20(bank, fn, sfx, cfg), \
455 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
456 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
457
458 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
459 PORT_GP_CFG_21(bank, fn, sfx, cfg), \
460 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
461 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
462
463 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
464 PORT_GP_CFG_22(bank, fn, sfx, cfg), \
465 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
466 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
467
468 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
469 PORT_GP_CFG_23(bank, fn, sfx, cfg), \
470 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
471 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
472
473 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
474 PORT_GP_CFG_24(bank, fn, sfx, cfg), \
475 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
476 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
477 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
478
479 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
480 PORT_GP_CFG_26(bank, fn, sfx, cfg), \
481 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
482 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
483 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
484
485 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
486 PORT_GP_CFG_28(bank, fn, sfx, cfg), \
487 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
488 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
489
490 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
491 PORT_GP_CFG_29(bank, fn, sfx, cfg), \
492 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
493 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
494
495 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
496 PORT_GP_CFG_30(bank, fn, sfx, cfg), \
497 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
498 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
499 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
500
501 #define PORT_GP_32_REV(bank, fn, sfx) \
502 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
503 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
504 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
505 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
506 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
507 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
508 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
509 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
510 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
511 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
512 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
513 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
514 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
515 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
516 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
517 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
518
519 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
520 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
521 #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
522
523 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
524 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
525 { \
526 .pin = (bank * 32) + _pin, \
527 .name = __stringify(_name), \
528 .enum_id = _name##_DATA, \
529 .configs = cfg, \
530 }
531 #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
532
533 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
534 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
535 #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
536
537 /*
538 * PORT style (linear pin space)
539 */
540
541 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
542
543 #define PORT_10(pn, fn, pfx, sfx) \
544 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
545 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
546 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
547 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
548 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
549
550 #define PORT_90(pn, fn, pfx, sfx) \
551 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
552 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
553 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
554 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
555 PORT_10(pn+90, fn, pfx##9, sfx)
556
557 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
558 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
559 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
560
561 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
562 #define PINMUX_GPIO(_pin) \
563 [GPIO_##_pin] = { \
564 .pin = (u16)-1, \
565 .name = __stringify(GPIO_##_pin), \
566 .enum_id = _pin##_DATA, \
567 }
568
569 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
570 #define SH_PFC_PIN_CFG(_pin, cfgs) \
571 { \
572 .pin = _pin, \
573 .name = __stringify(PORT##_pin), \
574 .enum_id = PORT##_pin##_DATA, \
575 .configs = cfgs, \
576 }
577
578 /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
579 #define SH_PFC_PIN_NAMED(row, col, _name) \
580 { \
581 .pin = PIN_NUMBER(row, col), \
582 .name = __stringify(PIN_##_name), \
583 .configs = SH_PFC_PIN_CFG_NO_GPIO, \
584 }
585
586 /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
587 #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
588 { \
589 .pin = PIN_NUMBER(row, col), \
590 .name = __stringify(PIN_##_name), \
591 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
592 }
593
594 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
595 * PORT_name_OUT, PORT_name_IN marks
596 */
597 #define _PORT_DATA(pn, pfx, sfx) \
598 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
599 PORT##pfx##_OUT, PORT##pfx##_IN)
600 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
601
602 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
603 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
604 [gpio - (base)] = { \
605 .name = __stringify(gpio), \
606 .enum_id = data_or_mark, \
607 }
608 #define GPIO_FN(str) \
609 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
610
611 /*
612 * PORTnCR helper macro for SH-Mobile/R-Mobile
613 */
614 #define PORTCR(nr, reg) \
615 { \
616 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
617 /* PULMD[1:0], handled by .set_bias() */ \
618 0, 0, 0, 0, \
619 /* IE and OE */ \
620 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
621 /* SEC, not supported */ \
622 0, 0, \
623 /* PTMD[2:0] */ \
624 PORT##nr##_FN0, PORT##nr##_FN1, \
625 PORT##nr##_FN2, PORT##nr##_FN3, \
626 PORT##nr##_FN4, PORT##nr##_FN5, \
627 PORT##nr##_FN6, PORT##nr##_FN7 \
628 } \
629 }
630
631 /*
632 * GPIO number helper macro for R-Car
633 */
634 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
635
636 #endif /* __SH_PFC_H */
CRIS linux kernel tree