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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / scsi / aacraid / src.c
blobfde6b6aa86e38a1af487d94b1117f3ffc340c5a5
1 /*
2 * Adaptec AAC series RAID controller driver
3 * (c) Copyright 2001 Red Hat Inc.
4 *
5 * based on the old aacraid driver that is..
6 * Adaptec aacraid device driver for Linux.
7 *
8 * Copyright (c) 2000-2010 Adaptec, Inc.
9 * 2010-2015 PMC-Sierra, Inc. (aacraid@pmc-sierra.com)
10 * 2016-2017 Microsemi Corp. (aacraid@microsemi.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Module Name:
27 * src.c
28 *
29 * Abstract: Hardware Device Interface for PMC SRC based controllers
30 *
31 */
32
33 #include <linux/kernel.h>
34 #include <linux/init.h>
35 #include <linux/types.h>
36 #include <linux/pci.h>
37 #include <linux/spinlock.h>
38 #include <linux/slab.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/completion.h>
42 #include <linux/time.h>
43 #include <linux/interrupt.h>
44 #include <scsi/scsi_host.h>
45
46 #include "aacraid.h"
47
48 static int aac_src_get_sync_status(struct aac_dev *dev);
49
50 static irqreturn_t aac_src_intr_message(int irq, void *dev_id)
51 {
52 struct aac_msix_ctx *ctx;
53 struct aac_dev *dev;
54 unsigned long bellbits, bellbits_shifted;
55 int vector_no;
56 int isFastResponse, mode;
57 u32 index, handle;
58
59 ctx = (struct aac_msix_ctx *)dev_id;
60 dev = ctx->dev;
61 vector_no = ctx->vector_no;
62
63 if (dev->msi_enabled) {
64 mode = AAC_INT_MODE_MSI;
65 if (vector_no == 0) {
66 bellbits = src_readl(dev, MUnit.ODR_MSI);
67 if (bellbits & 0x40000)
68 mode |= AAC_INT_MODE_AIF;
69 if (bellbits & 0x1000)
70 mode |= AAC_INT_MODE_SYNC;
71 }
72 } else {
73 mode = AAC_INT_MODE_INTX;
74 bellbits = src_readl(dev, MUnit.ODR_R);
75 if (bellbits & PmDoorBellResponseSent) {
76 bellbits = PmDoorBellResponseSent;
77 src_writel(dev, MUnit.ODR_C, bellbits);
78 src_readl(dev, MUnit.ODR_C);
79 } else {
80 bellbits_shifted = (bellbits >> SRC_ODR_SHIFT);
81 src_writel(dev, MUnit.ODR_C, bellbits);
82 src_readl(dev, MUnit.ODR_C);
83
84 if (bellbits_shifted & DoorBellAifPending)
85 mode |= AAC_INT_MODE_AIF;
86 else if (bellbits_shifted & OUTBOUNDDOORBELL_0)
87 mode |= AAC_INT_MODE_SYNC;
88 }
89 }
90
91 if (mode & AAC_INT_MODE_SYNC) {
92 unsigned long sflags;
93 struct list_head *entry;
94 int send_it = 0;
95 extern int aac_sync_mode;
96
97 if (!aac_sync_mode && !dev->msi_enabled) {
98 src_writel(dev, MUnit.ODR_C, bellbits);
99 src_readl(dev, MUnit.ODR_C);
100 }
101
102 if (dev->sync_fib) {
103 if (dev->sync_fib->callback)
104 dev->sync_fib->callback(dev->sync_fib->callback_data,
105 dev->sync_fib);
106 spin_lock_irqsave(&dev->sync_fib->event_lock, sflags);
107 if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) {
108 dev->management_fib_count--;
109 up(&dev->sync_fib->event_wait);
110 }
111 spin_unlock_irqrestore(&dev->sync_fib->event_lock,
112 sflags);
113 spin_lock_irqsave(&dev->sync_lock, sflags);
114 if (!list_empty(&dev->sync_fib_list)) {
115 entry = dev->sync_fib_list.next;
116 dev->sync_fib = list_entry(entry,
117 struct fib,
118 fiblink);
119 list_del(entry);
120 send_it = 1;
121 } else {
122 dev->sync_fib = NULL;
123 }
124 spin_unlock_irqrestore(&dev->sync_lock, sflags);
125 if (send_it) {
126 aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB,
127 (u32)dev->sync_fib->hw_fib_pa,
128 0, 0, 0, 0, 0,
129 NULL, NULL, NULL, NULL, NULL);
130 }
131 }
132 if (!dev->msi_enabled)
133 mode = 0;
134
135 }
136
137 if (mode & AAC_INT_MODE_AIF) {
138 /* handle AIF */
139 if (dev->sa_firmware) {
140 u32 events = src_readl(dev, MUnit.SCR0);
141
142 aac_intr_normal(dev, events, 1, 0, NULL);
143 writel(events, &dev->IndexRegs->Mailbox[0]);
144 src_writel(dev, MUnit.IDR, 1 << 23);
145 } else {
146 if (dev->aif_thread && dev->fsa_dev)
147 aac_intr_normal(dev, 0, 2, 0, NULL);
148 }
149 if (dev->msi_enabled)
150 aac_src_access_devreg(dev, AAC_CLEAR_AIF_BIT);
151 mode = 0;
152 }
153
154 if (mode) {
155 index = dev->host_rrq_idx[vector_no];
156
157 for (;;) {
158 isFastResponse = 0;
159 /* remove toggle bit (31) */
160 handle = le32_to_cpu((dev->host_rrq[index])
161 & 0x7fffffff);
162 /* check fast response bits (30, 1) */
163 if (handle & 0x40000000)
164 isFastResponse = 1;
165 handle &= 0x0000ffff;
166 if (handle == 0)
167 break;
168 handle >>= 2;
169 if (dev->msi_enabled && dev->max_msix > 1)
170 atomic_dec(&dev->rrq_outstanding[vector_no]);
171 aac_intr_normal(dev, handle, 0, isFastResponse, NULL);
172 dev->host_rrq[index++] = 0;
173 if (index == (vector_no + 1) * dev->vector_cap)
174 index = vector_no * dev->vector_cap;
175 dev->host_rrq_idx[vector_no] = index;
176 }
177 mode = 0;
178 }
179
180 return IRQ_HANDLED;
181 }
182
183 /**
184 * aac_src_disable_interrupt - Disable interrupts
185 * @dev: Adapter
186 */
187
188 static void aac_src_disable_interrupt(struct aac_dev *dev)
189 {
190 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
191 }
192
193 /**
194 * aac_src_enable_interrupt_message - Enable interrupts
195 * @dev: Adapter
196 */
197
198 static void aac_src_enable_interrupt_message(struct aac_dev *dev)
199 {
200 aac_src_access_devreg(dev, AAC_ENABLE_INTERRUPT);
201 }
202
203 /**
204 * src_sync_cmd - send a command and wait
205 * @dev: Adapter
206 * @command: Command to execute
207 * @p1: first parameter
208 * @ret: adapter status
209 *
210 * This routine will send a synchronous command to the adapter and wait
211 * for its completion.
212 */
213
214 static int src_sync_cmd(struct aac_dev *dev, u32 command,
215 u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6,
216 u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4)
217 {
218 unsigned long start;
219 unsigned long delay;
220 int ok;
221
222 /*
223 * Write the command into Mailbox 0
224 */
225 writel(command, &dev->IndexRegs->Mailbox[0]);
226 /*
227 * Write the parameters into Mailboxes 1 - 6
228 */
229 writel(p1, &dev->IndexRegs->Mailbox[1]);
230 writel(p2, &dev->IndexRegs->Mailbox[2]);
231 writel(p3, &dev->IndexRegs->Mailbox[3]);
232 writel(p4, &dev->IndexRegs->Mailbox[4]);
233
234 /*
235 * Clear the synch command doorbell to start on a clean slate.
236 */
237 if (!dev->msi_enabled)
238 src_writel(dev,
239 MUnit.ODR_C,
240 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
241
242 /*
243 * Disable doorbell interrupts
244 */
245 src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff);
246
247 /*
248 * Force the completion of the mask register write before issuing
249 * the interrupt.
250 */
251 src_readl(dev, MUnit.OIMR);
252
253 /*
254 * Signal that there is a new synch command
255 */
256 src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT);
257
258 if (!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) {
259 ok = 0;
260 start = jiffies;
261
262 if (command == IOP_RESET_ALWAYS) {
263 /* Wait up to 10 sec */
264 delay = 10*HZ;
265 } else {
266 /* Wait up to 5 minutes */
267 delay = 300*HZ;
268 }
269 while (time_before(jiffies, start+delay)) {
270 udelay(5); /* Delay 5 microseconds to let Mon960 get info. */
271 /*
272 * Mon960 will set doorbell0 bit when it has completed the command.
273 */
274 if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) {
275 /*
276 * Clear the doorbell.
277 */
278 if (dev->msi_enabled)
279 aac_src_access_devreg(dev,
280 AAC_CLEAR_SYNC_BIT);
281 else
282 src_writel(dev,
283 MUnit.ODR_C,
284 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
285 ok = 1;
286 break;
287 }
288 /*
289 * Yield the processor in case we are slow
290 */
291 msleep(1);
292 }
293 if (unlikely(ok != 1)) {
294 /*
295 * Restore interrupt mask even though we timed out
296 */
297 aac_adapter_enable_int(dev);
298 return -ETIMEDOUT;
299 }
300 /*
301 * Pull the synch status from Mailbox 0.
302 */
303 if (status)
304 *status = readl(&dev->IndexRegs->Mailbox[0]);
305 if (r1)
306 *r1 = readl(&dev->IndexRegs->Mailbox[1]);
307 if (r2)
308 *r2 = readl(&dev->IndexRegs->Mailbox[2]);
309 if (r3)
310 *r3 = readl(&dev->IndexRegs->Mailbox[3]);
311 if (r4)
312 *r4 = readl(&dev->IndexRegs->Mailbox[4]);
313 if (command == GET_COMM_PREFERRED_SETTINGS)
314 dev->max_msix =
315 readl(&dev->IndexRegs->Mailbox[5]) & 0xFFFF;
316 /*
317 * Clear the synch command doorbell.
318 */
319 if (!dev->msi_enabled)
320 src_writel(dev,
321 MUnit.ODR_C,
322 OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT);
323 }
324
325 /*
326 * Restore interrupt mask
327 */
328 aac_adapter_enable_int(dev);
329 return 0;
330 }
331
332 /**
333 * aac_src_interrupt_adapter - interrupt adapter
334 * @dev: Adapter
335 *
336 * Send an interrupt to the i960 and breakpoint it.
337 */
338
339 static void aac_src_interrupt_adapter(struct aac_dev *dev)
340 {
341 src_sync_cmd(dev, BREAKPOINT_REQUEST,
342 0, 0, 0, 0, 0, 0,
343 NULL, NULL, NULL, NULL, NULL);
344 }
345
346 /**
347 * aac_src_notify_adapter - send an event to the adapter
348 * @dev: Adapter
349 * @event: Event to send
350 *
351 * Notify the i960 that something it probably cares about has
352 * happened.
353 */
354
355 static void aac_src_notify_adapter(struct aac_dev *dev, u32 event)
356 {
357 switch (event) {
358
359 case AdapNormCmdQue:
360 src_writel(dev, MUnit.ODR_C,
361 INBOUNDDOORBELL_1 << SRC_ODR_SHIFT);
362 break;
363 case HostNormRespNotFull:
364 src_writel(dev, MUnit.ODR_C,
365 INBOUNDDOORBELL_4 << SRC_ODR_SHIFT);
366 break;
367 case AdapNormRespQue:
368 src_writel(dev, MUnit.ODR_C,
369 INBOUNDDOORBELL_2 << SRC_ODR_SHIFT);
370 break;
371 case HostNormCmdNotFull:
372 src_writel(dev, MUnit.ODR_C,
373 INBOUNDDOORBELL_3 << SRC_ODR_SHIFT);
374 break;
375 case FastIo:
376 src_writel(dev, MUnit.ODR_C,
377 INBOUNDDOORBELL_6 << SRC_ODR_SHIFT);
378 break;
379 case AdapPrintfDone:
380 src_writel(dev, MUnit.ODR_C,
381 INBOUNDDOORBELL_5 << SRC_ODR_SHIFT);
382 break;
383 default:
384 BUG();
385 break;
386 }
387 }
388
389 /**
390 * aac_src_start_adapter - activate adapter
391 * @dev: Adapter
392 *
393 * Start up processing on an i960 based AAC adapter
394 */
395
396 static void aac_src_start_adapter(struct aac_dev *dev)
397 {
398 union aac_init *init;
399 int i;
400
401 /* reset host_rrq_idx first */
402 for (i = 0; i < dev->max_msix; i++) {
403 dev->host_rrq_idx[i] = i * dev->vector_cap;
404 atomic_set(&dev->rrq_outstanding[i], 0);
405 }
406 atomic_set(&dev->msix_counter, 0);
407 dev->fibs_pushed_no = 0;
408
409 init = dev->init;
410 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
411 init->r8.host_elapsed_seconds = cpu_to_le32(get_seconds());
412 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
413 lower_32_bits(dev->init_pa),
414 upper_32_bits(dev->init_pa),
415 sizeof(struct _r8) +
416 (AAC_MAX_HRRQ - 1) * sizeof(struct _rrq),
417 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
418 } else {
419 init->r7.host_elapsed_seconds = cpu_to_le32(get_seconds());
420 // We can only use a 32 bit address here
421 src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS,
422 (u32)(ulong)dev->init_pa, 0, 0, 0, 0, 0,
423 NULL, NULL, NULL, NULL, NULL);
424 }
425
426 }
427
428 /**
429 * aac_src_check_health
430 * @dev: device to check if healthy
431 *
432 * Will attempt to determine if the specified adapter is alive and
433 * capable of handling requests, returning 0 if alive.
434 */
435 static int aac_src_check_health(struct aac_dev *dev)
436 {
437 u32 status = src_readl(dev, MUnit.OMR);
438
439 /*
440 * Check to see if the board panic'd.
441 */
442 if (unlikely(status & KERNEL_PANIC))
443 goto err_blink;
444
445 /*
446 * Check to see if the board failed any self tests.
447 */
448 if (unlikely(status & SELF_TEST_FAILED))
449 goto err_out;
450
451 /*
452 * Check to see if the board failed any self tests.
453 */
454 if (unlikely(status & MONITOR_PANIC))
455 goto err_out;
456
457 /*
458 * Wait for the adapter to be up and running.
459 */
460 if (unlikely(!(status & KERNEL_UP_AND_RUNNING)))
461 return -3;
462 /*
463 * Everything is OK
464 */
465 return 0;
466
467 err_out:
468 return -1;
469
470 err_blink:
471 return (status >> 16) & 0xFF;
472 }
473
474 static inline u32 aac_get_vector(struct aac_dev *dev)
475 {
476 return atomic_inc_return(&dev->msix_counter)%dev->max_msix;
477 }
478
479 /**
480 * aac_src_deliver_message
481 * @fib: fib to issue
482 *
483 * Will send a fib, returning 0 if successful.
484 */
485 static int aac_src_deliver_message(struct fib *fib)
486 {
487 struct aac_dev *dev = fib->dev;
488 struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue];
489 u32 fibsize;
490 dma_addr_t address;
491 struct aac_fib_xporthdr *pFibX;
492 int native_hba;
493 #if !defined(writeq)
494 unsigned long flags;
495 #endif
496
497 u16 vector_no;
498
499 atomic_inc(&q->numpending);
500
501 native_hba = (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA) ? 1 : 0;
502
503
504 if (dev->msi_enabled && dev->max_msix > 1 &&
505 (native_hba || fib->hw_fib_va->header.Command != AifRequest)) {
506
507 if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE3)
508 && dev->sa_firmware)
509 vector_no = aac_get_vector(dev);
510 else
511 vector_no = fib->vector_no;
512
513 if (native_hba) {
514 if (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA_TMF) {
515 struct aac_hba_tm_req *tm_req;
516
517 tm_req = (struct aac_hba_tm_req *)
518 fib->hw_fib_va;
519 if (tm_req->iu_type ==
520 HBA_IU_TYPE_SCSI_TM_REQ) {
521 ((struct aac_hba_tm_req *)
522 fib->hw_fib_va)->reply_qid
523 = vector_no;
524 ((struct aac_hba_tm_req *)
525 fib->hw_fib_va)->request_id
526 += (vector_no << 16);
527 } else {
528 ((struct aac_hba_reset_req *)
529 fib->hw_fib_va)->reply_qid
530 = vector_no;
531 ((struct aac_hba_reset_req *)
532 fib->hw_fib_va)->request_id
533 += (vector_no << 16);
534 }
535 } else {
536 ((struct aac_hba_cmd_req *)
537 fib->hw_fib_va)->reply_qid
538 = vector_no;
539 ((struct aac_hba_cmd_req *)
540 fib->hw_fib_va)->request_id
541 += (vector_no << 16);
542 }
543 } else {
544 fib->hw_fib_va->header.Handle += (vector_no << 16);
545 }
546 } else {
547 vector_no = 0;
548 }
549
550 atomic_inc(&dev->rrq_outstanding[vector_no]);
551
552 if (native_hba) {
553 address = fib->hw_fib_pa;
554 fibsize = (fib->hbacmd_size + 127) / 128 - 1;
555 if (fibsize > 31)
556 fibsize = 31;
557 address |= fibsize;
558 #if defined(writeq)
559 src_writeq(dev, MUnit.IQN_L, (u64)address);
560 #else
561 spin_lock_irqsave(&fib->dev->iq_lock, flags);
562 src_writel(dev, MUnit.IQN_H,
563 upper_32_bits(address) & 0xffffffff);
564 src_writel(dev, MUnit.IQN_L, address & 0xffffffff);
565 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
566 #endif
567 } else {
568 if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2 ||
569 dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) {
570 /* Calculate the amount to the fibsize bits */
571 fibsize = (le16_to_cpu(fib->hw_fib_va->header.Size)
572 + 127) / 128 - 1;
573 /* New FIB header, 32-bit */
574 address = fib->hw_fib_pa;
575 fib->hw_fib_va->header.StructType = FIB_MAGIC2;
576 fib->hw_fib_va->header.SenderFibAddress =
577 cpu_to_le32((u32)address);
578 fib->hw_fib_va->header.u.TimeStamp = 0;
579 WARN_ON(upper_32_bits(address) != 0L);
580 } else {
581 /* Calculate the amount to the fibsize bits */
582 fibsize = (sizeof(struct aac_fib_xporthdr) +
583 le16_to_cpu(fib->hw_fib_va->header.Size)
584 + 127) / 128 - 1;
585 /* Fill XPORT header */
586 pFibX = (struct aac_fib_xporthdr *)
587 ((unsigned char *)fib->hw_fib_va -
588 sizeof(struct aac_fib_xporthdr));
589 pFibX->Handle = fib->hw_fib_va->header.Handle;
590 pFibX->HostAddress =
591 cpu_to_le64((u64)fib->hw_fib_pa);
592 pFibX->Size = cpu_to_le32(
593 le16_to_cpu(fib->hw_fib_va->header.Size));
594 address = fib->hw_fib_pa -
595 (u64)sizeof(struct aac_fib_xporthdr);
596 }
597 if (fibsize > 31)
598 fibsize = 31;
599 address |= fibsize;
600
601 #if defined(writeq)
602 src_writeq(dev, MUnit.IQ_L, (u64)address);
603 #else
604 spin_lock_irqsave(&fib->dev->iq_lock, flags);
605 src_writel(dev, MUnit.IQ_H,
606 upper_32_bits(address) & 0xffffffff);
607 src_writel(dev, MUnit.IQ_L, address & 0xffffffff);
608 spin_unlock_irqrestore(&fib->dev->iq_lock, flags);
609 #endif
610 }
611 return 0;
612 }
613
614 /**
615 * aac_src_ioremap
616 * @size: mapping resize request
617 *
618 */
619 static int aac_src_ioremap(struct aac_dev *dev, u32 size)
620 {
621 if (!size) {
622 iounmap(dev->regs.src.bar1);
623 dev->regs.src.bar1 = NULL;
624 iounmap(dev->regs.src.bar0);
625 dev->base = dev->regs.src.bar0 = NULL;
626 return 0;
627 }
628 dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2),
629 AAC_MIN_SRC_BAR1_SIZE);
630 dev->base = NULL;
631 if (dev->regs.src.bar1 == NULL)
632 return -1;
633 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
634 if (dev->base == NULL) {
635 iounmap(dev->regs.src.bar1);
636 dev->regs.src.bar1 = NULL;
637 return -1;
638 }
639 dev->IndexRegs = &((struct src_registers __iomem *)
640 dev->base)->u.tupelo.IndexRegs;
641 return 0;
642 }
643
644 /**
645 * aac_srcv_ioremap
646 * @size: mapping resize request
647 *
648 */
649 static int aac_srcv_ioremap(struct aac_dev *dev, u32 size)
650 {
651 if (!size) {
652 iounmap(dev->regs.src.bar0);
653 dev->base = dev->regs.src.bar0 = NULL;
654 return 0;
655 }
656
657 dev->regs.src.bar1 =
658 ioremap(pci_resource_start(dev->pdev, 2), AAC_MIN_SRCV_BAR1_SIZE);
659 dev->base = NULL;
660 if (dev->regs.src.bar1 == NULL)
661 return -1;
662 dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size);
663 if (dev->base == NULL) {
664 iounmap(dev->regs.src.bar1);
665 dev->regs.src.bar1 = NULL;
666 return -1;
667 }
668 dev->IndexRegs = &((struct src_registers __iomem *)
669 dev->base)->u.denali.IndexRegs;
670 return 0;
671 }
672
673 void aac_set_intx_mode(struct aac_dev *dev)
674 {
675 if (dev->msi_enabled) {
676 aac_src_access_devreg(dev, AAC_ENABLE_INTX);
677 dev->msi_enabled = 0;
678 msleep(5000); /* Delay 5 seconds */
679 }
680 }
681
682 static void aac_dump_fw_fib_iop_reset(struct aac_dev *dev)
683 {
684 __le32 supported_options3;
685
686 if (!aac_fib_dump)
687 return;
688
689 supported_options3 = dev->supplement_adapter_info.supported_options3;
690 if (!(supported_options3 & AAC_OPTION_SUPPORTED3_IOP_RESET_FIB_DUMP))
691 return;
692
693 aac_adapter_sync_cmd(dev, IOP_RESET_FW_FIB_DUMP,
694 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL);
695 }
696
697 static bool aac_is_ctrl_up_and_running(struct aac_dev *dev)
698 {
699 bool ctrl_up = true;
700 unsigned long status, start;
701 bool is_up = false;
702
703 start = jiffies;
704 do {
705 schedule();
706 status = src_readl(dev, MUnit.OMR);
707
708 if (status == 0xffffffff)
709 status = 0;
710
711 if (status & KERNEL_BOOTING) {
712 start = jiffies;
713 continue;
714 }
715
716 if (time_after(jiffies, start+HZ*SOFT_RESET_TIME)) {
717 ctrl_up = false;
718 break;
719 }
720
721 is_up = status & KERNEL_UP_AND_RUNNING;
722
723 } while (!is_up);
724
725 return ctrl_up;
726 }
727
728 static void aac_notify_fw_of_iop_reset(struct aac_dev *dev)
729 {
730 aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS, 0, 0, 0, 0, 0, 0, NULL,
731 NULL, NULL, NULL, NULL);
732 }
733
734 static void aac_send_iop_reset(struct aac_dev *dev)
735 {
736 aac_dump_fw_fib_iop_reset(dev);
737
738 aac_notify_fw_of_iop_reset(dev);
739
740 aac_set_intx_mode(dev);
741
742 src_writel(dev, MUnit.IDR, IOP_SRC_RESET_MASK);
743
744 msleep(5000);
745 }
746
747 static void aac_send_hardware_soft_reset(struct aac_dev *dev)
748 {
749 u_int32_t val;
750
751 val = readl(((char *)(dev->base) + IBW_SWR_OFFSET));
752 val |= 0x01;
753 writel(val, ((char *)(dev->base) + IBW_SWR_OFFSET));
754 msleep_interruptible(20000);
755 }
756
757 static int aac_src_restart_adapter(struct aac_dev *dev, int bled, u8 reset_type)
758 {
759 bool is_ctrl_up;
760 int ret = 0;
761
762 if (bled < 0)
763 goto invalid_out;
764
765 if (bled)
766 dev_err(&dev->pdev->dev, "adapter kernel panic'd %x.\n", bled);
767
768 /*
769 * When there is a BlinkLED, IOP_RESET has not effect
770 */
771 if (bled >= 2 && dev->sa_firmware && reset_type & HW_IOP_RESET)
772 reset_type &= ~HW_IOP_RESET;
773
774 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
775
776 dev_err(&dev->pdev->dev, "Controller reset type is %d\n", reset_type);
777
778 if (reset_type & HW_IOP_RESET) {
779 dev_info(&dev->pdev->dev, "Issuing IOP reset\n");
780 aac_send_iop_reset(dev);
781
782 /*
783 * Creates a delay or wait till up and running comes thru
784 */
785 is_ctrl_up = aac_is_ctrl_up_and_running(dev);
786 if (!is_ctrl_up)
787 dev_err(&dev->pdev->dev, "IOP reset failed\n");
788 else {
789 dev_info(&dev->pdev->dev, "IOP reset succeded\n");
790 goto set_startup;
791 }
792 }
793
794 if (!dev->sa_firmware) {
795 dev_err(&dev->pdev->dev, "ARC Reset attempt failed\n");
796 ret = -ENODEV;
797 goto out;
798 }
799
800 if (reset_type & HW_SOFT_RESET) {
801 dev_info(&dev->pdev->dev, "Issuing SOFT reset\n");
802 aac_send_hardware_soft_reset(dev);
803 dev->msi_enabled = 0;
804
805 is_ctrl_up = aac_is_ctrl_up_and_running(dev);
806 if (!is_ctrl_up) {
807 dev_err(&dev->pdev->dev, "SOFT reset failed\n");
808 ret = -ENODEV;
809 goto out;
810 } else
811 dev_info(&dev->pdev->dev, "SOFT reset succeded\n");
812 }
813
814 set_startup:
815 if (startup_timeout < 300)
816 startup_timeout = 300;
817
818 out:
819 return ret;
820
821 invalid_out:
822 if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC)
823 ret = -ENODEV;
824 goto out;
825 }
826
827 /**
828 * aac_src_select_comm - Select communications method
829 * @dev: Adapter
830 * @comm: communications method
831 */
832 static int aac_src_select_comm(struct aac_dev *dev, int comm)
833 {
834 switch (comm) {
835 case AAC_COMM_MESSAGE:
836 dev->a_ops.adapter_intr = aac_src_intr_message;
837 dev->a_ops.adapter_deliver = aac_src_deliver_message;
838 break;
839 default:
840 return 1;
841 }
842 return 0;
843 }
844
845 /**
846 * aac_src_init - initialize an Cardinal Frey Bar card
847 * @dev: device to configure
848 *
849 */
850
851 int aac_src_init(struct aac_dev *dev)
852 {
853 unsigned long start;
854 unsigned long status;
855 int restart = 0;
856 int instance = dev->id;
857 const char *name = dev->name;
858
859 dev->a_ops.adapter_ioremap = aac_src_ioremap;
860 dev->a_ops.adapter_comm = aac_src_select_comm;
861
862 dev->base_size = AAC_MIN_SRC_BAR0_SIZE;
863 if (aac_adapter_ioremap(dev, dev->base_size)) {
864 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
865 goto error_iounmap;
866 }
867
868 /* Failure to reset here is an option ... */
869 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
870 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
871
872 if (dev->init_reset) {
873 dev->init_reset = false;
874 if (!aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET))
875 ++restart;
876 }
877
878 /*
879 * Check to see if the board panic'd while booting.
880 */
881 status = src_readl(dev, MUnit.OMR);
882 if (status & KERNEL_PANIC) {
883 if (aac_src_restart_adapter(dev,
884 aac_src_check_health(dev), IOP_HWSOFT_RESET))
885 goto error_iounmap;
886 ++restart;
887 }
888 /*
889 * Check to see if the board failed any self tests.
890 */
891 status = src_readl(dev, MUnit.OMR);
892 if (status & SELF_TEST_FAILED) {
893 printk(KERN_ERR "%s%d: adapter self-test failed.\n",
894 dev->name, instance);
895 goto error_iounmap;
896 }
897 /*
898 * Check to see if the monitor panic'd while booting.
899 */
900 if (status & MONITOR_PANIC) {
901 printk(KERN_ERR "%s%d: adapter monitor panic.\n",
902 dev->name, instance);
903 goto error_iounmap;
904 }
905 start = jiffies;
906 /*
907 * Wait for the adapter to be up and running. Wait up to 3 minutes
908 */
909 while (!((status = src_readl(dev, MUnit.OMR)) &
910 KERNEL_UP_AND_RUNNING)) {
911 if ((restart &&
912 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
913 time_after(jiffies, start+HZ*startup_timeout)) {
914 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
915 dev->name, instance, status);
916 goto error_iounmap;
917 }
918 if (!restart &&
919 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
920 time_after(jiffies, start + HZ *
921 ((startup_timeout > 60)
922 ? (startup_timeout - 60)
923 : (startup_timeout / 2))))) {
924 if (likely(!aac_src_restart_adapter(dev,
925 aac_src_check_health(dev), IOP_HWSOFT_RESET)))
926 start = jiffies;
927 ++restart;
928 }
929 msleep(1);
930 }
931 if (restart && aac_commit)
932 aac_commit = 1;
933 /*
934 * Fill in the common function dispatch table.
935 */
936 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
937 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
938 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
939 dev->a_ops.adapter_notify = aac_src_notify_adapter;
940 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
941 dev->a_ops.adapter_check_health = aac_src_check_health;
942 dev->a_ops.adapter_restart = aac_src_restart_adapter;
943 dev->a_ops.adapter_start = aac_src_start_adapter;
944
945 /*
946 * First clear out all interrupts. Then enable the one's that we
947 * can handle.
948 */
949 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
950 aac_adapter_disable_int(dev);
951 src_writel(dev, MUnit.ODR_C, 0xffffffff);
952 aac_adapter_enable_int(dev);
953
954 if (aac_init_adapter(dev) == NULL)
955 goto error_iounmap;
956 if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1)
957 goto error_iounmap;
958
959 dev->msi = !pci_enable_msi(dev->pdev);
960
961 dev->aac_msix[0].vector_no = 0;
962 dev->aac_msix[0].dev = dev;
963
964 if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr,
965 IRQF_SHARED, "aacraid", &(dev->aac_msix[0])) < 0) {
966
967 if (dev->msi)
968 pci_disable_msi(dev->pdev);
969
970 printk(KERN_ERR "%s%d: Interrupt unavailable.\n",
971 name, instance);
972 goto error_iounmap;
973 }
974 dev->dbg_base = pci_resource_start(dev->pdev, 2);
975 dev->dbg_base_mapped = dev->regs.src.bar1;
976 dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE;
977 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
978
979 aac_adapter_enable_int(dev);
980
981 if (!dev->sync_mode) {
982 /*
983 * Tell the adapter that all is configured, and it can
984 * start accepting requests
985 */
986 aac_src_start_adapter(dev);
987 }
988 return 0;
989
990 error_iounmap:
991
992 return -1;
993 }
994
995 /**
996 * aac_srcv_init - initialize an SRCv card
997 * @dev: device to configure
998 *
999 */
1000
1001 int aac_srcv_init(struct aac_dev *dev)
1002 {
1003 unsigned long start;
1004 unsigned long status;
1005 int restart = 0;
1006 int instance = dev->id;
1007 const char *name = dev->name;
1008
1009 dev->a_ops.adapter_ioremap = aac_srcv_ioremap;
1010 dev->a_ops.adapter_comm = aac_src_select_comm;
1011
1012 dev->base_size = AAC_MIN_SRCV_BAR0_SIZE;
1013 if (aac_adapter_ioremap(dev, dev->base_size)) {
1014 printk(KERN_WARNING "%s: unable to map adapter.\n", name);
1015 goto error_iounmap;
1016 }
1017
1018 /* Failure to reset here is an option ... */
1019 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
1020 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
1021
1022 if (dev->init_reset) {
1023 dev->init_reset = false;
1024 if (!aac_src_restart_adapter(dev, 0, IOP_HWSOFT_RESET))
1025 ++restart;
1026 }
1027
1028 /*
1029 * Check to see if flash update is running.
1030 * Wait for the adapter to be up and running. Wait up to 5 minutes
1031 */
1032 status = src_readl(dev, MUnit.OMR);
1033 if (status & FLASH_UPD_PENDING) {
1034 start = jiffies;
1035 do {
1036 status = src_readl(dev, MUnit.OMR);
1037 if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) {
1038 printk(KERN_ERR "%s%d: adapter flash update failed.\n",
1039 dev->name, instance);
1040 goto error_iounmap;
1041 }
1042 } while (!(status & FLASH_UPD_SUCCESS) &&
1043 !(status & FLASH_UPD_FAILED));
1044 /* Delay 10 seconds.
1045 * Because right now FW is doing a soft reset,
1046 * do not read scratch pad register at this time
1047 */
1048 ssleep(10);
1049 }
1050 /*
1051 * Check to see if the board panic'd while booting.
1052 */
1053 status = src_readl(dev, MUnit.OMR);
1054 if (status & KERNEL_PANIC) {
1055 if (aac_src_restart_adapter(dev,
1056 aac_src_check_health(dev), IOP_HWSOFT_RESET))
1057 goto error_iounmap;
1058 ++restart;
1059 }
1060 /*
1061 * Check to see if the board failed any self tests.
1062 */
1063 status = src_readl(dev, MUnit.OMR);
1064 if (status & SELF_TEST_FAILED) {
1065 printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance);
1066 goto error_iounmap;
1067 }
1068 /*
1069 * Check to see if the monitor panic'd while booting.
1070 */
1071 if (status & MONITOR_PANIC) {
1072 printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance);
1073 goto error_iounmap;
1074 }
1075 start = jiffies;
1076 /*
1077 * Wait for the adapter to be up and running. Wait up to 3 minutes
1078 */
1079 while (!((status = src_readl(dev, MUnit.OMR)) &
1080 KERNEL_UP_AND_RUNNING) ||
1081 status == 0xffffffff) {
1082 if ((restart &&
1083 (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) ||
1084 time_after(jiffies, start+HZ*startup_timeout)) {
1085 printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n",
1086 dev->name, instance, status);
1087 goto error_iounmap;
1088 }
1089 if (!restart &&
1090 ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) ||
1091 time_after(jiffies, start + HZ *
1092 ((startup_timeout > 60)
1093 ? (startup_timeout - 60)
1094 : (startup_timeout / 2))))) {
1095 if (likely(!aac_src_restart_adapter(dev,
1096 aac_src_check_health(dev), IOP_HWSOFT_RESET)))
1097 start = jiffies;
1098 ++restart;
1099 }
1100 msleep(1);
1101 }
1102 if (restart && aac_commit)
1103 aac_commit = 1;
1104 /*
1105 * Fill in the common function dispatch table.
1106 */
1107 dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter;
1108 dev->a_ops.adapter_disable_int = aac_src_disable_interrupt;
1109 dev->a_ops.adapter_enable_int = aac_src_disable_interrupt;
1110 dev->a_ops.adapter_notify = aac_src_notify_adapter;
1111 dev->a_ops.adapter_sync_cmd = src_sync_cmd;
1112 dev->a_ops.adapter_check_health = aac_src_check_health;
1113 dev->a_ops.adapter_restart = aac_src_restart_adapter;
1114 dev->a_ops.adapter_start = aac_src_start_adapter;
1115
1116 /*
1117 * First clear out all interrupts. Then enable the one's that we
1118 * can handle.
1119 */
1120 aac_adapter_comm(dev, AAC_COMM_MESSAGE);
1121 aac_adapter_disable_int(dev);
1122 src_writel(dev, MUnit.ODR_C, 0xffffffff);
1123 aac_adapter_enable_int(dev);
1124
1125 if (aac_init_adapter(dev) == NULL)
1126 goto error_iounmap;
1127 if ((dev->comm_interface != AAC_COMM_MESSAGE_TYPE2) &&
1128 (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3))
1129 goto error_iounmap;
1130 if (dev->msi_enabled)
1131 aac_src_access_devreg(dev, AAC_ENABLE_MSIX);
1132
1133 if (aac_acquire_irq(dev))
1134 goto error_iounmap;
1135
1136 dev->dbg_base = pci_resource_start(dev->pdev, 2);
1137 dev->dbg_base_mapped = dev->regs.src.bar1;
1138 dev->dbg_size = AAC_MIN_SRCV_BAR1_SIZE;
1139 dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message;
1140
1141 aac_adapter_enable_int(dev);
1142
1143 if (!dev->sync_mode) {
1144 /*
1145 * Tell the adapter that all is configured, and it can
1146 * start accepting requests
1147 */
1148 aac_src_start_adapter(dev);
1149 }
1150 return 0;
1151
1152 error_iounmap:
1153
1154 return -1;
1155 }
1156
1157 void aac_src_access_devreg(struct aac_dev *dev, int mode)
1158 {
1159 u_int32_t val;
1160
1161 switch (mode) {
1162 case AAC_ENABLE_INTERRUPT:
1163 src_writel(dev,
1164 MUnit.OIMR,
1165 dev->OIMR = (dev->msi_enabled ?
1166 AAC_INT_ENABLE_TYPE1_MSIX :
1167 AAC_INT_ENABLE_TYPE1_INTX));
1168 break;
1169
1170 case AAC_DISABLE_INTERRUPT:
1171 src_writel(dev,
1172 MUnit.OIMR,
1173 dev->OIMR = AAC_INT_DISABLE_ALL);
1174 break;
1175
1176 case AAC_ENABLE_MSIX:
1177 /* set bit 6 */
1178 val = src_readl(dev, MUnit.IDR);
1179 val |= 0x40;
1180 src_writel(dev, MUnit.IDR, val);
1181 src_readl(dev, MUnit.IDR);
1182 /* unmask int. */
1183 val = PMC_ALL_INTERRUPT_BITS;
1184 src_writel(dev, MUnit.IOAR, val);
1185 val = src_readl(dev, MUnit.OIMR);
1186 src_writel(dev,
1187 MUnit.OIMR,
1188 val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0)));
1189 break;
1190
1191 case AAC_DISABLE_MSIX:
1192 /* reset bit 6 */
1193 val = src_readl(dev, MUnit.IDR);
1194 val &= ~0x40;
1195 src_writel(dev, MUnit.IDR, val);
1196 src_readl(dev, MUnit.IDR);
1197 break;
1198
1199 case AAC_CLEAR_AIF_BIT:
1200 /* set bit 5 */
1201 val = src_readl(dev, MUnit.IDR);
1202 val |= 0x20;
1203 src_writel(dev, MUnit.IDR, val);
1204 src_readl(dev, MUnit.IDR);
1205 break;
1206
1207 case AAC_CLEAR_SYNC_BIT:
1208 /* set bit 4 */
1209 val = src_readl(dev, MUnit.IDR);
1210 val |= 0x10;
1211 src_writel(dev, MUnit.IDR, val);
1212 src_readl(dev, MUnit.IDR);
1213 break;
1214
1215 case AAC_ENABLE_INTX:
1216 /* set bit 7 */
1217 val = src_readl(dev, MUnit.IDR);
1218 val |= 0x80;
1219 src_writel(dev, MUnit.IDR, val);
1220 src_readl(dev, MUnit.IDR);
1221 /* unmask int. */
1222 val = PMC_ALL_INTERRUPT_BITS;
1223 src_writel(dev, MUnit.IOAR, val);
1224 src_readl(dev, MUnit.IOAR);
1225 val = src_readl(dev, MUnit.OIMR);
1226 src_writel(dev, MUnit.OIMR,
1227 val & (~(PMC_GLOBAL_INT_BIT2)));
1228 break;
1229
1230 default:
1231 break;
1232 }
1233 }
1234
1235 static int aac_src_get_sync_status(struct aac_dev *dev)
1236 {
1237
1238 int val;
1239
1240 if (dev->msi_enabled)
1241 val = src_readl(dev, MUnit.ODR_MSI) & 0x1000 ? 1 : 0;
1242 else
1243 val = src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT;
1244
1245 return val;
1246 }
CRIS linux kernel tree