2 * Copyright (C) 2017 Spreadtrum Communications Inc.
4 * SPDX-License-Identifier: GPL-2.0
7 #include <linux/hwspinlock.h>
8 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/platform_device.h>
15 #include <linux/spi/spi.h>
16 #include <linux/sizes.h>
18 /* Registers definitions for ADI controller */
19 #define REG_ADI_CTRL0 0x4
20 #define REG_ADI_CHN_PRIL 0x8
21 #define REG_ADI_CHN_PRIH 0xc
22 #define REG_ADI_INT_EN 0x10
23 #define REG_ADI_INT_RAW 0x14
24 #define REG_ADI_INT_MASK 0x18
25 #define REG_ADI_INT_CLR 0x1c
26 #define REG_ADI_GSSI_CFG0 0x20
27 #define REG_ADI_GSSI_CFG1 0x24
28 #define REG_ADI_RD_CMD 0x28
29 #define REG_ADI_RD_DATA 0x2c
30 #define REG_ADI_ARM_FIFO_STS 0x30
31 #define REG_ADI_STS 0x34
32 #define REG_ADI_EVT_FIFO_STS 0x38
33 #define REG_ADI_ARM_CMD_STS 0x3c
34 #define REG_ADI_CHN_EN 0x40
35 #define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
36 #define REG_ADI_CHN_EN1 0x20c
38 /* Bits definitions for register REG_ADI_GSSI_CFG0 */
39 #define BIT_CLK_ALL_ON BIT(30)
41 /* Bits definitions for register REG_ADI_RD_DATA */
42 #define BIT_RD_CMD_BUSY BIT(31)
43 #define RD_ADDR_SHIFT 16
44 #define RD_VALUE_MASK GENMASK(15, 0)
45 #define RD_ADDR_MASK GENMASK(30, 16)
47 /* Bits definitions for register REG_ADI_ARM_FIFO_STS */
48 #define BIT_FIFO_FULL BIT(11)
49 #define BIT_FIFO_EMPTY BIT(10)
52 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
53 * The slave devices address offset is always 0x8000 and size is 4K.
55 #define ADI_SLAVE_ADDR_SIZE SZ_4K
56 #define ADI_SLAVE_OFFSET 0x8000
58 /* Timeout (ms) for the trylock of hardware spinlocks */
59 #define ADI_HWSPINLOCK_TIMEOUT 5000
61 * ADI controller has 50 channels including 2 software channels
62 * and 48 hardware channels.
64 #define ADI_HW_CHNS 50
66 #define ADI_FIFO_DRAIN_TIMEOUT 1000
67 #define ADI_READ_TIMEOUT 2000
68 #define REG_ADDR_LOW_MASK GENMASK(11, 0)
71 struct spi_controller
*ctlr
;
74 struct hwspinlock
*hwlock
;
75 unsigned long slave_vbase
;
76 unsigned long slave_pbase
;
79 static int sprd_adi_check_paddr(struct sprd_adi
*sadi
, u32 paddr
)
81 if (paddr
< sadi
->slave_pbase
|| paddr
>
82 (sadi
->slave_pbase
+ ADI_SLAVE_ADDR_SIZE
)) {
84 "slave physical address is incorrect, addr = 0x%x\n",
92 static unsigned long sprd_adi_to_vaddr(struct sprd_adi
*sadi
, u32 paddr
)
94 return (paddr
- sadi
->slave_pbase
+ sadi
->slave_vbase
);
97 static int sprd_adi_drain_fifo(struct sprd_adi
*sadi
)
99 u32 timeout
= ADI_FIFO_DRAIN_TIMEOUT
;
103 sts
= readl_relaxed(sadi
->base
+ REG_ADI_ARM_FIFO_STS
);
104 if (sts
& BIT_FIFO_EMPTY
)
111 dev_err(sadi
->dev
, "drain write fifo timeout\n");
118 static int sprd_adi_fifo_is_full(struct sprd_adi
*sadi
)
120 return readl_relaxed(sadi
->base
+ REG_ADI_ARM_FIFO_STS
) & BIT_FIFO_FULL
;
123 static int sprd_adi_read(struct sprd_adi
*sadi
, u32 reg_paddr
, u32
*read_val
)
125 int read_timeout
= ADI_READ_TIMEOUT
;
129 * Set the physical register address need to read into RD_CMD register,
130 * then ADI controller will start to transfer automatically.
132 writel_relaxed(reg_paddr
, sadi
->base
+ REG_ADI_RD_CMD
);
135 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
136 * simultaneously when writing read command to register, and the
137 * BIT_RD_CMD_BUSY will be cleared after the read operation is
141 val
= readl_relaxed(sadi
->base
+ REG_ADI_RD_DATA
);
142 if (!(val
& BIT_RD_CMD_BUSY
))
146 } while (--read_timeout
);
148 if (read_timeout
== 0) {
149 dev_err(sadi
->dev
, "ADI read timeout\n");
154 * The return value includes data and read register address, from bit 0
155 * to bit 15 are data, and from bit 16 to bit 30 are read register
156 * address. Then we can check the returned register address to validate
159 rd_addr
= (val
& RD_ADDR_MASK
) >> RD_ADDR_SHIFT
;
161 if (rd_addr
!= (reg_paddr
& REG_ADDR_LOW_MASK
)) {
162 dev_err(sadi
->dev
, "read error, reg addr = 0x%x, val = 0x%x\n",
167 *read_val
= val
& RD_VALUE_MASK
;
171 static int sprd_adi_write(struct sprd_adi
*sadi
, unsigned long reg
, u32 val
)
173 u32 timeout
= ADI_FIFO_DRAIN_TIMEOUT
;
176 ret
= sprd_adi_drain_fifo(sadi
);
181 * we should wait for write fifo is empty before writing data to PMIC
185 if (!sprd_adi_fifo_is_full(sadi
)) {
186 writel_relaxed(val
, (void __iomem
*)reg
);
194 dev_err(sadi
->dev
, "write fifo is full\n");
201 static int sprd_adi_transfer_one(struct spi_controller
*ctlr
,
202 struct spi_device
*spi_dev
,
203 struct spi_transfer
*t
)
205 struct sprd_adi
*sadi
= spi_controller_get_devdata(ctlr
);
206 unsigned long flags
, virt_reg
;
211 phy_reg
= *(u32
*)t
->rx_buf
+ sadi
->slave_pbase
;
213 ret
= sprd_adi_check_paddr(sadi
, phy_reg
);
217 ret
= hwspin_lock_timeout_irqsave(sadi
->hwlock
,
218 ADI_HWSPINLOCK_TIMEOUT
,
221 dev_err(sadi
->dev
, "get the hw lock failed\n");
225 ret
= sprd_adi_read(sadi
, phy_reg
, &val
);
226 hwspin_unlock_irqrestore(sadi
->hwlock
, &flags
);
230 *(u32
*)t
->rx_buf
= val
;
231 } else if (t
->tx_buf
) {
232 u32
*p
= (u32
*)t
->tx_buf
;
235 * Get the physical register address need to write and convert
236 * the physical address to virtual address. Since we need
237 * virtual register address to write.
239 phy_reg
= *p
++ + sadi
->slave_pbase
;
240 ret
= sprd_adi_check_paddr(sadi
, phy_reg
);
244 virt_reg
= sprd_adi_to_vaddr(sadi
, phy_reg
);
247 ret
= hwspin_lock_timeout_irqsave(sadi
->hwlock
,
248 ADI_HWSPINLOCK_TIMEOUT
,
251 dev_err(sadi
->dev
, "get the hw lock failed\n");
255 ret
= sprd_adi_write(sadi
, virt_reg
, val
);
256 hwspin_unlock_irqrestore(sadi
->hwlock
, &flags
);
260 dev_err(sadi
->dev
, "no buffer for transfer\n");
267 static void sprd_adi_hw_init(struct sprd_adi
*sadi
)
269 struct device_node
*np
= sadi
->dev
->of_node
;
270 int i
, size
, chn_cnt
;
274 /* Address bits select default 12 bits */
275 writel_relaxed(0, sadi
->base
+ REG_ADI_CTRL0
);
277 /* Set all channels as default priority */
278 writel_relaxed(0, sadi
->base
+ REG_ADI_CHN_PRIL
);
279 writel_relaxed(0, sadi
->base
+ REG_ADI_CHN_PRIH
);
281 /* Set clock auto gate mode */
282 tmp
= readl_relaxed(sadi
->base
+ REG_ADI_GSSI_CFG0
);
283 tmp
&= ~BIT_CLK_ALL_ON
;
284 writel_relaxed(tmp
, sadi
->base
+ REG_ADI_GSSI_CFG0
);
286 /* Set hardware channels setting */
287 list
= of_get_property(np
, "sprd,hw-channels", &size
);
288 if (!list
|| !size
) {
289 dev_info(sadi
->dev
, "no hw channels setting in node\n");
294 for (i
= 0; i
< chn_cnt
; i
++) {
296 u32 chn_id
= be32_to_cpu(*list
++);
297 u32 chn_config
= be32_to_cpu(*list
++);
299 /* Channel 0 and 1 are software channels */
303 writel_relaxed(chn_config
, sadi
->base
+
304 REG_ADI_CHN_ADDR(chn_id
));
307 value
= readl_relaxed(sadi
->base
+ REG_ADI_CHN_EN
);
308 value
|= BIT(chn_id
);
309 writel_relaxed(value
, sadi
->base
+ REG_ADI_CHN_EN
);
310 } else if (chn_id
< ADI_HW_CHNS
) {
311 value
= readl_relaxed(sadi
->base
+ REG_ADI_CHN_EN1
);
312 value
|= BIT(chn_id
- 32);
313 writel_relaxed(value
, sadi
->base
+ REG_ADI_CHN_EN1
);
318 static int sprd_adi_probe(struct platform_device
*pdev
)
320 struct device_node
*np
= pdev
->dev
.of_node
;
321 struct spi_controller
*ctlr
;
322 struct sprd_adi
*sadi
;
323 struct resource
*res
;
328 dev_err(&pdev
->dev
, "can not find the adi bus node\n");
332 pdev
->id
= of_alias_get_id(np
, "spi");
333 num_chipselect
= of_get_child_count(np
);
335 ctlr
= spi_alloc_master(&pdev
->dev
, sizeof(struct sprd_adi
));
339 dev_set_drvdata(&pdev
->dev
, ctlr
);
340 sadi
= spi_controller_get_devdata(ctlr
);
342 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
343 sadi
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
344 if (IS_ERR(sadi
->base
)) {
345 ret
= PTR_ERR(sadi
->base
);
349 sadi
->slave_vbase
= (unsigned long)sadi
->base
+ ADI_SLAVE_OFFSET
;
350 sadi
->slave_pbase
= res
->start
+ ADI_SLAVE_OFFSET
;
352 sadi
->dev
= &pdev
->dev
;
353 ret
= of_hwspin_lock_get_id(np
, 0);
355 dev_err(&pdev
->dev
, "can not get the hardware spinlock\n");
359 sadi
->hwlock
= hwspin_lock_request_specific(ret
);
365 sprd_adi_hw_init(sadi
);
367 ctlr
->dev
.of_node
= pdev
->dev
.of_node
;
368 ctlr
->bus_num
= pdev
->id
;
369 ctlr
->num_chipselect
= num_chipselect
;
370 ctlr
->flags
= SPI_MASTER_HALF_DUPLEX
;
371 ctlr
->bits_per_word_mask
= 0;
372 ctlr
->transfer_one
= sprd_adi_transfer_one
;
374 ret
= devm_spi_register_controller(&pdev
->dev
, ctlr
);
376 dev_err(&pdev
->dev
, "failed to register SPI controller\n");
383 hwspin_lock_free(sadi
->hwlock
);
385 spi_controller_put(ctlr
);
389 static int sprd_adi_remove(struct platform_device
*pdev
)
391 struct spi_controller
*ctlr
= dev_get_drvdata(&pdev
->dev
);
392 struct sprd_adi
*sadi
= spi_controller_get_devdata(ctlr
);
394 hwspin_lock_free(sadi
->hwlock
);
398 static const struct of_device_id sprd_adi_of_match
[] = {
400 .compatible
= "sprd,sc9860-adi",
404 MODULE_DEVICE_TABLE(of
, sprd_adi_of_match
);
406 static struct platform_driver sprd_adi_driver
= {
409 .of_match_table
= sprd_adi_of_match
,
411 .probe
= sprd_adi_probe
,
412 .remove
= sprd_adi_remove
,
414 module_platform_driver(sprd_adi_driver
);
416 MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
417 MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
418 MODULE_LICENSE("GPL v2");