drivers/thermal/mtk_thermal.c

   1 /*
   2  * Copyright (c) 2015 MediaTek Inc.
   3  * Author: Hanyi Wu <hanyi.wu@mediatek.com>
   4  *         Sascha Hauer <s.hauer@pengutronix.de>
   5  *         Dawei Chien <dawei.chien@mediatek.com>
   6  *         Louis Yu <louis.yu@mediatek.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/nvmem-consumer.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_device.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/thermal.h>
  31 #include <linux/reset.h>
  32 #include <linux/types.h>
  33
  34 /* AUXADC Registers */
  35 #define AUXADC_CON1_SET_V       0x008
  36 #define AUXADC_CON1_CLR_V       0x00c
  37 #define AUXADC_CON2_V           0x010
  38 #define AUXADC_DATA(channel)    (0x14 + (channel) * 4)
  39
  40 #define APMIXED_SYS_TS_CON1     0x604
  41
  42 /* Thermal Controller Registers */
  43 #define TEMP_MONCTL0            0x000
  44 #define TEMP_MONCTL1            0x004
  45 #define TEMP_MONCTL2            0x008
  46 #define TEMP_MONIDET0           0x014
  47 #define TEMP_MONIDET1           0x018
  48 #define TEMP_MSRCTL0            0x038
  49 #define TEMP_AHBPOLL            0x040
  50 #define TEMP_AHBTO              0x044
  51 #define TEMP_ADCPNP0            0x048
  52 #define TEMP_ADCPNP1            0x04c
  53 #define TEMP_ADCPNP2            0x050
  54 #define TEMP_ADCPNP3            0x0b4
  55
  56 #define TEMP_ADCMUX             0x054
  57 #define TEMP_ADCEN              0x060
  58 #define TEMP_PNPMUXADDR         0x064
  59 #define TEMP_ADCMUXADDR         0x068
  60 #define TEMP_ADCENADDR          0x074
  61 #define TEMP_ADCVALIDADDR       0x078
  62 #define TEMP_ADCVOLTADDR        0x07c
  63 #define TEMP_RDCTRL             0x080
  64 #define TEMP_ADCVALIDMASK       0x084
  65 #define TEMP_ADCVOLTAGESHIFT    0x088
  66 #define TEMP_ADCWRITECTRL       0x08c
  67 #define TEMP_MSR0               0x090
  68 #define TEMP_MSR1               0x094
  69 #define TEMP_MSR2               0x098
  70 #define TEMP_MSR3               0x0B8
  71
  72 #define TEMP_SPARE0             0x0f0
  73
  74 #define PTPCORESEL              0x400
  75
  76 #define TEMP_MONCTL1_PERIOD_UNIT(x)     ((x) & 0x3ff)
  77
  78 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
  79 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
  80
  81 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)       (x)
  82
  83 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE         BIT(0)
  84 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE         BIT(1)
  85
  86 #define TEMP_ADCVALIDMASK_VALID_HIGH            BIT(5)
  87 #define TEMP_ADCVALIDMASK_VALID_POS(bit)        (bit)
  88
  89 /* MT8173 thermal sensors */
  90 #define MT8173_TS1      0
  91 #define MT8173_TS2      1
  92 #define MT8173_TS3      2
  93 #define MT8173_TS4      3
  94 #define MT8173_TSABB    4
  95
  96 /* AUXADC channel 11 is used for the temperature sensors */
  97 #define MT8173_TEMP_AUXADC_CHANNEL      11
  98
  99 /* The total number of temperature sensors in the MT8173 */
 100 #define MT8173_NUM_SENSORS              5
 101
 102 /* The number of banks in the MT8173 */
 103 #define MT8173_NUM_ZONES                4
 104
 105 /* The number of sensing points per bank */
 106 #define MT8173_NUM_SENSORS_PER_ZONE     4
 107
 108 /*
 109  * Layout of the fuses providing the calibration data
 110  * These macros could be used for MT8173, MT2701, and MT2712.
 111  * MT8173 has 5 sensors and needs 5 VTS calibration data.
 112  * MT2701 has 3 sensors and needs 3 VTS calibration data.
 113  * MT2712 has 4 sensors and needs 4 VTS calibration data.
 114  */
 115 #define MT8173_CALIB_BUF0_VALID         BIT(0)
 116 #define MT8173_CALIB_BUF1_ADC_GE(x)     (((x) >> 22) & 0x3ff)
 117 #define MT8173_CALIB_BUF0_VTS_TS1(x)    (((x) >> 17) & 0x1ff)
 118 #define MT8173_CALIB_BUF0_VTS_TS2(x)    (((x) >> 8) & 0x1ff)
 119 #define MT8173_CALIB_BUF1_VTS_TS3(x)    (((x) >> 0) & 0x1ff)
 120 #define MT8173_CALIB_BUF2_VTS_TS4(x)    (((x) >> 23) & 0x1ff)
 121 #define MT8173_CALIB_BUF2_VTS_TSABB(x)  (((x) >> 14) & 0x1ff)
 122 #define MT8173_CALIB_BUF0_DEGC_CALI(x)  (((x) >> 1) & 0x3f)
 123 #define MT8173_CALIB_BUF0_O_SLOPE(x)    (((x) >> 26) & 0x3f)
 124 #define MT8173_CALIB_BUF0_O_SLOPE_SIGN(x)       (((x) >> 7) & 0x1)
 125 #define MT8173_CALIB_BUF1_ID(x) (((x) >> 9) & 0x1)
 126
 127 /* MT2701 thermal sensors */
 128 #define MT2701_TS1      0
 129 #define MT2701_TS2      1
 130 #define MT2701_TSABB    2
 131
 132 /* AUXADC channel 11 is used for the temperature sensors */
 133 #define MT2701_TEMP_AUXADC_CHANNEL      11
 134
 135 /* The total number of temperature sensors in the MT2701 */
 136 #define MT2701_NUM_SENSORS      3
 137
 138 /* The number of sensing points per bank */
 139 #define MT2701_NUM_SENSORS_PER_ZONE     3
 140
 141 /* MT2712 thermal sensors */
 142 #define MT2712_TS1      0
 143 #define MT2712_TS2      1
 144 #define MT2712_TS3      2
 145 #define MT2712_TS4      3
 146
 147 /* AUXADC channel 11 is used for the temperature sensors */
 148 #define MT2712_TEMP_AUXADC_CHANNEL      11
 149
 150 /* The total number of temperature sensors in the MT2712 */
 151 #define MT2712_NUM_SENSORS      4
 152
 153 /* The number of sensing points per bank */
 154 #define MT2712_NUM_SENSORS_PER_ZONE     4
 155
 156 struct mtk_thermal;
 157
 158 struct thermal_bank_cfg {
 159         unsigned int num_sensors;
 160         const int *sensors;
 161 };
 162
 163 struct mtk_thermal_bank {
 164         struct mtk_thermal *mt;
 165         int id;
 166 };
 167
 168 struct mtk_thermal_data {
 169         s32 num_banks;
 170         s32 num_sensors;
 171         s32 auxadc_channel;
 172         const int *sensor_mux_values;
 173         const int *msr;
 174         const int *adcpnp;
 175         struct thermal_bank_cfg bank_data[];
 176 };
 177
 178 struct mtk_thermal {
 179         struct device *dev;
 180         void __iomem *thermal_base;
 181
 182         struct clk *clk_peri_therm;
 183         struct clk *clk_auxadc;
 184         /* lock: for getting and putting banks */
 185         struct mutex lock;
 186
 187         /* Calibration values */
 188         s32 adc_ge;
 189         s32 degc_cali;
 190         s32 o_slope;
 191         s32 vts[MT8173_NUM_SENSORS];
 192
 193         const struct mtk_thermal_data *conf;
 194         struct mtk_thermal_bank banks[];
 195 };
 196
 197 /* MT8173 thermal sensor data */
 198 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
 199         { MT8173_TS2, MT8173_TS3 },
 200         { MT8173_TS2, MT8173_TS4 },
 201         { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
 202         { MT8173_TS2 },
 203 };
 204
 205 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
 206         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
 207 };
 208
 209 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
 210         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
 211 };
 212
 213 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
 214
 215 /* MT2701 thermal sensor data */
 216 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
 217         MT2701_TS1, MT2701_TS2, MT2701_TSABB
 218 };
 219
 220 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
 221         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
 222 };
 223
 224 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
 225         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
 226 };
 227
 228 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
 229
 230 /* MT2712 thermal sensor data */
 231 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
 232         MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
 233 };
 234
 235 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
 236         TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
 237 };
 238
 239 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
 240         TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
 241 };
 242
 243 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
 244
 245 /**
 246  * The MT8173 thermal controller has four banks. Each bank can read up to
 247  * four temperature sensors simultaneously. The MT8173 has a total of 5
 248  * temperature sensors. We use each bank to measure a certain area of the
 249  * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
 250  * areas, hence is used in different banks.
 251  *
 252  * The thermal core only gets the maximum temperature of all banks, so
 253  * the bank concept wouldn't be necessary here. However, the SVS (Smart
 254  * Voltage Scaling) unit makes its decisions based on the same bank
 255  * data, and this indeed needs the temperatures of the individual banks
 256  * for making better decisions.
 257  */
 258 static const struct mtk_thermal_data mt8173_thermal_data = {
 259         .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
 260         .num_banks = MT8173_NUM_ZONES,
 261         .num_sensors = MT8173_NUM_SENSORS,
 262         .bank_data = {
 263                 {
 264                         .num_sensors = 2,
 265                         .sensors = mt8173_bank_data[0],
 266                 }, {
 267                         .num_sensors = 2,
 268                         .sensors = mt8173_bank_data[1],
 269                 }, {
 270                         .num_sensors = 3,
 271                         .sensors = mt8173_bank_data[2],
 272                 }, {
 273                         .num_sensors = 1,
 274                         .sensors = mt8173_bank_data[3],
 275                 },
 276         },
 277         .msr = mt8173_msr,
 278         .adcpnp = mt8173_adcpnp,
 279         .sensor_mux_values = mt8173_mux_values,
 280 };
 281
 282 /**
 283  * The MT2701 thermal controller has one bank, which can read up to
 284  * three temperature sensors simultaneously. The MT2701 has a total of 3
 285  * temperature sensors.
 286  *
 287  * The thermal core only gets the maximum temperature of this one bank,
 288  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
 289  * Voltage Scaling) unit makes its decisions based on the same bank
 290  * data.
 291  */
 292 static const struct mtk_thermal_data mt2701_thermal_data = {
 293         .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
 294         .num_banks = 1,
 295         .num_sensors = MT2701_NUM_SENSORS,
 296         .bank_data = {
 297                 {
 298                         .num_sensors = 3,
 299                         .sensors = mt2701_bank_data,
 300                 },
 301         },
 302         .msr = mt2701_msr,
 303         .adcpnp = mt2701_adcpnp,
 304         .sensor_mux_values = mt2701_mux_values,
 305 };
 306
 307 /**
 308  * The MT2712 thermal controller has one bank, which can read up to
 309  * four temperature sensors simultaneously. The MT2712 has a total of 4
 310  * temperature sensors.
 311  *
 312  * The thermal core only gets the maximum temperature of this one bank,
 313  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
 314  * Voltage Scaling) unit makes its decisions based on the same bank
 315  * data.
 316  */
 317 static const struct mtk_thermal_data mt2712_thermal_data = {
 318         .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
 319         .num_banks = 1,
 320         .num_sensors = MT2712_NUM_SENSORS,
 321         .bank_data = {
 322                 {
 323                         .num_sensors = 4,
 324                         .sensors = mt2712_bank_data,
 325                 },
 326         },
 327         .msr = mt2712_msr,
 328         .adcpnp = mt2712_adcpnp,
 329         .sensor_mux_values = mt2712_mux_values,
 330 };
 331
 332 /**
 333  * raw_to_mcelsius - convert a raw ADC value to mcelsius
 334  * @mt:         The thermal controller
 335  * @raw:        raw ADC value
 336  *
 337  * This converts the raw ADC value to mcelsius using the SoC specific
 338  * calibration constants
 339  */
 340 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
 341 {
 342         s32 tmp;
 343
 344         raw &= 0xfff;
 345
 346         tmp = 203450520 << 3;
 347         tmp /= 165 + mt->o_slope;
 348         tmp /= 10000 + mt->adc_ge;
 349         tmp *= raw - mt->vts[sensno] - 3350;
 350         tmp >>= 3;
 351
 352         return mt->degc_cali * 500 - tmp;
 353 }
 354
 355 /**
 356  * mtk_thermal_get_bank - get bank
 357  * @bank:       The bank
 358  *
 359  * The bank registers are banked, we have to select a bank in the
 360  * PTPCORESEL register to access it.
 361  */
 362 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
 363 {
 364         struct mtk_thermal *mt = bank->mt;
 365         u32 val;
 366
 367         mutex_lock(&mt->lock);
 368
 369         val = readl(mt->thermal_base + PTPCORESEL);
 370         val &= ~0xf;
 371         val |= bank->id;
 372         writel(val, mt->thermal_base + PTPCORESEL);
 373 }
 374
 375 /**
 376  * mtk_thermal_put_bank - release bank
 377  * @bank:       The bank
 378  *
 379  * release a bank previously taken with mtk_thermal_get_bank,
 380  */
 381 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
 382 {
 383         struct mtk_thermal *mt = bank->mt;
 384
 385         mutex_unlock(&mt->lock);
 386 }
 387
 388 /**
 389  * mtk_thermal_bank_temperature - get the temperature of a bank
 390  * @bank:       The bank
 391  *
 392  * The temperature of a bank is considered the maximum temperature of
 393  * the sensors associated to the bank.
 394  */
 395 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
 396 {
 397         struct mtk_thermal *mt = bank->mt;
 398         const struct mtk_thermal_data *conf = mt->conf;
 399         int i, temp = INT_MIN, max = INT_MIN;
 400         u32 raw;
 401
 402         for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
 403                 raw = readl(mt->thermal_base + conf->msr[i]);
 404
 405                 temp = raw_to_mcelsius(mt,
 406                                        conf->bank_data[bank->id].sensors[i],
 407                                        raw);
 408
 409                 /*
 410                  * The first read of a sensor often contains very high bogus
 411                  * temperature value. Filter these out so that the system does
 412                  * not immediately shut down.
 413                  */
 414                 if (temp > 200000)
 415                         temp = 0;
 416
 417                 if (temp > max)
 418                         max = temp;
 419         }
 420
 421         return max;
 422 }
 423
 424 static int mtk_read_temp(void *data, int *temperature)
 425 {
 426         struct mtk_thermal *mt = data;
 427         int i;
 428         int tempmax = INT_MIN;
 429
 430         for (i = 0; i < mt->conf->num_banks; i++) {
 431                 struct mtk_thermal_bank *bank = &mt->banks[i];
 432
 433                 mtk_thermal_get_bank(bank);
 434
 435                 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
 436
 437                 mtk_thermal_put_bank(bank);
 438         }
 439
 440         *temperature = tempmax;
 441
 442         return 0;
 443 }
 444
 445 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
 446         .get_temp = mtk_read_temp,
 447 };
 448
 449 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
 450                                   u32 apmixed_phys_base, u32 auxadc_phys_base)
 451 {
 452         struct mtk_thermal_bank *bank = &mt->banks[num];
 453         const struct mtk_thermal_data *conf = mt->conf;
 454         int i;
 455
 456         bank->id = num;
 457         bank->mt = mt;
 458
 459         mtk_thermal_get_bank(bank);
 460
 461         /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
 462         writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
 463
 464         /*
 465          * filt interval is 1 * 46.540us = 46.54us,
 466          * sen interval is 429 * 46.540us = 19.96ms
 467          */
 468         writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
 469                         TEMP_MONCTL2_SENSOR_INTERVAL(429),
 470                         mt->thermal_base + TEMP_MONCTL2);
 471
 472         /* poll is set to 10u */
 473         writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
 474                mt->thermal_base + TEMP_AHBPOLL);
 475
 476         /* temperature sampling control, 1 sample */
 477         writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
 478
 479         /* exceed this polling time, IRQ would be inserted */
 480         writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
 481
 482         /* number of interrupts per event, 1 is enough */
 483         writel(0x0, mt->thermal_base + TEMP_MONIDET0);
 484         writel(0x0, mt->thermal_base + TEMP_MONIDET1);
 485
 486         /*
 487          * The MT8173 thermal controller does not have its own ADC. Instead it
 488          * uses AHB bus accesses to control the AUXADC. To do this the thermal
 489          * controller has to be programmed with the physical addresses of the
 490          * AUXADC registers and with the various bit positions in the AUXADC.
 491          * Also the thermal controller controls a mux in the APMIXEDSYS register
 492          * space.
 493          */
 494
 495         /*
 496          * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
 497          * automatically by hw
 498          */
 499         writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX);
 500
 501         /* AHB address for auxadc mux selection */
 502         writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
 503                mt->thermal_base + TEMP_ADCMUXADDR);
 504
 505         /* AHB address for pnp sensor mux selection */
 506         writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
 507                mt->thermal_base + TEMP_PNPMUXADDR);
 508
 509         /* AHB value for auxadc enable */
 510         writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN);
 511
 512         /* AHB address for auxadc enable (channel 0 immediate mode selected) */
 513         writel(auxadc_phys_base + AUXADC_CON1_SET_V,
 514                mt->thermal_base + TEMP_ADCENADDR);
 515
 516         /* AHB address for auxadc valid bit */
 517         writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
 518                mt->thermal_base + TEMP_ADCVALIDADDR);
 519
 520         /* AHB address for auxadc voltage output */
 521         writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
 522                mt->thermal_base + TEMP_ADCVOLTADDR);
 523
 524         /* read valid & voltage are at the same register */
 525         writel(0x0, mt->thermal_base + TEMP_RDCTRL);
 526
 527         /* indicate where the valid bit is */
 528         writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
 529                mt->thermal_base + TEMP_ADCVALIDMASK);
 530
 531         /* no shift */
 532         writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
 533
 534         /* enable auxadc mux write transaction */
 535         writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 536                mt->thermal_base + TEMP_ADCWRITECTRL);
 537
 538         for (i = 0; i < conf->bank_data[num].num_sensors; i++)
 539                 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
 540                        mt->thermal_base + conf->adcpnp[i]);
 541
 542         writel((1 << conf->bank_data[num].num_sensors) - 1,
 543                mt->thermal_base + TEMP_MONCTL0);
 544
 545         writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
 546                TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
 547                mt->thermal_base + TEMP_ADCWRITECTRL);
 548
 549         mtk_thermal_put_bank(bank);
 550 }
 551
 552 static u64 of_get_phys_base(struct device_node *np)
 553 {
 554         u64 size64;
 555         const __be32 *regaddr_p;
 556
 557         regaddr_p = of_get_address(np, 0, &size64, NULL);
 558         if (!regaddr_p)
 559                 return OF_BAD_ADDR;
 560
 561         return of_translate_address(np, regaddr_p);
 562 }
 563
 564 static int mtk_thermal_get_calibration_data(struct device *dev,
 565                                             struct mtk_thermal *mt)
 566 {
 567         struct nvmem_cell *cell;
 568         u32 *buf;
 569         size_t len;
 570         int i, ret = 0;
 571
 572         /* Start with default values */
 573         mt->adc_ge = 512;
 574         for (i = 0; i < mt->conf->num_sensors; i++)
 575                 mt->vts[i] = 260;
 576         mt->degc_cali = 40;
 577         mt->o_slope = 0;
 578
 579         cell = nvmem_cell_get(dev, "calibration-data");
 580         if (IS_ERR(cell)) {
 581                 if (PTR_ERR(cell) == -EPROBE_DEFER)
 582                         return PTR_ERR(cell);
 583                 return 0;
 584         }
 585
 586         buf = (u32 *)nvmem_cell_read(cell, &len);
 587
 588         nvmem_cell_put(cell);
 589
 590         if (IS_ERR(buf))
 591                 return PTR_ERR(buf);
 592
 593         if (len < 3 * sizeof(u32)) {
 594                 dev_warn(dev, "invalid calibration data\n");
 595                 ret = -EINVAL;
 596                 goto out;
 597         }
 598
 599         if (buf[0] & MT8173_CALIB_BUF0_VALID) {
 600                 mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
 601                 mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
 602                 mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
 603                 mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
 604                 mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
 605                 mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
 606                 mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
 607                 if (MT8173_CALIB_BUF1_ID(buf[1]) &
 608                     MT8173_CALIB_BUF0_O_SLOPE_SIGN(buf[0]))
 609                         mt->o_slope = -MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
 610                 else
 611                         mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
 612         } else {
 613                 dev_info(dev, "Device not calibrated, using default calibration values\n");
 614         }
 615
 616 out:
 617         kfree(buf);
 618
 619         return ret;
 620 }
 621
 622 static const struct of_device_id mtk_thermal_of_match[] = {
 623         {
 624                 .compatible = "mediatek,mt8173-thermal",
 625                 .data = (void *)&mt8173_thermal_data,
 626         },
 627         {
 628                 .compatible = "mediatek,mt2701-thermal",
 629                 .data = (void *)&mt2701_thermal_data,
 630         },
 631         {
 632                 .compatible = "mediatek,mt2712-thermal",
 633                 .data = (void *)&mt2712_thermal_data,
 634         }, {
 635         },
 636 };
 637 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
 638
 639 static int mtk_thermal_probe(struct platform_device *pdev)
 640 {
 641         int ret, i;
 642         struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
 643         struct mtk_thermal *mt;
 644         struct resource *res;
 645         const struct of_device_id *of_id;
 646         u64 auxadc_phys_base, apmixed_phys_base;
 647         struct thermal_zone_device *tzdev;
 648
 649         mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
 650         if (!mt)
 651                 return -ENOMEM;
 652
 653         of_id = of_match_device(mtk_thermal_of_match, &pdev->dev);
 654         if (of_id)
 655                 mt->conf = (const struct mtk_thermal_data *)of_id->data;
 656
 657         mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
 658         if (IS_ERR(mt->clk_peri_therm))
 659                 return PTR_ERR(mt->clk_peri_therm);
 660
 661         mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
 662         if (IS_ERR(mt->clk_auxadc))
 663                 return PTR_ERR(mt->clk_auxadc);
 664
 665         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 666         mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
 667         if (IS_ERR(mt->thermal_base))
 668                 return PTR_ERR(mt->thermal_base);
 669
 670         ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
 671         if (ret)
 672                 return ret;
 673
 674         mutex_init(&mt->lock);
 675
 676         mt->dev = &pdev->dev;
 677
 678         auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
 679         if (!auxadc) {
 680                 dev_err(&pdev->dev, "missing auxadc node\n");
 681                 return -ENODEV;
 682         }
 683
 684         auxadc_phys_base = of_get_phys_base(auxadc);
 685
 686         of_node_put(auxadc);
 687
 688         if (auxadc_phys_base == OF_BAD_ADDR) {
 689                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 690                 return -EINVAL;
 691         }
 692
 693         apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
 694         if (!apmixedsys) {
 695                 dev_err(&pdev->dev, "missing apmixedsys node\n");
 696                 return -ENODEV;
 697         }
 698
 699         apmixed_phys_base = of_get_phys_base(apmixedsys);
 700
 701         of_node_put(apmixedsys);
 702
 703         if (apmixed_phys_base == OF_BAD_ADDR) {
 704                 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
 705                 return -EINVAL;
 706         }
 707
 708         ret = device_reset(&pdev->dev);
 709         if (ret)
 710                 return ret;
 711
 712         ret = clk_prepare_enable(mt->clk_auxadc);
 713         if (ret) {
 714                 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
 715                 return ret;
 716         }
 717
 718         ret = clk_prepare_enable(mt->clk_peri_therm);
 719         if (ret) {
 720                 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
 721                 goto err_disable_clk_auxadc;
 722         }
 723
 724         for (i = 0; i < mt->conf->num_banks; i++)
 725                 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
 726                                       auxadc_phys_base);
 727
 728         platform_set_drvdata(pdev, mt);
 729
 730         tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
 731                                                      &mtk_thermal_ops);
 732         if (IS_ERR(tzdev)) {
 733                 ret = PTR_ERR(tzdev);
 734                 goto err_disable_clk_peri_therm;
 735         }
 736
 737         return 0;
 738
 739 err_disable_clk_peri_therm:
 740         clk_disable_unprepare(mt->clk_peri_therm);
 741 err_disable_clk_auxadc:
 742         clk_disable_unprepare(mt->clk_auxadc);
 743
 744         return ret;
 745 }
 746
 747 static int mtk_thermal_remove(struct platform_device *pdev)
 748 {
 749         struct mtk_thermal *mt = platform_get_drvdata(pdev);
 750
 751         clk_disable_unprepare(mt->clk_peri_therm);
 752         clk_disable_unprepare(mt->clk_auxadc);
 753
 754         return 0;
 755 }
 756
 757 static struct platform_driver mtk_thermal_driver = {
 758         .probe = mtk_thermal_probe,
 759         .remove = mtk_thermal_remove,
 760         .driver = {
 761                 .name = "mtk-thermal",
 762                 .of_match_table = mtk_thermal_of_match,
 763         },
 764 };
 765
 766 module_platform_driver(mtk_thermal_driver);
 767
 768 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
 769 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
 770 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
 771 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
 772 MODULE_DESCRIPTION("Mediatek thermal driver");
 773 MODULE_LICENSE("GPL v2");