drivers/thermal/ti-soc-thermal/dra752-thermal-data.c

   1 /*
   2  * DRA752 thermal data.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Inc.
   5  * Contact:
   6  *      Eduardo Valentin <eduardo.valentin@ti.com>
   7  *      Tero Kristo <t-kristo@ti.com>
   8  *
   9  * This file is partially autogenerated.
  10  *
  11  * This software is licensed under the terms of the GNU General Public
  12  * License version 2, as published by the Free Software Foundation, and
  13  * may be copied, distributed, and modified under those terms.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  */
  21
  22 #include "ti-thermal.h"
  23 #include "ti-bandgap.h"
  24 #include "dra752-bandgap.h"
  25
  26 /*
  27  * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
  28  * IVA and DSPEVE need to describe the individual registers and
  29  * bit fields.
  30  */
  31
  32 /*
  33  * DRA752 CORE thermal sensor register offsets and bit-fields
  34  */
  35 static struct temp_sensor_registers
  36 dra752_core_temp_sensor_registers = {
  37         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
  38         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
  39         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
  40         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
  41         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
  42         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
  43         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
  44         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
  45         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
  46         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
  47         .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
  48         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
  49         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
  50         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
  51         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
  52         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
  53         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
  54         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
  55         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
  56         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
  57         .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
  58         .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
  59         .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
  60         .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
  61         .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
  62         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
  63 };
  64
  65 /*
  66  * DRA752 IVA thermal sensor register offsets and bit-fields
  67  */
  68 static struct temp_sensor_registers
  69 dra752_iva_temp_sensor_registers = {
  70         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
  71         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
  72         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
  73         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
  74         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
  75         .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
  76         .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
  77         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
  78         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
  79         .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
  80         .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
  81         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
  82         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
  83         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
  84         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
  85         .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
  86         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
  87         .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
  88         .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
  89         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
  90         .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
  91         .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
  92         .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
  93         .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
  94         .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
  95         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
  96 };
  97
  98 /*
  99  * DRA752 MPU thermal sensor register offsets and bit-fields
 100  */
 101 static struct temp_sensor_registers
 102 dra752_mpu_temp_sensor_registers = {
 103         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
 104         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 105         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 106         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 107         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
 108         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
 109         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
 110         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
 111         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
 112         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
 113         .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
 114         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
 115         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
 116         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 117         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 118         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
 119         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
 120         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
 121         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
 122         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
 123         .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
 124         .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
 125         .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
 126         .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
 127         .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
 128         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
 129 };
 130
 131 /*
 132  * DRA752 DSPEVE thermal sensor register offsets and bit-fields
 133  */
 134 static struct temp_sensor_registers
 135 dra752_dspeve_temp_sensor_registers = {
 136         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
 137         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 138         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 139         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 140         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
 141         .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
 142         .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
 143         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
 144         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
 145         .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
 146         .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
 147         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
 148         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
 149         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 150         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 151         .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
 152         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
 153         .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
 154         .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
 155         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
 156         .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
 157         .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
 158         .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
 159         .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
 160         .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
 161         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
 162 };
 163
 164 /*
 165  * DRA752 GPU thermal sensor register offsets and bit-fields
 166  */
 167 static struct temp_sensor_registers
 168 dra752_gpu_temp_sensor_registers = {
 169         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
 170         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 171         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 172         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 173         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
 174         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
 175         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
 176         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
 177         .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
 178         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
 179         .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
 180         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
 181         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
 182         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 183         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 184         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
 185         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
 186         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
 187         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
 188         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
 189         .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
 190         .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
 191         .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
 192         .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
 193         .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
 194         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
 195 };
 196
 197 /* Thresholds and limits for DRA752 MPU temperature sensor */
 198 static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
 199         .t_hot = DRA752_MPU_T_HOT,
 200         .t_cold = DRA752_MPU_T_COLD,
 201         .min_freq = DRA752_MPU_MIN_FREQ,
 202         .max_freq = DRA752_MPU_MAX_FREQ,
 203         .max_temp = DRA752_MPU_MAX_TEMP,
 204         .min_temp = DRA752_MPU_MIN_TEMP,
 205         .hyst_val = DRA752_MPU_HYST_VAL,
 206         .update_int1 = 1000,
 207         .update_int2 = 2000,
 208 };
 209
 210 /* Thresholds and limits for DRA752 GPU temperature sensor */
 211 static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
 212         .t_hot = DRA752_GPU_T_HOT,
 213         .t_cold = DRA752_GPU_T_COLD,
 214         .min_freq = DRA752_GPU_MIN_FREQ,
 215         .max_freq = DRA752_GPU_MAX_FREQ,
 216         .max_temp = DRA752_GPU_MAX_TEMP,
 217         .min_temp = DRA752_GPU_MIN_TEMP,
 218         .hyst_val = DRA752_GPU_HYST_VAL,
 219         .update_int1 = 1000,
 220         .update_int2 = 2000,
 221 };
 222
 223 /* Thresholds and limits for DRA752 CORE temperature sensor */
 224 static struct temp_sensor_data dra752_core_temp_sensor_data = {
 225         .t_hot = DRA752_CORE_T_HOT,
 226         .t_cold = DRA752_CORE_T_COLD,
 227         .min_freq = DRA752_CORE_MIN_FREQ,
 228         .max_freq = DRA752_CORE_MAX_FREQ,
 229         .max_temp = DRA752_CORE_MAX_TEMP,
 230         .min_temp = DRA752_CORE_MIN_TEMP,
 231         .hyst_val = DRA752_CORE_HYST_VAL,
 232         .update_int1 = 1000,
 233         .update_int2 = 2000,
 234 };
 235
 236 /* Thresholds and limits for DRA752 DSPEVE temperature sensor */
 237 static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
 238         .t_hot = DRA752_DSPEVE_T_HOT,
 239         .t_cold = DRA752_DSPEVE_T_COLD,
 240         .min_freq = DRA752_DSPEVE_MIN_FREQ,
 241         .max_freq = DRA752_DSPEVE_MAX_FREQ,
 242         .max_temp = DRA752_DSPEVE_MAX_TEMP,
 243         .min_temp = DRA752_DSPEVE_MIN_TEMP,
 244         .hyst_val = DRA752_DSPEVE_HYST_VAL,
 245         .update_int1 = 1000,
 246         .update_int2 = 2000,
 247 };
 248
 249 /* Thresholds and limits for DRA752 IVA temperature sensor */
 250 static struct temp_sensor_data dra752_iva_temp_sensor_data = {
 251         .t_hot = DRA752_IVA_T_HOT,
 252         .t_cold = DRA752_IVA_T_COLD,
 253         .min_freq = DRA752_IVA_MIN_FREQ,
 254         .max_freq = DRA752_IVA_MAX_FREQ,
 255         .max_temp = DRA752_IVA_MAX_TEMP,
 256         .min_temp = DRA752_IVA_MIN_TEMP,
 257         .hyst_val = DRA752_IVA_HYST_VAL,
 258         .update_int1 = 1000,
 259         .update_int2 = 2000,
 260 };
 261
 262 /*
 263  * DRA752 : Temperature values in milli degree celsius
 264  * ADC code values from 540 to 945
 265  */
 266 static
 267 int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
 268         /* Index 540 - 549 */
 269         -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
 270         -37800,
 271         /* Index 550 - 559 */
 272         -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
 273         -33400,
 274         /* Index 560 - 569 */
 275         -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
 276         -29400,
 277         /* Index 570 - 579 */
 278         -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
 279         -25000,
 280         /* Index 580 - 589 */
 281         -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
 282         -21000,
 283         /* Index 590 - 599 */
 284         -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
 285         -16600,
 286         /* Index 600 - 609 */
 287         -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
 288         -12500,
 289         /* Index 610 - 619 */
 290         -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
 291         -8200,
 292         /* Index 620 - 629 */
 293         -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
 294         -3900,
 295         /* Index 630 - 639 */
 296         -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
 297         200,
 298         /* Index 640 - 649 */
 299         600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
 300         4500,
 301         /* Index 650 - 659 */
 302         5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
 303         8600,
 304         /* Index 660 - 669 */
 305         9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
 306         12700,
 307         /* Index 670 - 679 */
 308         13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
 309         17000,
 310         /* Index 680 - 689 */
 311         17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
 312         21000,
 313         /* Index 690 - 699 */
 314         21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
 315         25400,
 316         /* Index 700 - 709 */
 317         25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
 318         29400,
 319         /* Index 710 - 719 */
 320         29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
 321         33800,
 322         /* Index 720 - 729 */
 323         34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
 324         37800,
 325         /* Index 730 - 739 */
 326         38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
 327         41800,
 328         /* Index 740 - 749 */
 329         42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
 330         46200,
 331         /* Index 750 - 759 */
 332         46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
 333         50200,
 334         /* Index 760 - 769 */
 335         50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
 336         54200,
 337         /* Index 770 - 779 */
 338         54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
 339         58600,
 340         /* Index 780 - 789 */
 341         59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
 342         62600,
 343         /* Index 790 - 799 */
 344         63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
 345         66600,
 346         /* Index 800 - 809 */
 347         67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
 348         70600,
 349         /* Index 810 - 819 */
 350         71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
 351         75000,
 352         /* Index 820 - 829 */
 353         75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
 354         79000,
 355         /* Index 830 - 839 */
 356         79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
 357         83000,
 358         /* Index 840 - 849 */
 359         83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
 360         87000,
 361         /* Index 850 - 859 */
 362         87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
 363         91000,
 364         /* Index 860 - 869 */
 365         91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
 366         95000,
 367         /* Index 870 - 879 */
 368         95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
 369         99400,
 370         /* Index 880 - 889 */
 371         99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
 372         103400,
 373         /* Index 890 - 899 */
 374         103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
 375         107400,
 376         /* Index 900 - 909 */
 377         107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
 378         111400,
 379         /* Index 910 - 919 */
 380         111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
 381         115400,
 382         /* Index 920 - 929 */
 383         115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
 384         119400,
 385         /* Index 930 - 939 */
 386         119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
 387         123400,
 388         /* Index 940 - 945 */
 389         123800, 124200, 124600, 124900, 125000, 125000,
 390 };
 391
 392 /* DRA752 data */
 393 const struct ti_bandgap_data dra752_data = {
 394         .features = TI_BANDGAP_FEATURE_FREEZE_BIT |
 395                         TI_BANDGAP_FEATURE_TALERT |
 396                         TI_BANDGAP_FEATURE_COUNTER_DELAY |
 397                         TI_BANDGAP_FEATURE_HISTORY_BUFFER |
 398                         TI_BANDGAP_FEATURE_ERRATA_814,
 399         .fclock_name = "l3instr_ts_gclk_div",
 400         .div_ck_name = "l3instr_ts_gclk_div",
 401         .conv_table = dra752_adc_to_temp,
 402         .adc_start_val = DRA752_ADC_START_VALUE,
 403         .adc_end_val = DRA752_ADC_END_VALUE,
 404         .expose_sensor = ti_thermal_expose_sensor,
 405         .remove_sensor = ti_thermal_remove_sensor,
 406         .sensors = {
 407                 {
 408                 .registers = &dra752_mpu_temp_sensor_registers,
 409                 .ts_data = &dra752_mpu_temp_sensor_data,
 410                 .domain = "cpu",
 411                 .register_cooling = ti_thermal_register_cpu_cooling,
 412                 .unregister_cooling = ti_thermal_unregister_cpu_cooling,
 413                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 414                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 415                 },
 416                 {
 417                 .registers = &dra752_gpu_temp_sensor_registers,
 418                 .ts_data = &dra752_gpu_temp_sensor_data,
 419                 .domain = "gpu",
 420                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 421                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 422                 },
 423                 {
 424                 .registers = &dra752_core_temp_sensor_registers,
 425                 .ts_data = &dra752_core_temp_sensor_data,
 426                 .domain = "core",
 427                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 428                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 429                 },
 430                 {
 431                 .registers = &dra752_dspeve_temp_sensor_registers,
 432                 .ts_data = &dra752_dspeve_temp_sensor_data,
 433                 .domain = "dspeve",
 434                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 435                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 436                 },
 437                 {
 438                 .registers = &dra752_iva_temp_sensor_registers,
 439                 .ts_data = &dra752_iva_temp_sensor_data,
 440                 .domain = "iva",
 441                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 442                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 443                 },
 444         },
 445         .sensor_count = 5,
 446 };