?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / tty / serial / max310x.c
blob39f635812077ad3848fa910770bac7de0b23f344
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
4 *
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
6 *
7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
9 * Based on max3107.c, by Aavamobile
10 */
11
12 #include <linux/bitops.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/regmap.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/spi/spi.h>
26 #include <linux/uaccess.h>
27
28 #define MAX310X_NAME "max310x"
29 #define MAX310X_MAJOR 204
30 #define MAX310X_MINOR 209
31 #define MAX310X_UART_NRMAX 16
32
33 /* MAX310X register definitions */
34 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
35 #define MAX310X_THR_REG (0x00) /* TX FIFO */
36 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
37 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
38 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
39 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
40 #define MAX310X_REG_05 (0x05)
41 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
42 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
43 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
44 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
45 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
46 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
47 #define MAX310X_LCR_REG (0x0b) /* LCR */
48 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
49 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
50 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
51 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
52 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
53 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
54 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
55 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
56 #define MAX310X_XON1_REG (0x14) /* XON1 character */
57 #define MAX310X_XON2_REG (0x15) /* XON2 character */
58 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
59 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
60 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
61 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
62 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
63 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
64 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
65 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
66 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
67 #define MAX310X_REG_1F (0x1f)
68
69 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
70
71 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
72 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
73
74 /* Extended registers */
75 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
76
77 /* IRQ register bits */
78 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
79 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
80 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
81 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
82 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
83 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
84 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
85 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
86
87 /* LSR register bits */
88 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
89 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
90 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
91 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
92 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
93 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
94 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
95
96 /* Special character register bits */
97 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
98 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
99 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
100 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
101 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
103
104 /* Status register bits */
105 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
106 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
107 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
108 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
109 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
110 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
111
112 /* MODE1 register bits */
113 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
114 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
117 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
118 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
119 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
120 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
121
122 /* MODE2 register bits */
123 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
124 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
125 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
126 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
127 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
128 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
129 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
130 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
131
132 /* LCR register bits */
133 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
134 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
135 *
136 * Word length bits table:
137 * 00 -> 5 bit words
138 * 01 -> 6 bit words
139 * 10 -> 7 bit words
140 * 11 -> 8 bit words
141 */
142 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
143 *
144 * STOP length bit table:
145 * 0 -> 1 stop bit
146 * 1 -> 1-1.5 stop bits if
147 * word length is 5,
148 * 2 stop bits otherwise
149 */
150 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
151 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
152 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
153 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
154 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
155
156 /* IRDA register bits */
157 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
158 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
159
160 /* Flow control trigger level register masks */
161 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
162 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
163 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
164 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
165
166 /* FIFO interrupt trigger level register masks */
167 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
168 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
169 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
170 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
171
172 /* Flow control register bits */
173 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
175 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
176 * are used in conjunction with
177 * XOFF2 for definition of
178 * special character */
179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
180 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
181 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
182 *
183 * SWFLOW bits 1 & 0 table:
184 * 00 -> no transmitter flow
185 * control
186 * 01 -> receiver compares
187 * XON2 and XOFF2
188 * and controls
189 * transmitter
190 * 10 -> receiver compares
191 * XON1 and XOFF1
192 * and controls
193 * transmitter
194 * 11 -> receiver compares
195 * XON1, XON2, XOFF1 and
196 * XOFF2 and controls
197 * transmitter
198 */
199 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
200 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
201 *
202 * SWFLOW bits 3 & 2 table:
203 * 00 -> no received flow
204 * control
205 * 01 -> transmitter generates
206 * XON2 and XOFF2
207 * 10 -> transmitter generates
208 * XON1 and XOFF1
209 * 11 -> transmitter generates
210 * XON1, XON2, XOFF1 and
211 * XOFF2
212 */
213
214 /* PLL configuration register masks */
215 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
216 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
217
218 /* Baud rate generator configuration register bits */
219 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
220 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
221
222 /* Clock source register bits */
223 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
224 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
225 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
226 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
227 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
228
229 /* Global commands */
230 #define MAX310X_EXTREG_ENBL (0xce)
231 #define MAX310X_EXTREG_DSBL (0xcd)
232
233 /* Misc definitions */
234 #define MAX310X_FIFO_SIZE (128)
235 #define MAX310x_REV_MASK (0xf8)
236 #define MAX310X_WRITE_BIT 0x80
237
238 /* MAX3107 specific */
239 #define MAX3107_REV_ID (0xa0)
240
241 /* MAX3109 specific */
242 #define MAX3109_REV_ID (0xc0)
243
244 /* MAX14830 specific */
245 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
246 #define MAX14830_REV_ID (0xb0)
247
248 struct max310x_devtype {
249 char name[9];
250 int nr;
251 int (*detect)(struct device *);
252 void (*power)(struct uart_port *, int);
253 };
254
255 struct max310x_one {
256 struct uart_port port;
257 struct work_struct tx_work;
258 struct work_struct md_work;
259 struct work_struct rs_work;
260 };
261
262 struct max310x_port {
263 struct max310x_devtype *devtype;
264 struct regmap *regmap;
265 struct mutex mutex;
266 struct clk *clk;
267 #ifdef CONFIG_GPIOLIB
268 struct gpio_chip gpio;
269 #endif
270 struct max310x_one p[0];
271 };
272
273 static struct uart_driver max310x_uart = {
274 .owner = THIS_MODULE,
275 .driver_name = MAX310X_NAME,
276 .dev_name = "ttyMAX",
277 .major = MAX310X_MAJOR,
278 .minor = MAX310X_MINOR,
279 .nr = MAX310X_UART_NRMAX,
280 };
281
282 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
283
284 static u8 max310x_port_read(struct uart_port *port, u8 reg)
285 {
286 struct max310x_port *s = dev_get_drvdata(port->dev);
287 unsigned int val = 0;
288
289 regmap_read(s->regmap, port->iobase + reg, &val);
290
291 return val;
292 }
293
294 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
295 {
296 struct max310x_port *s = dev_get_drvdata(port->dev);
297
298 regmap_write(s->regmap, port->iobase + reg, val);
299 }
300
301 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
302 {
303 struct max310x_port *s = dev_get_drvdata(port->dev);
304
305 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
306 }
307
308 static int max3107_detect(struct device *dev)
309 {
310 struct max310x_port *s = dev_get_drvdata(dev);
311 unsigned int val = 0;
312 int ret;
313
314 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
315 if (ret)
316 return ret;
317
318 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
319 dev_err(dev,
320 "%s ID 0x%02x does not match\n", s->devtype->name, val);
321 return -ENODEV;
322 }
323
324 return 0;
325 }
326
327 static int max3108_detect(struct device *dev)
328 {
329 struct max310x_port *s = dev_get_drvdata(dev);
330 unsigned int val = 0;
331 int ret;
332
333 /* MAX3108 have not REV ID register, we just check default value
334 * from clocksource register to make sure everything works.
335 */
336 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
337 if (ret)
338 return ret;
339
340 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
341 dev_err(dev, "%s not present\n", s->devtype->name);
342 return -ENODEV;
343 }
344
345 return 0;
346 }
347
348 static int max3109_detect(struct device *dev)
349 {
350 struct max310x_port *s = dev_get_drvdata(dev);
351 unsigned int val = 0;
352 int ret;
353
354 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
355 MAX310X_EXTREG_ENBL);
356 if (ret)
357 return ret;
358
359 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
360 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
361 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
362 dev_err(dev,
363 "%s ID 0x%02x does not match\n", s->devtype->name, val);
364 return -ENODEV;
365 }
366
367 return 0;
368 }
369
370 static void max310x_power(struct uart_port *port, int on)
371 {
372 max310x_port_update(port, MAX310X_MODE1_REG,
373 MAX310X_MODE1_FORCESLEEP_BIT,
374 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
375 if (on)
376 msleep(50);
377 }
378
379 static int max14830_detect(struct device *dev)
380 {
381 struct max310x_port *s = dev_get_drvdata(dev);
382 unsigned int val = 0;
383 int ret;
384
385 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
386 MAX310X_EXTREG_ENBL);
387 if (ret)
388 return ret;
389
390 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
391 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
392 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
393 dev_err(dev,
394 "%s ID 0x%02x does not match\n", s->devtype->name, val);
395 return -ENODEV;
396 }
397
398 return 0;
399 }
400
401 static void max14830_power(struct uart_port *port, int on)
402 {
403 max310x_port_update(port, MAX310X_BRGCFG_REG,
404 MAX14830_BRGCFG_CLKDIS_BIT,
405 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
406 if (on)
407 msleep(50);
408 }
409
410 static const struct max310x_devtype max3107_devtype = {
411 .name = "MAX3107",
412 .nr = 1,
413 .detect = max3107_detect,
414 .power = max310x_power,
415 };
416
417 static const struct max310x_devtype max3108_devtype = {
418 .name = "MAX3108",
419 .nr = 1,
420 .detect = max3108_detect,
421 .power = max310x_power,
422 };
423
424 static const struct max310x_devtype max3109_devtype = {
425 .name = "MAX3109",
426 .nr = 2,
427 .detect = max3109_detect,
428 .power = max310x_power,
429 };
430
431 static const struct max310x_devtype max14830_devtype = {
432 .name = "MAX14830",
433 .nr = 4,
434 .detect = max14830_detect,
435 .power = max14830_power,
436 };
437
438 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
439 {
440 switch (reg & 0x1f) {
441 case MAX310X_IRQSTS_REG:
442 case MAX310X_LSR_IRQSTS_REG:
443 case MAX310X_SPCHR_IRQSTS_REG:
444 case MAX310X_STS_IRQSTS_REG:
445 case MAX310X_TXFIFOLVL_REG:
446 case MAX310X_RXFIFOLVL_REG:
447 return false;
448 default:
449 break;
450 }
451
452 return true;
453 }
454
455 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
456 {
457 switch (reg & 0x1f) {
458 case MAX310X_RHR_REG:
459 case MAX310X_IRQSTS_REG:
460 case MAX310X_LSR_IRQSTS_REG:
461 case MAX310X_SPCHR_IRQSTS_REG:
462 case MAX310X_STS_IRQSTS_REG:
463 case MAX310X_TXFIFOLVL_REG:
464 case MAX310X_RXFIFOLVL_REG:
465 case MAX310X_GPIODATA_REG:
466 case MAX310X_BRGDIVLSB_REG:
467 case MAX310X_REG_05:
468 case MAX310X_REG_1F:
469 return true;
470 default:
471 break;
472 }
473
474 return false;
475 }
476
477 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
478 {
479 switch (reg & 0x1f) {
480 case MAX310X_RHR_REG:
481 case MAX310X_IRQSTS_REG:
482 case MAX310X_SPCHR_IRQSTS_REG:
483 case MAX310X_STS_IRQSTS_REG:
484 return true;
485 default:
486 break;
487 }
488
489 return false;
490 }
491
492 static int max310x_set_baud(struct uart_port *port, int baud)
493 {
494 unsigned int mode = 0, clk = port->uartclk, div = clk / baud;
495
496 /* Check for minimal value for divider */
497 if (div < 16)
498 div = 16;
499
500 if (clk % baud && (div / 16) < 0x8000) {
501 /* Mode x2 */
502 mode = MAX310X_BRGCFG_2XMODE_BIT;
503 clk = port->uartclk * 2;
504 div = clk / baud;
505
506 if (clk % baud && (div / 16) < 0x8000) {
507 /* Mode x4 */
508 mode = MAX310X_BRGCFG_4XMODE_BIT;
509 clk = port->uartclk * 4;
510 div = clk / baud;
511 }
512 }
513
514 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);
515 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);
516 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode);
517
518 return DIV_ROUND_CLOSEST(clk, div);
519 }
520
521 static int max310x_update_best_err(unsigned long f, long *besterr)
522 {
523 /* Use baudrate 115200 for calculate error */
524 long err = f % (115200 * 16);
525
526 if ((*besterr < 0) || (*besterr > err)) {
527 *besterr = err;
528 return 0;
529 }
530
531 return 1;
532 }
533
534 static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
535 bool xtal)
536 {
537 unsigned int div, clksrc, pllcfg = 0;
538 long besterr = -1;
539 unsigned long fdiv, fmul, bestfreq = freq;
540
541 /* First, update error without PLL */
542 max310x_update_best_err(freq, &besterr);
543
544 /* Try all possible PLL dividers */
545 for (div = 1; (div <= 63) && besterr; div++) {
546 fdiv = DIV_ROUND_CLOSEST(freq, div);
547
548 /* Try multiplier 6 */
549 fmul = fdiv * 6;
550 if ((fdiv >= 500000) && (fdiv <= 800000))
551 if (!max310x_update_best_err(fmul, &besterr)) {
552 pllcfg = (0 << 6) | div;
553 bestfreq = fmul;
554 }
555 /* Try multiplier 48 */
556 fmul = fdiv * 48;
557 if ((fdiv >= 850000) && (fdiv <= 1200000))
558 if (!max310x_update_best_err(fmul, &besterr)) {
559 pllcfg = (1 << 6) | div;
560 bestfreq = fmul;
561 }
562 /* Try multiplier 96 */
563 fmul = fdiv * 96;
564 if ((fdiv >= 425000) && (fdiv <= 1000000))
565 if (!max310x_update_best_err(fmul, &besterr)) {
566 pllcfg = (2 << 6) | div;
567 bestfreq = fmul;
568 }
569 /* Try multiplier 144 */
570 fmul = fdiv * 144;
571 if ((fdiv >= 390000) && (fdiv <= 667000))
572 if (!max310x_update_best_err(fmul, &besterr)) {
573 pllcfg = (3 << 6) | div;
574 bestfreq = fmul;
575 }
576 }
577
578 /* Configure clock source */
579 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT;
580
581 /* Configure PLL */
582 if (pllcfg) {
583 clksrc |= MAX310X_CLKSRC_PLL_BIT;
584 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
585 } else
586 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
587
588 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
589
590 /* Wait for crystal */
591 if (pllcfg && xtal)
592 msleep(10);
593
594 return (int)bestfreq;
595 }
596
597 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len)
598 {
599 u8 header[] = { (port->iobase + MAX310X_THR_REG) | MAX310X_WRITE_BIT };
600 struct spi_transfer xfer[] = {
601 {
602 .tx_buf = &header,
603 .len = sizeof(header),
604 }, {
605 .tx_buf = txbuf,
606 .len = len,
607 }
608 };
609 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
610 }
611
612 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len)
613 {
614 u8 header[] = { port->iobase + MAX310X_RHR_REG };
615 struct spi_transfer xfer[] = {
616 {
617 .tx_buf = &header,
618 .len = sizeof(header),
619 }, {
620 .rx_buf = rxbuf,
621 .len = len,
622 }
623 };
624 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer));
625 }
626
627 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
628 {
629 unsigned int sts, ch, flag, i;
630 u8 buf[MAX310X_FIFO_SIZE];
631
632 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) {
633 /* We are just reading, happily ignoring any error conditions.
634 * Break condition, parity checking, framing errors -- they
635 * are all ignored. That means that we can do a batch-read.
636 *
637 * There is a small opportunity for race if the RX FIFO
638 * overruns while we're reading the buffer; the datasheets says
639 * that the LSR register applies to the "current" character.
640 * That's also the reason why we cannot do batched reads when
641 * asked to check the individual statuses.
642 * */
643
644 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
645 max310x_batch_read(port, buf, rxlen);
646
647 port->icount.rx += rxlen;
648 flag = TTY_NORMAL;
649 sts &= port->read_status_mask;
650
651 if (sts & MAX310X_LSR_RXOVR_BIT) {
652 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n");
653 port->icount.overrun++;
654 }
655
656 for (i = 0; i < rxlen; ++i) {
657 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, buf[i], flag);
658 }
659
660 } else {
661 if (unlikely(rxlen >= port->fifosize)) {
662 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
663 port->icount.buf_overrun++;
664 /* Ensure sanity of RX level */
665 rxlen = port->fifosize;
666 }
667
668 while (rxlen--) {
669 ch = max310x_port_read(port, MAX310X_RHR_REG);
670 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
671
672 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
673 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
674
675 port->icount.rx++;
676 flag = TTY_NORMAL;
677
678 if (unlikely(sts)) {
679 if (sts & MAX310X_LSR_RXBRK_BIT) {
680 port->icount.brk++;
681 if (uart_handle_break(port))
682 continue;
683 } else if (sts & MAX310X_LSR_RXPAR_BIT)
684 port->icount.parity++;
685 else if (sts & MAX310X_LSR_FRERR_BIT)
686 port->icount.frame++;
687 else if (sts & MAX310X_LSR_RXOVR_BIT)
688 port->icount.overrun++;
689
690 sts &= port->read_status_mask;
691 if (sts & MAX310X_LSR_RXBRK_BIT)
692 flag = TTY_BREAK;
693 else if (sts & MAX310X_LSR_RXPAR_BIT)
694 flag = TTY_PARITY;
695 else if (sts & MAX310X_LSR_FRERR_BIT)
696 flag = TTY_FRAME;
697 else if (sts & MAX310X_LSR_RXOVR_BIT)
698 flag = TTY_OVERRUN;
699 }
700
701 if (uart_handle_sysrq_char(port, ch))
702 continue;
703
704 if (sts & port->ignore_status_mask)
705 continue;
706
707 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
708 }
709 }
710
711 tty_flip_buffer_push(&port->state->port);
712 }
713
714 static void max310x_handle_tx(struct uart_port *port)
715 {
716 struct circ_buf *xmit = &port->state->xmit;
717 unsigned int txlen, to_send, until_end;
718
719 if (unlikely(port->x_char)) {
720 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
721 port->icount.tx++;
722 port->x_char = 0;
723 return;
724 }
725
726 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
727 return;
728
729 /* Get length of data pending in circular buffer */
730 to_send = uart_circ_chars_pending(xmit);
731 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
732 if (likely(to_send)) {
733 /* Limit to size of TX FIFO */
734 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
735 txlen = port->fifosize - txlen;
736 to_send = (to_send > txlen) ? txlen : to_send;
737
738 if (until_end < to_send) {
739 /* It's a circ buffer -- wrap around.
740 * We could do that in one SPI transaction, but meh. */
741 max310x_batch_write(port, xmit->buf + xmit->tail, until_end);
742 max310x_batch_write(port, xmit->buf, to_send - until_end);
743 } else {
744 max310x_batch_write(port, xmit->buf + xmit->tail, to_send);
745 }
746
747 /* Add data to send */
748 port->icount.tx += to_send;
749 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1);
750 }
751
752 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
753 uart_write_wakeup(port);
754 }
755
756 static void max310x_start_tx(struct uart_port *port)
757 {
758 struct max310x_one *one = container_of(port, struct max310x_one, port);
759
760 if (!work_pending(&one->tx_work))
761 schedule_work(&one->tx_work);
762 }
763
764 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno)
765 {
766 struct uart_port *port = &s->p[portno].port;
767 irqreturn_t res = IRQ_NONE;
768
769 do {
770 unsigned int ists, lsr, rxlen;
771
772 /* Read IRQ status & RX FIFO level */
773 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
774 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
775 if (!ists && !rxlen)
776 break;
777
778 res = IRQ_HANDLED;
779
780 if (ists & MAX310X_IRQ_CTS_BIT) {
781 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
782 uart_handle_cts_change(port,
783 !!(lsr & MAX310X_LSR_CTS_BIT));
784 }
785 if (rxlen)
786 max310x_handle_rx(port, rxlen);
787 if (ists & MAX310X_IRQ_TXEMPTY_BIT)
788 max310x_start_tx(port);
789 } while (1);
790 return res;
791 }
792
793 static irqreturn_t max310x_ist(int irq, void *dev_id)
794 {
795 struct max310x_port *s = (struct max310x_port *)dev_id;
796 bool handled = false;
797
798 if (s->devtype->nr > 1) {
799 do {
800 unsigned int val = ~0;
801
802 WARN_ON_ONCE(regmap_read(s->regmap,
803 MAX310X_GLOBALIRQ_REG, &val));
804 val = ((1 << s->devtype->nr) - 1) & ~val;
805 if (!val)
806 break;
807 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED)
808 handled = true;
809 } while (1);
810 } else {
811 if (max310x_port_irq(s, 0) == IRQ_HANDLED)
812 handled = true;
813 }
814
815 return IRQ_RETVAL(handled);
816 }
817
818 static void max310x_wq_proc(struct work_struct *ws)
819 {
820 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
821 struct max310x_port *s = dev_get_drvdata(one->port.dev);
822
823 mutex_lock(&s->mutex);
824 max310x_handle_tx(&one->port);
825 mutex_unlock(&s->mutex);
826 }
827
828 static unsigned int max310x_tx_empty(struct uart_port *port)
829 {
830 unsigned int lvl, sts;
831
832 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
833 sts = max310x_port_read(port, MAX310X_IRQSTS_REG);
834
835 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0;
836 }
837
838 static unsigned int max310x_get_mctrl(struct uart_port *port)
839 {
840 /* DCD and DSR are not wired and CTS/RTS is handled automatically
841 * so just indicate DSR and CAR asserted
842 */
843 return TIOCM_DSR | TIOCM_CAR;
844 }
845
846 static void max310x_md_proc(struct work_struct *ws)
847 {
848 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
849
850 max310x_port_update(&one->port, MAX310X_MODE2_REG,
851 MAX310X_MODE2_LOOPBACK_BIT,
852 (one->port.mctrl & TIOCM_LOOP) ?
853 MAX310X_MODE2_LOOPBACK_BIT : 0);
854 }
855
856 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
857 {
858 struct max310x_one *one = container_of(port, struct max310x_one, port);
859
860 schedule_work(&one->md_work);
861 }
862
863 static void max310x_break_ctl(struct uart_port *port, int break_state)
864 {
865 max310x_port_update(port, MAX310X_LCR_REG,
866 MAX310X_LCR_TXBREAK_BIT,
867 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
868 }
869
870 static void max310x_set_termios(struct uart_port *port,
871 struct ktermios *termios,
872 struct ktermios *old)
873 {
874 unsigned int lcr = 0, flow = 0;
875 int baud;
876
877 /* Mask termios capabilities we don't support */
878 termios->c_cflag &= ~CMSPAR;
879
880 /* Word size */
881 switch (termios->c_cflag & CSIZE) {
882 case CS5:
883 break;
884 case CS6:
885 lcr = MAX310X_LCR_LENGTH0_BIT;
886 break;
887 case CS7:
888 lcr = MAX310X_LCR_LENGTH1_BIT;
889 break;
890 case CS8:
891 default:
892 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
893 break;
894 }
895
896 /* Parity */
897 if (termios->c_cflag & PARENB) {
898 lcr |= MAX310X_LCR_PARITY_BIT;
899 if (!(termios->c_cflag & PARODD))
900 lcr |= MAX310X_LCR_EVENPARITY_BIT;
901 }
902
903 /* Stop bits */
904 if (termios->c_cflag & CSTOPB)
905 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
906
907 /* Update LCR register */
908 max310x_port_write(port, MAX310X_LCR_REG, lcr);
909
910 /* Set read status mask */
911 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
912 if (termios->c_iflag & INPCK)
913 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
914 MAX310X_LSR_FRERR_BIT;
915 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
916 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
917
918 /* Set status ignore mask */
919 port->ignore_status_mask = 0;
920 if (termios->c_iflag & IGNBRK)
921 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
922 if (!(termios->c_cflag & CREAD))
923 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
924 MAX310X_LSR_RXOVR_BIT |
925 MAX310X_LSR_FRERR_BIT |
926 MAX310X_LSR_RXBRK_BIT;
927
928 /* Configure flow control */
929 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
930 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
931 if (termios->c_cflag & CRTSCTS)
932 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
933 MAX310X_FLOWCTRL_AUTORTS_BIT;
934 if (termios->c_iflag & IXON)
935 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
936 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
937 if (termios->c_iflag & IXOFF)
938 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
939 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
940 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
941
942 /* Get baud rate generator configuration */
943 baud = uart_get_baud_rate(port, termios, old,
944 port->uartclk / 16 / 0xffff,
945 port->uartclk / 4);
946
947 /* Setup baudrate generator */
948 baud = max310x_set_baud(port, baud);
949
950 /* Update timeout according to new baud rate */
951 uart_update_timeout(port, termios->c_cflag, baud);
952 }
953
954 static void max310x_rs_proc(struct work_struct *ws)
955 {
956 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
957 unsigned int val;
958
959 val = (one->port.rs485.delay_rts_before_send << 4) |
960 one->port.rs485.delay_rts_after_send;
961 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val);
962
963 if (one->port.rs485.flags & SER_RS485_ENABLED) {
964 max310x_port_update(&one->port, MAX310X_MODE1_REG,
965 MAX310X_MODE1_TRNSCVCTRL_BIT,
966 MAX310X_MODE1_TRNSCVCTRL_BIT);
967 max310x_port_update(&one->port, MAX310X_MODE2_REG,
968 MAX310X_MODE2_ECHOSUPR_BIT,
969 MAX310X_MODE2_ECHOSUPR_BIT);
970 } else {
971 max310x_port_update(&one->port, MAX310X_MODE1_REG,
972 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
973 max310x_port_update(&one->port, MAX310X_MODE2_REG,
974 MAX310X_MODE2_ECHOSUPR_BIT, 0);
975 }
976 }
977
978 static int max310x_rs485_config(struct uart_port *port,
979 struct serial_rs485 *rs485)
980 {
981 struct max310x_one *one = container_of(port, struct max310x_one, port);
982
983 if ((rs485->delay_rts_before_send > 0x0f) ||
984 (rs485->delay_rts_after_send > 0x0f))
985 return -ERANGE;
986
987 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
988 memset(rs485->padding, 0, sizeof(rs485->padding));
989 port->rs485 = *rs485;
990
991 schedule_work(&one->rs_work);
992
993 return 0;
994 }
995
996 static int max310x_startup(struct uart_port *port)
997 {
998 struct max310x_port *s = dev_get_drvdata(port->dev);
999 unsigned int val;
1000
1001 s->devtype->power(port, 1);
1002
1003 /* Configure MODE1 register */
1004 max310x_port_update(port, MAX310X_MODE1_REG,
1005 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
1006
1007 /* Configure MODE2 register & Reset FIFOs*/
1008 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
1009 max310x_port_write(port, MAX310X_MODE2_REG, val);
1010 max310x_port_update(port, MAX310X_MODE2_REG,
1011 MAX310X_MODE2_FIFORST_BIT, 0);
1012
1013 /* Configure flow control levels */
1014 /* Flow control halt level 96, resume level 48 */
1015 max310x_port_write(port, MAX310X_FLOWLVL_REG,
1016 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
1017
1018 /* Clear IRQ status register */
1019 max310x_port_read(port, MAX310X_IRQSTS_REG);
1020
1021 /* Enable RX, TX, CTS change interrupts */
1022 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
1023 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
1024
1025 return 0;
1026 }
1027
1028 static void max310x_shutdown(struct uart_port *port)
1029 {
1030 struct max310x_port *s = dev_get_drvdata(port->dev);
1031
1032 /* Disable all interrupts */
1033 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
1034
1035 s->devtype->power(port, 0);
1036 }
1037
1038 static const char *max310x_type(struct uart_port *port)
1039 {
1040 struct max310x_port *s = dev_get_drvdata(port->dev);
1041
1042 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
1043 }
1044
1045 static int max310x_request_port(struct uart_port *port)
1046 {
1047 /* Do nothing */
1048 return 0;
1049 }
1050
1051 static void max310x_config_port(struct uart_port *port, int flags)
1052 {
1053 if (flags & UART_CONFIG_TYPE)
1054 port->type = PORT_MAX310X;
1055 }
1056
1057 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
1058 {
1059 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
1060 return -EINVAL;
1061 if (s->irq != port->irq)
1062 return -EINVAL;
1063
1064 return 0;
1065 }
1066
1067 static void max310x_null_void(struct uart_port *port)
1068 {
1069 /* Do nothing */
1070 }
1071
1072 static const struct uart_ops max310x_ops = {
1073 .tx_empty = max310x_tx_empty,
1074 .set_mctrl = max310x_set_mctrl,
1075 .get_mctrl = max310x_get_mctrl,
1076 .stop_tx = max310x_null_void,
1077 .start_tx = max310x_start_tx,
1078 .stop_rx = max310x_null_void,
1079 .break_ctl = max310x_break_ctl,
1080 .startup = max310x_startup,
1081 .shutdown = max310x_shutdown,
1082 .set_termios = max310x_set_termios,
1083 .type = max310x_type,
1084 .request_port = max310x_request_port,
1085 .release_port = max310x_null_void,
1086 .config_port = max310x_config_port,
1087 .verify_port = max310x_verify_port,
1088 };
1089
1090 static int __maybe_unused max310x_suspend(struct device *dev)
1091 {
1092 struct max310x_port *s = dev_get_drvdata(dev);
1093 int i;
1094
1095 for (i = 0; i < s->devtype->nr; i++) {
1096 uart_suspend_port(&max310x_uart, &s->p[i].port);
1097 s->devtype->power(&s->p[i].port, 0);
1098 }
1099
1100 return 0;
1101 }
1102
1103 static int __maybe_unused max310x_resume(struct device *dev)
1104 {
1105 struct max310x_port *s = dev_get_drvdata(dev);
1106 int i;
1107
1108 for (i = 0; i < s->devtype->nr; i++) {
1109 s->devtype->power(&s->p[i].port, 1);
1110 uart_resume_port(&max310x_uart, &s->p[i].port);
1111 }
1112
1113 return 0;
1114 }
1115
1116 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1117
1118 #ifdef CONFIG_GPIOLIB
1119 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1120 {
1121 unsigned int val;
1122 struct max310x_port *s = gpiochip_get_data(chip);
1123 struct uart_port *port = &s->p[offset / 4].port;
1124
1125 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1126
1127 return !!((val >> 4) & (1 << (offset % 4)));
1128 }
1129
1130 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1131 {
1132 struct max310x_port *s = gpiochip_get_data(chip);
1133 struct uart_port *port = &s->p[offset / 4].port;
1134
1135 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1136 value ? 1 << (offset % 4) : 0);
1137 }
1138
1139 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1140 {
1141 struct max310x_port *s = gpiochip_get_data(chip);
1142 struct uart_port *port = &s->p[offset / 4].port;
1143
1144 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1145
1146 return 0;
1147 }
1148
1149 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1150 unsigned offset, int value)
1151 {
1152 struct max310x_port *s = gpiochip_get_data(chip);
1153 struct uart_port *port = &s->p[offset / 4].port;
1154
1155 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1156 value ? 1 << (offset % 4) : 0);
1157 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1158 1 << (offset % 4));
1159
1160 return 0;
1161 }
1162
1163 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
1164 unsigned long config)
1165 {
1166 struct max310x_port *s = gpiochip_get_data(chip);
1167 struct uart_port *port = &s->p[offset / 4].port;
1168
1169 switch (pinconf_to_config_param(config)) {
1170 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1171 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1172 1 << ((offset % 4) + 4),
1173 1 << ((offset % 4) + 4));
1174 return 0;
1175 case PIN_CONFIG_DRIVE_PUSH_PULL:
1176 max310x_port_update(port, MAX310X_GPIOCFG_REG,
1177 1 << ((offset % 4) + 4), 0);
1178 return 0;
1179 default:
1180 return -ENOTSUPP;
1181 }
1182 }
1183 #endif
1184
1185 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1186 struct regmap *regmap, int irq)
1187 {
1188 int i, ret, fmin, fmax, freq, uartclk;
1189 struct clk *clk_osc, *clk_xtal;
1190 struct max310x_port *s;
1191 bool xtal = false;
1192
1193 if (IS_ERR(regmap))
1194 return PTR_ERR(regmap);
1195
1196 /* Alloc port structure */
1197 s = devm_kzalloc(dev, sizeof(*s) +
1198 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1199 if (!s) {
1200 dev_err(dev, "Error allocating port structure\n");
1201 return -ENOMEM;
1202 }
1203
1204 clk_osc = devm_clk_get(dev, "osc");
1205 clk_xtal = devm_clk_get(dev, "xtal");
1206 if (!IS_ERR(clk_osc)) {
1207 s->clk = clk_osc;
1208 fmin = 500000;
1209 fmax = 35000000;
1210 } else if (!IS_ERR(clk_xtal)) {
1211 s->clk = clk_xtal;
1212 fmin = 1000000;
1213 fmax = 4000000;
1214 xtal = true;
1215 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1216 PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1217 return -EPROBE_DEFER;
1218 } else {
1219 dev_err(dev, "Cannot get clock\n");
1220 return -EINVAL;
1221 }
1222
1223 ret = clk_prepare_enable(s->clk);
1224 if (ret)
1225 return ret;
1226
1227 freq = clk_get_rate(s->clk);
1228 /* Check frequency limits */
1229 if (freq < fmin || freq > fmax) {
1230 ret = -ERANGE;
1231 goto out_clk;
1232 }
1233
1234 s->regmap = regmap;
1235 s->devtype = devtype;
1236 dev_set_drvdata(dev, s);
1237
1238 /* Check device to ensure we are talking to what we expect */
1239 ret = devtype->detect(dev);
1240 if (ret)
1241 goto out_clk;
1242
1243 for (i = 0; i < devtype->nr; i++) {
1244 unsigned int offs = i << 5;
1245
1246 /* Reset port */
1247 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1248 MAX310X_MODE2_RST_BIT);
1249 /* Clear port reset */
1250 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1251
1252 /* Wait for port startup */
1253 do {
1254 regmap_read(s->regmap,
1255 MAX310X_BRGDIVLSB_REG + offs, &ret);
1256 } while (ret != 0x01);
1257
1258 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1259 MAX310X_MODE1_AUTOSLEEP_BIT,
1260 MAX310X_MODE1_AUTOSLEEP_BIT);
1261 }
1262
1263 uartclk = max310x_set_ref_clk(s, freq, xtal);
1264 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1265
1266 mutex_init(&s->mutex);
1267
1268 for (i = 0; i < devtype->nr; i++) {
1269 unsigned int line;
1270
1271 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1272 if (line == MAX310X_UART_NRMAX) {
1273 ret = -ERANGE;
1274 goto out_uart;
1275 }
1276
1277 /* Initialize port data */
1278 s->p[i].port.line = line;
1279 s->p[i].port.dev = dev;
1280 s->p[i].port.irq = irq;
1281 s->p[i].port.type = PORT_MAX310X;
1282 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1283 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1284 s->p[i].port.iotype = UPIO_PORT;
1285 s->p[i].port.iobase = i * 0x20;
1286 s->p[i].port.membase = (void __iomem *)~0;
1287 s->p[i].port.uartclk = uartclk;
1288 s->p[i].port.rs485_config = max310x_rs485_config;
1289 s->p[i].port.ops = &max310x_ops;
1290 /* Disable all interrupts */
1291 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1292 /* Clear IRQ status register */
1293 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1294 /* Enable IRQ pin */
1295 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1296 MAX310X_MODE1_IRQSEL_BIT,
1297 MAX310X_MODE1_IRQSEL_BIT);
1298 /* Initialize queue for start TX */
1299 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1300 /* Initialize queue for changing LOOPBACK mode */
1301 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1302 /* Initialize queue for changing RS485 mode */
1303 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1304
1305 /* Register port */
1306 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1307 if (ret) {
1308 s->p[i].port.dev = NULL;
1309 goto out_uart;
1310 }
1311 set_bit(line, max310x_lines);
1312
1313 /* Go to suspend mode */
1314 devtype->power(&s->p[i].port, 0);
1315 }
1316
1317 #ifdef CONFIG_GPIOLIB
1318 /* Setup GPIO cotroller */
1319 s->gpio.owner = THIS_MODULE;
1320 s->gpio.parent = dev;
1321 s->gpio.label = dev_name(dev);
1322 s->gpio.direction_input = max310x_gpio_direction_input;
1323 s->gpio.get = max310x_gpio_get;
1324 s->gpio.direction_output= max310x_gpio_direction_output;
1325 s->gpio.set = max310x_gpio_set;
1326 s->gpio.set_config = max310x_gpio_set_config;
1327 s->gpio.base = -1;
1328 s->gpio.ngpio = devtype->nr * 4;
1329 s->gpio.can_sleep = 1;
1330 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1331 if (ret)
1332 goto out_uart;
1333 #endif
1334
1335 /* Setup interrupt */
1336 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1337 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s);
1338 if (!ret)
1339 return 0;
1340
1341 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1342
1343 out_uart:
1344 for (i = 0; i < devtype->nr; i++) {
1345 if (s->p[i].port.dev) {
1346 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1347 clear_bit(s->p[i].port.line, max310x_lines);
1348 }
1349 }
1350
1351 mutex_destroy(&s->mutex);
1352
1353 out_clk:
1354 clk_disable_unprepare(s->clk);
1355
1356 return ret;
1357 }
1358
1359 static int max310x_remove(struct device *dev)
1360 {
1361 struct max310x_port *s = dev_get_drvdata(dev);
1362 int i;
1363
1364 for (i = 0; i < s->devtype->nr; i++) {
1365 cancel_work_sync(&s->p[i].tx_work);
1366 cancel_work_sync(&s->p[i].md_work);
1367 cancel_work_sync(&s->p[i].rs_work);
1368 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1369 clear_bit(s->p[i].port.line, max310x_lines);
1370 s->devtype->power(&s->p[i].port, 0);
1371 }
1372
1373 mutex_destroy(&s->mutex);
1374 clk_disable_unprepare(s->clk);
1375
1376 return 0;
1377 }
1378
1379 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1380 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1381 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1382 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1383 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1384 { }
1385 };
1386 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1387
1388 static struct regmap_config regcfg = {
1389 .reg_bits = 8,
1390 .val_bits = 8,
1391 .write_flag_mask = MAX310X_WRITE_BIT,
1392 .cache_type = REGCACHE_RBTREE,
1393 .writeable_reg = max310x_reg_writeable,
1394 .volatile_reg = max310x_reg_volatile,
1395 .precious_reg = max310x_reg_precious,
1396 };
1397
1398 #ifdef CONFIG_SPI_MASTER
1399 static int max310x_spi_probe(struct spi_device *spi)
1400 {
1401 struct max310x_devtype *devtype;
1402 struct regmap *regmap;
1403 int ret;
1404
1405 /* Setup SPI bus */
1406 spi->bits_per_word = 8;
1407 spi->mode = spi->mode ? : SPI_MODE_0;
1408 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1409 ret = spi_setup(spi);
1410 if (ret)
1411 return ret;
1412
1413 if (spi->dev.of_node) {
1414 const struct of_device_id *of_id =
1415 of_match_device(max310x_dt_ids, &spi->dev);
1416
1417 devtype = (struct max310x_devtype *)of_id->data;
1418 } else {
1419 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1420
1421 devtype = (struct max310x_devtype *)id_entry->driver_data;
1422 }
1423
1424 regcfg.max_register = devtype->nr * 0x20 - 1;
1425 regmap = devm_regmap_init_spi(spi, &regcfg);
1426
1427 return max310x_probe(&spi->dev, devtype, regmap, spi->irq);
1428 }
1429
1430 static int max310x_spi_remove(struct spi_device *spi)
1431 {
1432 return max310x_remove(&spi->dev);
1433 }
1434
1435 static const struct spi_device_id max310x_id_table[] = {
1436 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1437 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1438 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1439 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1440 { }
1441 };
1442 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1443
1444 static struct spi_driver max310x_spi_driver = {
1445 .driver = {
1446 .name = MAX310X_NAME,
1447 .of_match_table = of_match_ptr(max310x_dt_ids),
1448 .pm = &max310x_pm_ops,
1449 },
1450 .probe = max310x_spi_probe,
1451 .remove = max310x_spi_remove,
1452 .id_table = max310x_id_table,
1453 };
1454 #endif
1455
1456 static int __init max310x_uart_init(void)
1457 {
1458 int ret;
1459
1460 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1461
1462 ret = uart_register_driver(&max310x_uart);
1463 if (ret)
1464 return ret;
1465
1466 #ifdef CONFIG_SPI_MASTER
1467 spi_register_driver(&max310x_spi_driver);
1468 #endif
1469
1470 return 0;
1471 }
1472 module_init(max310x_uart_init);
1473
1474 static void __exit max310x_uart_exit(void)
1475 {
1476 #ifdef CONFIG_SPI_MASTER
1477 spi_unregister_driver(&max310x_spi_driver);
1478 #endif
1479
1480 uart_unregister_driver(&max310x_uart);
1481 }
1482 module_exit(max310x_uart_exit);
1483
1484 MODULE_LICENSE("GPL");
1485 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1486 MODULE_DESCRIPTION("MAX310X serial driver");
CRIS linux kernel tree