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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / tty / serial / pch_uart.c
blob760d5dd0aada2e34b198c70727741c671ed0ad16
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6 #define SUPPORT_SYSRQ
7 #endif
8 #include <linux/kernel.h>
9 #include <linux/serial_reg.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/console.h>
14 #include <linux/serial_core.h>
15 #include <linux/tty.h>
16 #include <linux/tty_flip.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/dmi.h>
20 #include <linux/nmi.h>
21 #include <linux/delay.h>
22 #include <linux/of.h>
23
24 #include <linux/debugfs.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pch_dma.h>
27
28 enum {
29 PCH_UART_HANDLED_RX_INT_SHIFT,
30 PCH_UART_HANDLED_TX_INT_SHIFT,
31 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
32 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
33 PCH_UART_HANDLED_MS_INT_SHIFT,
34 PCH_UART_HANDLED_LS_INT_SHIFT,
35 };
36
37 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
38
39 /* Set the max number of UART port
40 * Intel EG20T PCH: 4 port
41 * LAPIS Semiconductor ML7213 IOH: 3 port
42 * LAPIS Semiconductor ML7223 IOH: 2 port
43 */
44 #define PCH_UART_NR 4
45
46 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
47 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
48 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
49 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
50 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
51 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
52 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
53
54 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
55
56 #define PCH_UART_RBR 0x00
57 #define PCH_UART_THR 0x00
58
59 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
60 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
61 #define PCH_UART_IER_ERBFI 0x00000001
62 #define PCH_UART_IER_ETBEI 0x00000002
63 #define PCH_UART_IER_ELSI 0x00000004
64 #define PCH_UART_IER_EDSSI 0x00000008
65
66 #define PCH_UART_IIR_IP 0x00000001
67 #define PCH_UART_IIR_IID 0x00000006
68 #define PCH_UART_IIR_MSI 0x00000000
69 #define PCH_UART_IIR_TRI 0x00000002
70 #define PCH_UART_IIR_RRI 0x00000004
71 #define PCH_UART_IIR_REI 0x00000006
72 #define PCH_UART_IIR_TOI 0x00000008
73 #define PCH_UART_IIR_FIFO256 0x00000020
74 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
75 #define PCH_UART_IIR_FE 0x000000C0
76
77 #define PCH_UART_FCR_FIFOE 0x00000001
78 #define PCH_UART_FCR_RFR 0x00000002
79 #define PCH_UART_FCR_TFR 0x00000004
80 #define PCH_UART_FCR_DMS 0x00000008
81 #define PCH_UART_FCR_FIFO256 0x00000020
82 #define PCH_UART_FCR_RFTL 0x000000C0
83
84 #define PCH_UART_FCR_RFTL1 0x00000000
85 #define PCH_UART_FCR_RFTL64 0x00000040
86 #define PCH_UART_FCR_RFTL128 0x00000080
87 #define PCH_UART_FCR_RFTL224 0x000000C0
88 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
89 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
90 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
91 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
92 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
93 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
94 #define PCH_UART_FCR_RFTL_SHIFT 6
95
96 #define PCH_UART_LCR_WLS 0x00000003
97 #define PCH_UART_LCR_STB 0x00000004
98 #define PCH_UART_LCR_PEN 0x00000008
99 #define PCH_UART_LCR_EPS 0x00000010
100 #define PCH_UART_LCR_SP 0x00000020
101 #define PCH_UART_LCR_SB 0x00000040
102 #define PCH_UART_LCR_DLAB 0x00000080
103 #define PCH_UART_LCR_NP 0x00000000
104 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
105 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
106 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
107 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
108 PCH_UART_LCR_SP)
109
110 #define PCH_UART_LCR_5BIT 0x00000000
111 #define PCH_UART_LCR_6BIT 0x00000001
112 #define PCH_UART_LCR_7BIT 0x00000002
113 #define PCH_UART_LCR_8BIT 0x00000003
114
115 #define PCH_UART_MCR_DTR 0x00000001
116 #define PCH_UART_MCR_RTS 0x00000002
117 #define PCH_UART_MCR_OUT 0x0000000C
118 #define PCH_UART_MCR_LOOP 0x00000010
119 #define PCH_UART_MCR_AFE 0x00000020
120
121 #define PCH_UART_LSR_DR 0x00000001
122 #define PCH_UART_LSR_ERR (1<<7)
123
124 #define PCH_UART_MSR_DCTS 0x00000001
125 #define PCH_UART_MSR_DDSR 0x00000002
126 #define PCH_UART_MSR_TERI 0x00000004
127 #define PCH_UART_MSR_DDCD 0x00000008
128 #define PCH_UART_MSR_CTS 0x00000010
129 #define PCH_UART_MSR_DSR 0x00000020
130 #define PCH_UART_MSR_RI 0x00000040
131 #define PCH_UART_MSR_DCD 0x00000080
132 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
133 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
134
135 #define PCH_UART_DLL 0x00
136 #define PCH_UART_DLM 0x01
137
138 #define PCH_UART_BRCSR 0x0E
139
140 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
141 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
142 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
143 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
144 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
145
146 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
147 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
148 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
149 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
150 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
151 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
152 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
153 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
154 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
155 #define PCH_UART_HAL_STB1 0
156 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
157
158 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
159 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
160 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
161 PCH_UART_HAL_CLR_RX_FIFO)
162
163 #define PCH_UART_HAL_DMA_MODE0 0
164 #define PCH_UART_HAL_FIFO_DIS 0
165 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
166 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
167 PCH_UART_FCR_FIFO256)
168 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
169 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
170 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
171 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
172 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
173 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
174 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
175 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
176 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
177 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
178 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
179 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
180 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
181 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
182
183 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
184 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
185 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
186 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
187 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
188
189 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
190 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
191 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
192 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
193 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
194
195 #define PCI_VENDOR_ID_ROHM 0x10DB
196
197 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
198
199 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
200 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
201 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
202 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
203 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
204 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */
205
206 struct pch_uart_buffer {
207 unsigned char *buf;
208 int size;
209 };
210
211 struct eg20t_port {
212 struct uart_port port;
213 int port_type;
214 void __iomem *membase;
215 resource_size_t mapbase;
216 unsigned int iobase;
217 struct pci_dev *pdev;
218 int fifo_size;
219 unsigned int uartclk;
220 int start_tx;
221 int start_rx;
222 int tx_empty;
223 int trigger;
224 int trigger_level;
225 struct pch_uart_buffer rxbuf;
226 unsigned int dmsr;
227 unsigned int fcr;
228 unsigned int mcr;
229 unsigned int use_dma;
230 struct dma_async_tx_descriptor *desc_tx;
231 struct dma_async_tx_descriptor *desc_rx;
232 struct pch_dma_slave param_tx;
233 struct pch_dma_slave param_rx;
234 struct dma_chan *chan_tx;
235 struct dma_chan *chan_rx;
236 struct scatterlist *sg_tx_p;
237 int nent;
238 struct scatterlist sg_rx;
239 int tx_dma_use;
240 void *rx_buf_virt;
241 dma_addr_t rx_buf_dma;
242
243 struct dentry *debugfs;
244 #define IRQ_NAME_SIZE 17
245 char irq_name[IRQ_NAME_SIZE];
246
247 /* protect the eg20t_port private structure and io access to membase */
248 spinlock_t lock;
249 };
250
251 /**
252 * struct pch_uart_driver_data - private data structure for UART-DMA
253 * @port_type: The type of UART port
254 * @line_no: UART port line number (0, 1, 2...)
255 */
256 struct pch_uart_driver_data {
257 int port_type;
258 int line_no;
259 };
260
261 enum pch_uart_num_t {
262 pch_et20t_uart0 = 0,
263 pch_et20t_uart1,
264 pch_et20t_uart2,
265 pch_et20t_uart3,
266 pch_ml7213_uart0,
267 pch_ml7213_uart1,
268 pch_ml7213_uart2,
269 pch_ml7223_uart0,
270 pch_ml7223_uart1,
271 pch_ml7831_uart0,
272 pch_ml7831_uart1,
273 };
274
275 static struct pch_uart_driver_data drv_dat[] = {
276 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
277 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
278 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
279 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
280 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
281 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
282 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
283 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
284 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
285 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
286 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
287 };
288
289 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
290 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
291 #endif
292 static unsigned int default_baud = 9600;
293 static unsigned int user_uartclk = 0;
294 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
295 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
296 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
297 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
298
299 #ifdef CONFIG_DEBUG_FS
300
301 #define PCH_REGS_BUFSIZE 1024
302
303
304 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
305 size_t count, loff_t *ppos)
306 {
307 struct eg20t_port *priv = file->private_data;
308 char *buf;
309 u32 len = 0;
310 ssize_t ret;
311 unsigned char lcr;
312
313 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
314 if (!buf)
315 return 0;
316
317 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
318 "PCH EG20T port[%d] regs:\n", priv->port.line);
319
320 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
321 "=================================\n");
322 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
323 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
324 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
325 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
326 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
327 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
328 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
329 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
331 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
333 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "BRCSR: \t0x%02x\n",
336 ioread8(priv->membase + PCH_UART_BRCSR));
337
338 lcr = ioread8(priv->membase + UART_LCR);
339 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
341 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
343 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
344 iowrite8(lcr, priv->membase + UART_LCR);
345
346 if (len > PCH_REGS_BUFSIZE)
347 len = PCH_REGS_BUFSIZE;
348
349 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
350 kfree(buf);
351 return ret;
352 }
353
354 static const struct file_operations port_regs_ops = {
355 .owner = THIS_MODULE,
356 .open = simple_open,
357 .read = port_show_regs,
358 .llseek = default_llseek,
359 };
360 #endif /* CONFIG_DEBUG_FS */
361
362 static const struct dmi_system_id pch_uart_dmi_table[] = {
363 {
364 .ident = "CM-iTC",
365 {
366 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
367 },
368 (void *)CMITC_UARTCLK,
369 },
370 {
371 .ident = "FRI2",
372 {
373 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
374 },
375 (void *)FRI2_64_UARTCLK,
376 },
377 {
378 .ident = "Fish River Island II",
379 {
380 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
381 },
382 (void *)FRI2_48_UARTCLK,
383 },
384 {
385 .ident = "COMe-mTT",
386 {
387 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
388 },
389 (void *)NTC1_UARTCLK,
390 },
391 {
392 .ident = "nanoETXexpress-TT",
393 {
394 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
395 },
396 (void *)NTC1_UARTCLK,
397 },
398 {
399 .ident = "MinnowBoard",
400 {
401 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
402 },
403 (void *)MINNOW_UARTCLK,
404 },
405 { }
406 };
407
408 /* Return UART clock, checking for board specific clocks. */
409 static unsigned int pch_uart_get_uartclk(void)
410 {
411 const struct dmi_system_id *d;
412
413 if (user_uartclk)
414 return user_uartclk;
415
416 d = dmi_first_match(pch_uart_dmi_table);
417 if (d)
418 return (unsigned long)d->driver_data;
419
420 return DEFAULT_UARTCLK;
421 }
422
423 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
424 unsigned int flag)
425 {
426 u8 ier = ioread8(priv->membase + UART_IER);
427 ier |= flag & PCH_UART_IER_MASK;
428 iowrite8(ier, priv->membase + UART_IER);
429 }
430
431 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
432 unsigned int flag)
433 {
434 u8 ier = ioread8(priv->membase + UART_IER);
435 ier &= ~(flag & PCH_UART_IER_MASK);
436 iowrite8(ier, priv->membase + UART_IER);
437 }
438
439 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
440 unsigned int parity, unsigned int bits,
441 unsigned int stb)
442 {
443 unsigned int dll, dlm, lcr;
444 int div;
445
446 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
447 if (div < 0 || USHRT_MAX <= div) {
448 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
449 return -EINVAL;
450 }
451
452 dll = (unsigned int)div & 0x00FFU;
453 dlm = ((unsigned int)div >> 8) & 0x00FFU;
454
455 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
456 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
457 return -EINVAL;
458 }
459
460 if (bits & ~PCH_UART_LCR_WLS) {
461 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
462 return -EINVAL;
463 }
464
465 if (stb & ~PCH_UART_LCR_STB) {
466 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
467 return -EINVAL;
468 }
469
470 lcr = parity;
471 lcr |= bits;
472 lcr |= stb;
473
474 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
475 __func__, baud, div, lcr, jiffies);
476 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
477 iowrite8(dll, priv->membase + PCH_UART_DLL);
478 iowrite8(dlm, priv->membase + PCH_UART_DLM);
479 iowrite8(lcr, priv->membase + UART_LCR);
480
481 return 0;
482 }
483
484 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
485 unsigned int flag)
486 {
487 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
488 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
489 __func__, flag);
490 return -EINVAL;
491 }
492
493 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
494 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
495 priv->membase + UART_FCR);
496 iowrite8(priv->fcr, priv->membase + UART_FCR);
497
498 return 0;
499 }
500
501 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
502 unsigned int dmamode,
503 unsigned int fifo_size, unsigned int trigger)
504 {
505 u8 fcr;
506
507 if (dmamode & ~PCH_UART_FCR_DMS) {
508 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
509 __func__, dmamode);
510 return -EINVAL;
511 }
512
513 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
514 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
515 __func__, fifo_size);
516 return -EINVAL;
517 }
518
519 if (trigger & ~PCH_UART_FCR_RFTL) {
520 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
521 __func__, trigger);
522 return -EINVAL;
523 }
524
525 switch (priv->fifo_size) {
526 case 256:
527 priv->trigger_level =
528 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
529 break;
530 case 64:
531 priv->trigger_level =
532 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
533 break;
534 case 16:
535 priv->trigger_level =
536 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
537 break;
538 default:
539 priv->trigger_level =
540 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
541 break;
542 }
543 fcr =
544 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
545 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
546 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
547 priv->membase + UART_FCR);
548 iowrite8(fcr, priv->membase + UART_FCR);
549 priv->fcr = fcr;
550
551 return 0;
552 }
553
554 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
555 {
556 unsigned int msr = ioread8(priv->membase + UART_MSR);
557 priv->dmsr = msr & PCH_UART_MSR_DELTA;
558 return (u8)msr;
559 }
560
561 static void pch_uart_hal_write(struct eg20t_port *priv,
562 const unsigned char *buf, int tx_size)
563 {
564 int i;
565 unsigned int thr;
566
567 for (i = 0; i < tx_size;) {
568 thr = buf[i++];
569 iowrite8(thr, priv->membase + PCH_UART_THR);
570 }
571 }
572
573 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
574 int rx_size)
575 {
576 int i;
577 u8 rbr, lsr;
578 struct uart_port *port = &priv->port;
579
580 lsr = ioread8(priv->membase + UART_LSR);
581 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
582 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
583 lsr = ioread8(priv->membase + UART_LSR)) {
584 rbr = ioread8(priv->membase + PCH_UART_RBR);
585
586 if (lsr & UART_LSR_BI) {
587 port->icount.brk++;
588 if (uart_handle_break(port))
589 continue;
590 }
591 #ifdef SUPPORT_SYSRQ
592 if (port->sysrq) {
593 if (uart_handle_sysrq_char(port, rbr))
594 continue;
595 }
596 #endif
597
598 buf[i++] = rbr;
599 }
600 return i;
601 }
602
603 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
604 {
605 return ioread8(priv->membase + UART_IIR) &\
606 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
607 }
608
609 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
610 {
611 return ioread8(priv->membase + UART_LSR);
612 }
613
614 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
615 {
616 unsigned int lcr;
617
618 lcr = ioread8(priv->membase + UART_LCR);
619 if (on)
620 lcr |= PCH_UART_LCR_SB;
621 else
622 lcr &= ~PCH_UART_LCR_SB;
623
624 iowrite8(lcr, priv->membase + UART_LCR);
625 }
626
627 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
628 int size)
629 {
630 struct uart_port *port = &priv->port;
631 struct tty_port *tport = &port->state->port;
632
633 tty_insert_flip_string(tport, buf, size);
634 tty_flip_buffer_push(tport);
635
636 return 0;
637 }
638
639 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
640 {
641 int ret = 0;
642 struct uart_port *port = &priv->port;
643
644 if (port->x_char) {
645 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
646 __func__, port->x_char, jiffies);
647 buf[0] = port->x_char;
648 port->x_char = 0;
649 ret = 1;
650 }
651
652 return ret;
653 }
654
655 static int dma_push_rx(struct eg20t_port *priv, int size)
656 {
657 int room;
658 struct uart_port *port = &priv->port;
659 struct tty_port *tport = &port->state->port;
660
661 room = tty_buffer_request_room(tport, size);
662
663 if (room < size)
664 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
665 size - room);
666 if (!room)
667 return 0;
668
669 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
670
671 port->icount.rx += room;
672
673 return room;
674 }
675
676 static void pch_free_dma(struct uart_port *port)
677 {
678 struct eg20t_port *priv;
679 priv = container_of(port, struct eg20t_port, port);
680
681 if (priv->chan_tx) {
682 dma_release_channel(priv->chan_tx);
683 priv->chan_tx = NULL;
684 }
685 if (priv->chan_rx) {
686 dma_release_channel(priv->chan_rx);
687 priv->chan_rx = NULL;
688 }
689
690 if (priv->rx_buf_dma) {
691 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
692 priv->rx_buf_dma);
693 priv->rx_buf_virt = NULL;
694 priv->rx_buf_dma = 0;
695 }
696
697 return;
698 }
699
700 static bool filter(struct dma_chan *chan, void *slave)
701 {
702 struct pch_dma_slave *param = slave;
703
704 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
705 chan->device->dev)) {
706 chan->private = param;
707 return true;
708 } else {
709 return false;
710 }
711 }
712
713 static void pch_request_dma(struct uart_port *port)
714 {
715 dma_cap_mask_t mask;
716 struct dma_chan *chan;
717 struct pci_dev *dma_dev;
718 struct pch_dma_slave *param;
719 struct eg20t_port *priv =
720 container_of(port, struct eg20t_port, port);
721 dma_cap_zero(mask);
722 dma_cap_set(DMA_SLAVE, mask);
723
724 /* Get DMA's dev information */
725 dma_dev = pci_get_slot(priv->pdev->bus,
726 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
727
728 /* Set Tx DMA */
729 param = &priv->param_tx;
730 param->dma_dev = &dma_dev->dev;
731 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
732
733 param->tx_reg = port->mapbase + UART_TX;
734 chan = dma_request_channel(mask, filter, param);
735 if (!chan) {
736 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
737 __func__);
738 return;
739 }
740 priv->chan_tx = chan;
741
742 /* Set Rx DMA */
743 param = &priv->param_rx;
744 param->dma_dev = &dma_dev->dev;
745 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
746
747 param->rx_reg = port->mapbase + UART_RX;
748 chan = dma_request_channel(mask, filter, param);
749 if (!chan) {
750 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
751 __func__);
752 dma_release_channel(priv->chan_tx);
753 priv->chan_tx = NULL;
754 return;
755 }
756
757 /* Get Consistent memory for DMA */
758 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
759 &priv->rx_buf_dma, GFP_KERNEL);
760 priv->chan_rx = chan;
761 }
762
763 static void pch_dma_rx_complete(void *arg)
764 {
765 struct eg20t_port *priv = arg;
766 struct uart_port *port = &priv->port;
767 int count;
768
769 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
770 count = dma_push_rx(priv, priv->trigger_level);
771 if (count)
772 tty_flip_buffer_push(&port->state->port);
773 async_tx_ack(priv->desc_rx);
774 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
775 PCH_UART_HAL_RX_ERR_INT);
776 }
777
778 static void pch_dma_tx_complete(void *arg)
779 {
780 struct eg20t_port *priv = arg;
781 struct uart_port *port = &priv->port;
782 struct circ_buf *xmit = &port->state->xmit;
783 struct scatterlist *sg = priv->sg_tx_p;
784 int i;
785
786 for (i = 0; i < priv->nent; i++, sg++) {
787 xmit->tail += sg_dma_len(sg);
788 port->icount.tx += sg_dma_len(sg);
789 }
790 xmit->tail &= UART_XMIT_SIZE - 1;
791 async_tx_ack(priv->desc_tx);
792 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
793 priv->tx_dma_use = 0;
794 priv->nent = 0;
795 kfree(priv->sg_tx_p);
796 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
797 }
798
799 static int pop_tx(struct eg20t_port *priv, int size)
800 {
801 int count = 0;
802 struct uart_port *port = &priv->port;
803 struct circ_buf *xmit = &port->state->xmit;
804
805 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
806 goto pop_tx_end;
807
808 do {
809 int cnt_to_end =
810 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
811 int sz = min(size - count, cnt_to_end);
812 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
813 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
814 count += sz;
815 } while (!uart_circ_empty(xmit) && count < size);
816
817 pop_tx_end:
818 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
819 count, size - count, jiffies);
820
821 return count;
822 }
823
824 static int handle_rx_to(struct eg20t_port *priv)
825 {
826 struct pch_uart_buffer *buf;
827 int rx_size;
828 int ret;
829 if (!priv->start_rx) {
830 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
831 PCH_UART_HAL_RX_ERR_INT);
832 return 0;
833 }
834 buf = &priv->rxbuf;
835 do {
836 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
837 ret = push_rx(priv, buf->buf, rx_size);
838 if (ret)
839 return 0;
840 } while (rx_size == buf->size);
841
842 return PCH_UART_HANDLED_RX_INT;
843 }
844
845 static int handle_rx(struct eg20t_port *priv)
846 {
847 return handle_rx_to(priv);
848 }
849
850 static int dma_handle_rx(struct eg20t_port *priv)
851 {
852 struct uart_port *port = &priv->port;
853 struct dma_async_tx_descriptor *desc;
854 struct scatterlist *sg;
855
856 priv = container_of(port, struct eg20t_port, port);
857 sg = &priv->sg_rx;
858
859 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
860
861 sg_dma_len(sg) = priv->trigger_level;
862
863 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
864 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
865
866 sg_dma_address(sg) = priv->rx_buf_dma;
867
868 desc = dmaengine_prep_slave_sg(priv->chan_rx,
869 sg, 1, DMA_DEV_TO_MEM,
870 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
871
872 if (!desc)
873 return 0;
874
875 priv->desc_rx = desc;
876 desc->callback = pch_dma_rx_complete;
877 desc->callback_param = priv;
878 desc->tx_submit(desc);
879 dma_async_issue_pending(priv->chan_rx);
880
881 return PCH_UART_HANDLED_RX_INT;
882 }
883
884 static unsigned int handle_tx(struct eg20t_port *priv)
885 {
886 struct uart_port *port = &priv->port;
887 struct circ_buf *xmit = &port->state->xmit;
888 int fifo_size;
889 int tx_size;
890 int size;
891 int tx_empty;
892
893 if (!priv->start_tx) {
894 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
895 __func__, jiffies);
896 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
897 priv->tx_empty = 1;
898 return 0;
899 }
900
901 fifo_size = max(priv->fifo_size, 1);
902 tx_empty = 1;
903 if (pop_tx_x(priv, xmit->buf)) {
904 pch_uart_hal_write(priv, xmit->buf, 1);
905 port->icount.tx++;
906 tx_empty = 0;
907 fifo_size--;
908 }
909 size = min(xmit->head - xmit->tail, fifo_size);
910 if (size < 0)
911 size = fifo_size;
912
913 tx_size = pop_tx(priv, size);
914 if (tx_size > 0) {
915 port->icount.tx += tx_size;
916 tx_empty = 0;
917 }
918
919 priv->tx_empty = tx_empty;
920
921 if (tx_empty) {
922 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
923 uart_write_wakeup(port);
924 }
925
926 return PCH_UART_HANDLED_TX_INT;
927 }
928
929 static unsigned int dma_handle_tx(struct eg20t_port *priv)
930 {
931 struct uart_port *port = &priv->port;
932 struct circ_buf *xmit = &port->state->xmit;
933 struct scatterlist *sg;
934 int nent;
935 int fifo_size;
936 int tx_empty;
937 struct dma_async_tx_descriptor *desc;
938 int num;
939 int i;
940 int bytes;
941 int size;
942 int rem;
943
944 if (!priv->start_tx) {
945 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
946 __func__, jiffies);
947 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
948 priv->tx_empty = 1;
949 return 0;
950 }
951
952 if (priv->tx_dma_use) {
953 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
954 __func__, jiffies);
955 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
956 priv->tx_empty = 1;
957 return 0;
958 }
959
960 fifo_size = max(priv->fifo_size, 1);
961 tx_empty = 1;
962 if (pop_tx_x(priv, xmit->buf)) {
963 pch_uart_hal_write(priv, xmit->buf, 1);
964 port->icount.tx++;
965 tx_empty = 0;
966 fifo_size--;
967 }
968
969 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
970 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
971 xmit->tail, UART_XMIT_SIZE));
972 if (!bytes) {
973 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
974 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
975 uart_write_wakeup(port);
976 return 0;
977 }
978
979 if (bytes > fifo_size) {
980 num = bytes / fifo_size + 1;
981 size = fifo_size;
982 rem = bytes % fifo_size;
983 } else {
984 num = 1;
985 size = bytes;
986 rem = bytes;
987 }
988
989 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
990 __func__, num, size, rem);
991
992 priv->tx_dma_use = 1;
993
994 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
995 if (!priv->sg_tx_p) {
996 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
997 return 0;
998 }
999
1000 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1001 sg = priv->sg_tx_p;
1002
1003 for (i = 0; i < num; i++, sg++) {
1004 if (i == (num - 1))
1005 sg_set_page(sg, virt_to_page(xmit->buf),
1006 rem, fifo_size * i);
1007 else
1008 sg_set_page(sg, virt_to_page(xmit->buf),
1009 size, fifo_size * i);
1010 }
1011
1012 sg = priv->sg_tx_p;
1013 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1014 if (!nent) {
1015 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1016 return 0;
1017 }
1018 priv->nent = nent;
1019
1020 for (i = 0; i < nent; i++, sg++) {
1021 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1022 fifo_size * i;
1023 sg_dma_address(sg) = (sg_dma_address(sg) &
1024 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1025 if (i == (nent - 1))
1026 sg_dma_len(sg) = rem;
1027 else
1028 sg_dma_len(sg) = size;
1029 }
1030
1031 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1032 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1033 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1034 if (!desc) {
1035 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1036 __func__);
1037 return 0;
1038 }
1039 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1040 priv->desc_tx = desc;
1041 desc->callback = pch_dma_tx_complete;
1042 desc->callback_param = priv;
1043
1044 desc->tx_submit(desc);
1045
1046 dma_async_issue_pending(priv->chan_tx);
1047
1048 return PCH_UART_HANDLED_TX_INT;
1049 }
1050
1051 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1052 {
1053 struct uart_port *port = &priv->port;
1054 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1055 char *error_msg[5] = {};
1056 int i = 0;
1057
1058 if (lsr & PCH_UART_LSR_ERR)
1059 error_msg[i++] = "Error data in FIFO\n";
1060
1061 if (lsr & UART_LSR_FE) {
1062 port->icount.frame++;
1063 error_msg[i++] = " Framing Error\n";
1064 }
1065
1066 if (lsr & UART_LSR_PE) {
1067 port->icount.parity++;
1068 error_msg[i++] = " Parity Error\n";
1069 }
1070
1071 if (lsr & UART_LSR_OE) {
1072 port->icount.overrun++;
1073 error_msg[i++] = " Overrun Error\n";
1074 }
1075
1076 if (tty == NULL) {
1077 for (i = 0; error_msg[i] != NULL; i++)
1078 dev_err(&priv->pdev->dev, error_msg[i]);
1079 } else {
1080 tty_kref_put(tty);
1081 }
1082 }
1083
1084 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1085 {
1086 struct eg20t_port *priv = dev_id;
1087 unsigned int handled;
1088 u8 lsr;
1089 int ret = 0;
1090 unsigned char iid;
1091 unsigned long flags;
1092 int next = 1;
1093 u8 msr;
1094
1095 spin_lock_irqsave(&priv->lock, flags);
1096 handled = 0;
1097 while (next) {
1098 iid = pch_uart_hal_get_iid(priv);
1099 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1100 break;
1101 switch (iid) {
1102 case PCH_UART_IID_RLS: /* Receiver Line Status */
1103 lsr = pch_uart_hal_get_line_status(priv);
1104 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1105 UART_LSR_PE | UART_LSR_OE)) {
1106 pch_uart_err_ir(priv, lsr);
1107 ret = PCH_UART_HANDLED_RX_ERR_INT;
1108 } else {
1109 ret = PCH_UART_HANDLED_LS_INT;
1110 }
1111 break;
1112 case PCH_UART_IID_RDR: /* Received Data Ready */
1113 if (priv->use_dma) {
1114 pch_uart_hal_disable_interrupt(priv,
1115 PCH_UART_HAL_RX_INT |
1116 PCH_UART_HAL_RX_ERR_INT);
1117 ret = dma_handle_rx(priv);
1118 if (!ret)
1119 pch_uart_hal_enable_interrupt(priv,
1120 PCH_UART_HAL_RX_INT |
1121 PCH_UART_HAL_RX_ERR_INT);
1122 } else {
1123 ret = handle_rx(priv);
1124 }
1125 break;
1126 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1127 (FIFO Timeout) */
1128 ret = handle_rx_to(priv);
1129 break;
1130 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1131 Empty */
1132 if (priv->use_dma)
1133 ret = dma_handle_tx(priv);
1134 else
1135 ret = handle_tx(priv);
1136 break;
1137 case PCH_UART_IID_MS: /* Modem Status */
1138 msr = pch_uart_hal_get_modem(priv);
1139 next = 0; /* MS ir prioirty is the lowest. So, MS ir
1140 means final interrupt */
1141 if ((msr & UART_MSR_ANY_DELTA) == 0)
1142 break;
1143 ret |= PCH_UART_HANDLED_MS_INT;
1144 break;
1145 default: /* Never junp to this label */
1146 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1147 iid, jiffies);
1148 ret = -1;
1149 next = 0;
1150 break;
1151 }
1152 handled |= (unsigned int)ret;
1153 }
1154
1155 spin_unlock_irqrestore(&priv->lock, flags);
1156 return IRQ_RETVAL(handled);
1157 }
1158
1159 /* This function tests whether the transmitter fifo and shifter for the port
1160 described by 'port' is empty. */
1161 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1162 {
1163 struct eg20t_port *priv;
1164
1165 priv = container_of(port, struct eg20t_port, port);
1166 if (priv->tx_empty)
1167 return TIOCSER_TEMT;
1168 else
1169 return 0;
1170 }
1171
1172 /* Returns the current state of modem control inputs. */
1173 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1174 {
1175 struct eg20t_port *priv;
1176 u8 modem;
1177 unsigned int ret = 0;
1178
1179 priv = container_of(port, struct eg20t_port, port);
1180 modem = pch_uart_hal_get_modem(priv);
1181
1182 if (modem & UART_MSR_DCD)
1183 ret |= TIOCM_CAR;
1184
1185 if (modem & UART_MSR_RI)
1186 ret |= TIOCM_RNG;
1187
1188 if (modem & UART_MSR_DSR)
1189 ret |= TIOCM_DSR;
1190
1191 if (modem & UART_MSR_CTS)
1192 ret |= TIOCM_CTS;
1193
1194 return ret;
1195 }
1196
1197 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1198 {
1199 u32 mcr = 0;
1200 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1201
1202 if (mctrl & TIOCM_DTR)
1203 mcr |= UART_MCR_DTR;
1204 if (mctrl & TIOCM_RTS)
1205 mcr |= UART_MCR_RTS;
1206 if (mctrl & TIOCM_LOOP)
1207 mcr |= UART_MCR_LOOP;
1208
1209 if (priv->mcr & UART_MCR_AFE)
1210 mcr |= UART_MCR_AFE;
1211
1212 if (mctrl)
1213 iowrite8(mcr, priv->membase + UART_MCR);
1214 }
1215
1216 static void pch_uart_stop_tx(struct uart_port *port)
1217 {
1218 struct eg20t_port *priv;
1219 priv = container_of(port, struct eg20t_port, port);
1220 priv->start_tx = 0;
1221 priv->tx_dma_use = 0;
1222 }
1223
1224 static void pch_uart_start_tx(struct uart_port *port)
1225 {
1226 struct eg20t_port *priv;
1227
1228 priv = container_of(port, struct eg20t_port, port);
1229
1230 if (priv->use_dma) {
1231 if (priv->tx_dma_use) {
1232 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1233 __func__);
1234 return;
1235 }
1236 }
1237
1238 priv->start_tx = 1;
1239 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1240 }
1241
1242 static void pch_uart_stop_rx(struct uart_port *port)
1243 {
1244 struct eg20t_port *priv;
1245 priv = container_of(port, struct eg20t_port, port);
1246 priv->start_rx = 0;
1247 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1248 PCH_UART_HAL_RX_ERR_INT);
1249 }
1250
1251 /* Enable the modem status interrupts. */
1252 static void pch_uart_enable_ms(struct uart_port *port)
1253 {
1254 struct eg20t_port *priv;
1255 priv = container_of(port, struct eg20t_port, port);
1256 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1257 }
1258
1259 /* Control the transmission of a break signal. */
1260 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1261 {
1262 struct eg20t_port *priv;
1263 unsigned long flags;
1264
1265 priv = container_of(port, struct eg20t_port, port);
1266 spin_lock_irqsave(&priv->lock, flags);
1267 pch_uart_hal_set_break(priv, ctl);
1268 spin_unlock_irqrestore(&priv->lock, flags);
1269 }
1270
1271 /* Grab any interrupt resources and initialise any low level driver state. */
1272 static int pch_uart_startup(struct uart_port *port)
1273 {
1274 struct eg20t_port *priv;
1275 int ret;
1276 int fifo_size;
1277 int trigger_level;
1278
1279 priv = container_of(port, struct eg20t_port, port);
1280 priv->tx_empty = 1;
1281
1282 if (port->uartclk)
1283 priv->uartclk = port->uartclk;
1284 else
1285 port->uartclk = priv->uartclk;
1286
1287 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1288 ret = pch_uart_hal_set_line(priv, default_baud,
1289 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1290 PCH_UART_HAL_STB1);
1291 if (ret)
1292 return ret;
1293
1294 switch (priv->fifo_size) {
1295 case 256:
1296 fifo_size = PCH_UART_HAL_FIFO256;
1297 break;
1298 case 64:
1299 fifo_size = PCH_UART_HAL_FIFO64;
1300 break;
1301 case 16:
1302 fifo_size = PCH_UART_HAL_FIFO16;
1303 break;
1304 case 1:
1305 default:
1306 fifo_size = PCH_UART_HAL_FIFO_DIS;
1307 break;
1308 }
1309
1310 switch (priv->trigger) {
1311 case PCH_UART_HAL_TRIGGER1:
1312 trigger_level = 1;
1313 break;
1314 case PCH_UART_HAL_TRIGGER_L:
1315 trigger_level = priv->fifo_size / 4;
1316 break;
1317 case PCH_UART_HAL_TRIGGER_M:
1318 trigger_level = priv->fifo_size / 2;
1319 break;
1320 case PCH_UART_HAL_TRIGGER_H:
1321 default:
1322 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1323 break;
1324 }
1325
1326 priv->trigger_level = trigger_level;
1327 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1328 fifo_size, priv->trigger);
1329 if (ret < 0)
1330 return ret;
1331
1332 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1333 priv->irq_name, priv);
1334 if (ret < 0)
1335 return ret;
1336
1337 if (priv->use_dma)
1338 pch_request_dma(port);
1339
1340 priv->start_rx = 1;
1341 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1342 PCH_UART_HAL_RX_ERR_INT);
1343 uart_update_timeout(port, CS8, default_baud);
1344
1345 return 0;
1346 }
1347
1348 static void pch_uart_shutdown(struct uart_port *port)
1349 {
1350 struct eg20t_port *priv;
1351 int ret;
1352
1353 priv = container_of(port, struct eg20t_port, port);
1354 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1355 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1356 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1357 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1358 if (ret)
1359 dev_err(priv->port.dev,
1360 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1361
1362 pch_free_dma(port);
1363
1364 free_irq(priv->port.irq, priv);
1365 }
1366
1367 /* Change the port parameters, including word length, parity, stop
1368 *bits. Update read_status_mask and ignore_status_mask to indicate
1369 *the types of events we are interested in receiving. */
1370 static void pch_uart_set_termios(struct uart_port *port,
1371 struct ktermios *termios, struct ktermios *old)
1372 {
1373 int rtn;
1374 unsigned int baud, parity, bits, stb;
1375 struct eg20t_port *priv;
1376 unsigned long flags;
1377
1378 priv = container_of(port, struct eg20t_port, port);
1379 switch (termios->c_cflag & CSIZE) {
1380 case CS5:
1381 bits = PCH_UART_HAL_5BIT;
1382 break;
1383 case CS6:
1384 bits = PCH_UART_HAL_6BIT;
1385 break;
1386 case CS7:
1387 bits = PCH_UART_HAL_7BIT;
1388 break;
1389 default: /* CS8 */
1390 bits = PCH_UART_HAL_8BIT;
1391 break;
1392 }
1393 if (termios->c_cflag & CSTOPB)
1394 stb = PCH_UART_HAL_STB2;
1395 else
1396 stb = PCH_UART_HAL_STB1;
1397
1398 if (termios->c_cflag & PARENB) {
1399 if (termios->c_cflag & PARODD)
1400 parity = PCH_UART_HAL_PARITY_ODD;
1401 else
1402 parity = PCH_UART_HAL_PARITY_EVEN;
1403
1404 } else
1405 parity = PCH_UART_HAL_PARITY_NONE;
1406
1407 /* Only UART0 has auto hardware flow function */
1408 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1409 priv->mcr |= UART_MCR_AFE;
1410 else
1411 priv->mcr &= ~UART_MCR_AFE;
1412
1413 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1414
1415 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1416
1417 spin_lock_irqsave(&priv->lock, flags);
1418 spin_lock(&port->lock);
1419
1420 uart_update_timeout(port, termios->c_cflag, baud);
1421 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1422 if (rtn)
1423 goto out;
1424
1425 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1426 /* Don't rewrite B0 */
1427 if (tty_termios_baud_rate(termios))
1428 tty_termios_encode_baud_rate(termios, baud, baud);
1429
1430 out:
1431 spin_unlock(&port->lock);
1432 spin_unlock_irqrestore(&priv->lock, flags);
1433 }
1434
1435 static const char *pch_uart_type(struct uart_port *port)
1436 {
1437 return KBUILD_MODNAME;
1438 }
1439
1440 static void pch_uart_release_port(struct uart_port *port)
1441 {
1442 struct eg20t_port *priv;
1443
1444 priv = container_of(port, struct eg20t_port, port);
1445 pci_iounmap(priv->pdev, priv->membase);
1446 pci_release_regions(priv->pdev);
1447 }
1448
1449 static int pch_uart_request_port(struct uart_port *port)
1450 {
1451 struct eg20t_port *priv;
1452 int ret;
1453 void __iomem *membase;
1454
1455 priv = container_of(port, struct eg20t_port, port);
1456 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1457 if (ret < 0)
1458 return -EBUSY;
1459
1460 membase = pci_iomap(priv->pdev, 1, 0);
1461 if (!membase) {
1462 pci_release_regions(priv->pdev);
1463 return -EBUSY;
1464 }
1465 priv->membase = port->membase = membase;
1466
1467 return 0;
1468 }
1469
1470 static void pch_uart_config_port(struct uart_port *port, int type)
1471 {
1472 struct eg20t_port *priv;
1473
1474 priv = container_of(port, struct eg20t_port, port);
1475 if (type & UART_CONFIG_TYPE) {
1476 port->type = priv->port_type;
1477 pch_uart_request_port(port);
1478 }
1479 }
1480
1481 static int pch_uart_verify_port(struct uart_port *port,
1482 struct serial_struct *serinfo)
1483 {
1484 struct eg20t_port *priv;
1485
1486 priv = container_of(port, struct eg20t_port, port);
1487 if (serinfo->flags & UPF_LOW_LATENCY) {
1488 dev_info(priv->port.dev,
1489 "PCH UART : Use PIO Mode (without DMA)\n");
1490 priv->use_dma = 0;
1491 serinfo->flags &= ~UPF_LOW_LATENCY;
1492 } else {
1493 #ifndef CONFIG_PCH_DMA
1494 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1495 __func__);
1496 return -EOPNOTSUPP;
1497 #endif
1498 if (!priv->use_dma) {
1499 pch_request_dma(port);
1500 if (priv->chan_rx)
1501 priv->use_dma = 1;
1502 }
1503 dev_info(priv->port.dev, "PCH UART: %s\n",
1504 priv->use_dma ?
1505 "Use DMA Mode" : "No DMA");
1506 }
1507
1508 return 0;
1509 }
1510
1511 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1512 /*
1513 * Wait for transmitter & holding register to empty
1514 */
1515 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1516 {
1517 unsigned int status, tmout = 10000;
1518
1519 /* Wait up to 10ms for the character(s) to be sent. */
1520 for (;;) {
1521 status = ioread8(up->membase + UART_LSR);
1522
1523 if ((status & bits) == bits)
1524 break;
1525 if (--tmout == 0)
1526 break;
1527 udelay(1);
1528 }
1529
1530 /* Wait up to 1s for flow control if necessary */
1531 if (up->port.flags & UPF_CONS_FLOW) {
1532 unsigned int tmout;
1533 for (tmout = 1000000; tmout; tmout--) {
1534 unsigned int msr = ioread8(up->membase + UART_MSR);
1535 if (msr & UART_MSR_CTS)
1536 break;
1537 udelay(1);
1538 touch_nmi_watchdog();
1539 }
1540 }
1541 }
1542 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1543
1544 #ifdef CONFIG_CONSOLE_POLL
1545 /*
1546 * Console polling routines for communicate via uart while
1547 * in an interrupt or debug context.
1548 */
1549 static int pch_uart_get_poll_char(struct uart_port *port)
1550 {
1551 struct eg20t_port *priv =
1552 container_of(port, struct eg20t_port, port);
1553 u8 lsr = ioread8(priv->membase + UART_LSR);
1554
1555 if (!(lsr & UART_LSR_DR))
1556 return NO_POLL_CHAR;
1557
1558 return ioread8(priv->membase + PCH_UART_RBR);
1559 }
1560
1561
1562 static void pch_uart_put_poll_char(struct uart_port *port,
1563 unsigned char c)
1564 {
1565 unsigned int ier;
1566 struct eg20t_port *priv =
1567 container_of(port, struct eg20t_port, port);
1568
1569 /*
1570 * First save the IER then disable the interrupts
1571 */
1572 ier = ioread8(priv->membase + UART_IER);
1573 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1574
1575 wait_for_xmitr(priv, UART_LSR_THRE);
1576 /*
1577 * Send the character out.
1578 */
1579 iowrite8(c, priv->membase + PCH_UART_THR);
1580
1581 /*
1582 * Finally, wait for transmitter to become empty
1583 * and restore the IER
1584 */
1585 wait_for_xmitr(priv, BOTH_EMPTY);
1586 iowrite8(ier, priv->membase + UART_IER);
1587 }
1588 #endif /* CONFIG_CONSOLE_POLL */
1589
1590 static const struct uart_ops pch_uart_ops = {
1591 .tx_empty = pch_uart_tx_empty,
1592 .set_mctrl = pch_uart_set_mctrl,
1593 .get_mctrl = pch_uart_get_mctrl,
1594 .stop_tx = pch_uart_stop_tx,
1595 .start_tx = pch_uart_start_tx,
1596 .stop_rx = pch_uart_stop_rx,
1597 .enable_ms = pch_uart_enable_ms,
1598 .break_ctl = pch_uart_break_ctl,
1599 .startup = pch_uart_startup,
1600 .shutdown = pch_uart_shutdown,
1601 .set_termios = pch_uart_set_termios,
1602 /* .pm = pch_uart_pm, Not supported yet */
1603 .type = pch_uart_type,
1604 .release_port = pch_uart_release_port,
1605 .request_port = pch_uart_request_port,
1606 .config_port = pch_uart_config_port,
1607 .verify_port = pch_uart_verify_port,
1608 #ifdef CONFIG_CONSOLE_POLL
1609 .poll_get_char = pch_uart_get_poll_char,
1610 .poll_put_char = pch_uart_put_poll_char,
1611 #endif
1612 };
1613
1614 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1615
1616 static void pch_console_putchar(struct uart_port *port, int ch)
1617 {
1618 struct eg20t_port *priv =
1619 container_of(port, struct eg20t_port, port);
1620
1621 wait_for_xmitr(priv, UART_LSR_THRE);
1622 iowrite8(ch, priv->membase + PCH_UART_THR);
1623 }
1624
1625 /*
1626 * Print a string to the serial port trying not to disturb
1627 * any possible real use of the port...
1628 *
1629 * The console_lock must be held when we get here.
1630 */
1631 static void
1632 pch_console_write(struct console *co, const char *s, unsigned int count)
1633 {
1634 struct eg20t_port *priv;
1635 unsigned long flags;
1636 int priv_locked = 1;
1637 int port_locked = 1;
1638 u8 ier;
1639
1640 priv = pch_uart_ports[co->index];
1641
1642 touch_nmi_watchdog();
1643
1644 local_irq_save(flags);
1645 if (priv->port.sysrq) {
1646 /* call to uart_handle_sysrq_char already took the priv lock */
1647 priv_locked = 0;
1648 /* serial8250_handle_port() already took the port lock */
1649 port_locked = 0;
1650 } else if (oops_in_progress) {
1651 priv_locked = spin_trylock(&priv->lock);
1652 port_locked = spin_trylock(&priv->port.lock);
1653 } else {
1654 spin_lock(&priv->lock);
1655 spin_lock(&priv->port.lock);
1656 }
1657
1658 /*
1659 * First save the IER then disable the interrupts
1660 */
1661 ier = ioread8(priv->membase + UART_IER);
1662
1663 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1664
1665 uart_console_write(&priv->port, s, count, pch_console_putchar);
1666
1667 /*
1668 * Finally, wait for transmitter to become empty
1669 * and restore the IER
1670 */
1671 wait_for_xmitr(priv, BOTH_EMPTY);
1672 iowrite8(ier, priv->membase + UART_IER);
1673
1674 if (port_locked)
1675 spin_unlock(&priv->port.lock);
1676 if (priv_locked)
1677 spin_unlock(&priv->lock);
1678 local_irq_restore(flags);
1679 }
1680
1681 static int __init pch_console_setup(struct console *co, char *options)
1682 {
1683 struct uart_port *port;
1684 int baud = default_baud;
1685 int bits = 8;
1686 int parity = 'n';
1687 int flow = 'n';
1688
1689 /*
1690 * Check whether an invalid uart number has been specified, and
1691 * if so, search for the first available port that does have
1692 * console support.
1693 */
1694 if (co->index >= PCH_UART_NR)
1695 co->index = 0;
1696 port = &pch_uart_ports[co->index]->port;
1697
1698 if (!port || (!port->iobase && !port->membase))
1699 return -ENODEV;
1700
1701 port->uartclk = pch_uart_get_uartclk();
1702
1703 if (options)
1704 uart_parse_options(options, &baud, &parity, &bits, &flow);
1705
1706 return uart_set_options(port, co, baud, parity, bits, flow);
1707 }
1708
1709 static struct uart_driver pch_uart_driver;
1710
1711 static struct console pch_console = {
1712 .name = PCH_UART_DRIVER_DEVICE,
1713 .write = pch_console_write,
1714 .device = uart_console_device,
1715 .setup = pch_console_setup,
1716 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1717 .index = -1,
1718 .data = &pch_uart_driver,
1719 };
1720
1721 #define PCH_CONSOLE (&pch_console)
1722 #else
1723 #define PCH_CONSOLE NULL
1724 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1725
1726 static struct uart_driver pch_uart_driver = {
1727 .owner = THIS_MODULE,
1728 .driver_name = KBUILD_MODNAME,
1729 .dev_name = PCH_UART_DRIVER_DEVICE,
1730 .major = 0,
1731 .minor = 0,
1732 .nr = PCH_UART_NR,
1733 .cons = PCH_CONSOLE,
1734 };
1735
1736 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1737 const struct pci_device_id *id)
1738 {
1739 struct eg20t_port *priv;
1740 int ret;
1741 unsigned int iobase;
1742 unsigned int mapbase;
1743 unsigned char *rxbuf;
1744 int fifosize;
1745 int port_type;
1746 struct pch_uart_driver_data *board;
1747 #ifdef CONFIG_DEBUG_FS
1748 char name[32]; /* for debugfs file name */
1749 #endif
1750
1751 board = &drv_dat[id->driver_data];
1752 port_type = board->port_type;
1753
1754 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1755 if (priv == NULL)
1756 goto init_port_alloc_err;
1757
1758 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1759 if (!rxbuf)
1760 goto init_port_free_txbuf;
1761
1762 switch (port_type) {
1763 case PORT_PCH_8LINE:
1764 fifosize = 256; /* EG20T/ML7213: UART0 */
1765 break;
1766 case PORT_PCH_2LINE:
1767 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1768 break;
1769 default:
1770 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1771 goto init_port_hal_free;
1772 }
1773
1774 pci_enable_msi(pdev);
1775 pci_set_master(pdev);
1776
1777 spin_lock_init(&priv->lock);
1778
1779 iobase = pci_resource_start(pdev, 0);
1780 mapbase = pci_resource_start(pdev, 1);
1781 priv->mapbase = mapbase;
1782 priv->iobase = iobase;
1783 priv->pdev = pdev;
1784 priv->tx_empty = 1;
1785 priv->rxbuf.buf = rxbuf;
1786 priv->rxbuf.size = PAGE_SIZE;
1787
1788 priv->fifo_size = fifosize;
1789 priv->uartclk = pch_uart_get_uartclk();
1790 priv->port_type = port_type;
1791 priv->port.dev = &pdev->dev;
1792 priv->port.iobase = iobase;
1793 priv->port.membase = NULL;
1794 priv->port.mapbase = mapbase;
1795 priv->port.irq = pdev->irq;
1796 priv->port.iotype = UPIO_PORT;
1797 priv->port.ops = &pch_uart_ops;
1798 priv->port.flags = UPF_BOOT_AUTOCONF;
1799 priv->port.fifosize = fifosize;
1800 priv->port.line = board->line_no;
1801 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1802
1803 snprintf(priv->irq_name, IRQ_NAME_SIZE,
1804 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1805 priv->port.line);
1806
1807 spin_lock_init(&priv->port.lock);
1808
1809 pci_set_drvdata(pdev, priv);
1810 priv->trigger_level = 1;
1811 priv->fcr = 0;
1812
1813 if (pdev->dev.of_node)
1814 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1815 , &user_uartclk);
1816
1817 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1818 pch_uart_ports[board->line_no] = priv;
1819 #endif
1820 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1821 if (ret < 0)
1822 goto init_port_hal_free;
1823
1824 #ifdef CONFIG_DEBUG_FS
1825 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1826 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1827 NULL, priv, &port_regs_ops);
1828 #endif
1829
1830 return priv;
1831
1832 init_port_hal_free:
1833 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1834 pch_uart_ports[board->line_no] = NULL;
1835 #endif
1836 free_page((unsigned long)rxbuf);
1837 init_port_free_txbuf:
1838 kfree(priv);
1839 init_port_alloc_err:
1840
1841 return NULL;
1842 }
1843
1844 static void pch_uart_exit_port(struct eg20t_port *priv)
1845 {
1846
1847 #ifdef CONFIG_DEBUG_FS
1848 debugfs_remove(priv->debugfs);
1849 #endif
1850 uart_remove_one_port(&pch_uart_driver, &priv->port);
1851 free_page((unsigned long)priv->rxbuf.buf);
1852 }
1853
1854 static void pch_uart_pci_remove(struct pci_dev *pdev)
1855 {
1856 struct eg20t_port *priv = pci_get_drvdata(pdev);
1857
1858 pci_disable_msi(pdev);
1859
1860 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1861 pch_uart_ports[priv->port.line] = NULL;
1862 #endif
1863 pch_uart_exit_port(priv);
1864 pci_disable_device(pdev);
1865 kfree(priv);
1866 return;
1867 }
1868 #ifdef CONFIG_PM
1869 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1870 {
1871 struct eg20t_port *priv = pci_get_drvdata(pdev);
1872
1873 uart_suspend_port(&pch_uart_driver, &priv->port);
1874
1875 pci_save_state(pdev);
1876 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1877 return 0;
1878 }
1879
1880 static int pch_uart_pci_resume(struct pci_dev *pdev)
1881 {
1882 struct eg20t_port *priv = pci_get_drvdata(pdev);
1883 int ret;
1884
1885 pci_set_power_state(pdev, PCI_D0);
1886 pci_restore_state(pdev);
1887
1888 ret = pci_enable_device(pdev);
1889 if (ret) {
1890 dev_err(&pdev->dev,
1891 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1892 return ret;
1893 }
1894
1895 uart_resume_port(&pch_uart_driver, &priv->port);
1896
1897 return 0;
1898 }
1899 #else
1900 #define pch_uart_pci_suspend NULL
1901 #define pch_uart_pci_resume NULL
1902 #endif
1903
1904 static const struct pci_device_id pch_uart_pci_id[] = {
1905 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1906 .driver_data = pch_et20t_uart0},
1907 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1908 .driver_data = pch_et20t_uart1},
1909 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1910 .driver_data = pch_et20t_uart2},
1911 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1912 .driver_data = pch_et20t_uart3},
1913 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1914 .driver_data = pch_ml7213_uart0},
1915 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1916 .driver_data = pch_ml7213_uart1},
1917 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1918 .driver_data = pch_ml7213_uart2},
1919 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1920 .driver_data = pch_ml7223_uart0},
1921 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1922 .driver_data = pch_ml7223_uart1},
1923 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1924 .driver_data = pch_ml7831_uart0},
1925 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1926 .driver_data = pch_ml7831_uart1},
1927 {0,},
1928 };
1929
1930 static int pch_uart_pci_probe(struct pci_dev *pdev,
1931 const struct pci_device_id *id)
1932 {
1933 int ret;
1934 struct eg20t_port *priv;
1935
1936 ret = pci_enable_device(pdev);
1937 if (ret < 0)
1938 goto probe_error;
1939
1940 priv = pch_uart_init_port(pdev, id);
1941 if (!priv) {
1942 ret = -EBUSY;
1943 goto probe_disable_device;
1944 }
1945 pci_set_drvdata(pdev, priv);
1946
1947 return ret;
1948
1949 probe_disable_device:
1950 pci_disable_msi(pdev);
1951 pci_disable_device(pdev);
1952 probe_error:
1953 return ret;
1954 }
1955
1956 static struct pci_driver pch_uart_pci_driver = {
1957 .name = "pch_uart",
1958 .id_table = pch_uart_pci_id,
1959 .probe = pch_uart_pci_probe,
1960 .remove = pch_uart_pci_remove,
1961 .suspend = pch_uart_pci_suspend,
1962 .resume = pch_uart_pci_resume,
1963 };
1964
1965 static int __init pch_uart_module_init(void)
1966 {
1967 int ret;
1968
1969 /* register as UART driver */
1970 ret = uart_register_driver(&pch_uart_driver);
1971 if (ret < 0)
1972 return ret;
1973
1974 /* register as PCI driver */
1975 ret = pci_register_driver(&pch_uart_pci_driver);
1976 if (ret < 0)
1977 uart_unregister_driver(&pch_uart_driver);
1978
1979 return ret;
1980 }
1981 module_init(pch_uart_module_init);
1982
1983 static void __exit pch_uart_module_exit(void)
1984 {
1985 pci_unregister_driver(&pch_uart_pci_driver);
1986 uart_unregister_driver(&pch_uart_driver);
1987 }
1988 module_exit(pch_uart_module_exit);
1989
1990 MODULE_LICENSE("GPL v2");
1991 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1992 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1993
1994 module_param(default_baud, uint, S_IRUGO);
1995 MODULE_PARM_DESC(default_baud,
1996 "Default BAUD for initial driver state and console (default 9600)");
1997 module_param(user_uartclk, uint, S_IRUGO);
1998 MODULE_PARM_DESC(user_uartclk,
1999 "Override UART default or board specific UART clock");
CRIS linux kernel tree