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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / drivers / tty / serial / samsung.c
blobf9fecc5ed0cee82656e978f77938d5af7ff1f70a
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver core for Samsung SoC onboard UARTs.
4 *
5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
7 */
8
9 /* Hote on 2410 error handling
10 *
11 * The s3c2410 manual has a love/hate affair with the contents of the
12 * UERSTAT register in the UART blocks, and keeps marking some of the
13 * error bits as reserved. Having checked with the s3c2410x01,
14 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
15 * feature from the latter versions of the manual.
16 *
17 * If it becomes aparrent that latter versions of the 2410 remove these
18 * bits, then action will have to be taken to differentiate the versions
19 * and change the policy on BREAK
20 *
21 * BJD, 04-Nov-2004
22 */
23
24 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25 #define SUPPORT_SYSRQ
26 #endif
27
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/module.h>
32 #include <linux/ioport.h>
33 #include <linux/io.h>
34 #include <linux/platform_device.h>
35 #include <linux/init.h>
36 #include <linux/sysrq.h>
37 #include <linux/console.h>
38 #include <linux/tty.h>
39 #include <linux/tty_flip.h>
40 #include <linux/serial_core.h>
41 #include <linux/serial.h>
42 #include <linux/serial_s3c.h>
43 #include <linux/delay.h>
44 #include <linux/clk.h>
45 #include <linux/cpufreq.h>
46 #include <linux/of.h>
47
48 #include <asm/irq.h>
49
50 #include "samsung.h"
51
52 #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
53 !defined(MODULE)
54
55 extern void printascii(const char *);
56
57 __printf(1, 2)
58 static void dbg(const char *fmt, ...)
59 {
60 va_list va;
61 char buff[256];
62
63 va_start(va, fmt);
64 vscnprintf(buff, sizeof(buff), fmt, va);
65 va_end(va);
66
67 printascii(buff);
68 }
69
70 #else
71 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
72 #endif
73
74 /* UART name and device definitions */
75
76 #define S3C24XX_SERIAL_NAME "ttySAC"
77 #define S3C24XX_SERIAL_MAJOR 204
78 #define S3C24XX_SERIAL_MINOR 64
79
80 #define S3C24XX_TX_PIO 1
81 #define S3C24XX_TX_DMA 2
82 #define S3C24XX_RX_PIO 1
83 #define S3C24XX_RX_DMA 2
84 /* macros to change one thing to another */
85
86 #define tx_enabled(port) ((port)->unused[0])
87 #define rx_enabled(port) ((port)->unused[1])
88
89 /* flag to ignore all characters coming in */
90 #define RXSTAT_DUMMY_READ (0x10000000)
91
92 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
93 {
94 return container_of(port, struct s3c24xx_uart_port, port);
95 }
96
97 /* translate a port to the device name */
98
99 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
100 {
101 return to_platform_device(port->dev)->name;
102 }
103
104 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
105 {
106 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
107 }
108
109 /*
110 * s3c64xx and later SoC's include the interrupt mask and status registers in
111 * the controller itself, unlike the s3c24xx SoC's which have these registers
112 * in the interrupt controller. Check if the port type is s3c64xx or higher.
113 */
114 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
115 {
116 return to_ourport(port)->info->type == PORT_S3C6400;
117 }
118
119 static void s3c24xx_serial_rx_enable(struct uart_port *port)
120 {
121 unsigned long flags;
122 unsigned int ucon, ufcon;
123 int count = 10000;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 while (--count && !s3c24xx_serial_txempty_nofifo(port))
128 udelay(100);
129
130 ufcon = rd_regl(port, S3C2410_UFCON);
131 ufcon |= S3C2410_UFCON_RESETRX;
132 wr_regl(port, S3C2410_UFCON, ufcon);
133
134 ucon = rd_regl(port, S3C2410_UCON);
135 ucon |= S3C2410_UCON_RXIRQMODE;
136 wr_regl(port, S3C2410_UCON, ucon);
137
138 rx_enabled(port) = 1;
139 spin_unlock_irqrestore(&port->lock, flags);
140 }
141
142 static void s3c24xx_serial_rx_disable(struct uart_port *port)
143 {
144 unsigned long flags;
145 unsigned int ucon;
146
147 spin_lock_irqsave(&port->lock, flags);
148
149 ucon = rd_regl(port, S3C2410_UCON);
150 ucon &= ~S3C2410_UCON_RXIRQMODE;
151 wr_regl(port, S3C2410_UCON, ucon);
152
153 rx_enabled(port) = 0;
154 spin_unlock_irqrestore(&port->lock, flags);
155 }
156
157 static void s3c24xx_serial_stop_tx(struct uart_port *port)
158 {
159 struct s3c24xx_uart_port *ourport = to_ourport(port);
160 struct s3c24xx_uart_dma *dma = ourport->dma;
161 struct circ_buf *xmit = &port->state->xmit;
162 struct dma_tx_state state;
163 int count;
164
165 if (!tx_enabled(port))
166 return;
167
168 if (s3c24xx_serial_has_interrupt_mask(port))
169 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
170 else
171 disable_irq_nosync(ourport->tx_irq);
172
173 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
174 dmaengine_pause(dma->tx_chan);
175 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
176 dmaengine_terminate_all(dma->tx_chan);
177 dma_sync_single_for_cpu(ourport->port.dev,
178 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
179 async_tx_ack(dma->tx_desc);
180 count = dma->tx_bytes_requested - state.residue;
181 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
182 port->icount.tx += count;
183 }
184
185 tx_enabled(port) = 0;
186 ourport->tx_in_progress = 0;
187
188 if (port->flags & UPF_CONS_FLOW)
189 s3c24xx_serial_rx_enable(port);
190
191 ourport->tx_mode = 0;
192 }
193
194 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
195
196 static void s3c24xx_serial_tx_dma_complete(void *args)
197 {
198 struct s3c24xx_uart_port *ourport = args;
199 struct uart_port *port = &ourport->port;
200 struct circ_buf *xmit = &port->state->xmit;
201 struct s3c24xx_uart_dma *dma = ourport->dma;
202 struct dma_tx_state state;
203 unsigned long flags;
204 int count;
205
206
207 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
208 count = dma->tx_bytes_requested - state.residue;
209 async_tx_ack(dma->tx_desc);
210
211 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
212 dma->tx_size, DMA_TO_DEVICE);
213
214 spin_lock_irqsave(&port->lock, flags);
215
216 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
217 port->icount.tx += count;
218 ourport->tx_in_progress = 0;
219
220 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
221 uart_write_wakeup(port);
222
223 s3c24xx_serial_start_next_tx(ourport);
224 spin_unlock_irqrestore(&port->lock, flags);
225 }
226
227 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
228 {
229 struct uart_port *port = &ourport->port;
230 u32 ucon;
231
232 /* Mask Tx interrupt */
233 if (s3c24xx_serial_has_interrupt_mask(port))
234 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
235 else
236 disable_irq_nosync(ourport->tx_irq);
237
238 /* Enable tx dma mode */
239 ucon = rd_regl(port, S3C2410_UCON);
240 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
241 ucon |= (dma_get_cache_alignment() >= 16) ?
242 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
243 ucon |= S3C64XX_UCON_TXMODE_DMA;
244 wr_regl(port, S3C2410_UCON, ucon);
245
246 ourport->tx_mode = S3C24XX_TX_DMA;
247 }
248
249 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
250 {
251 struct uart_port *port = &ourport->port;
252 u32 ucon, ufcon;
253
254 /* Set ufcon txtrig */
255 ourport->tx_in_progress = S3C24XX_TX_PIO;
256 ufcon = rd_regl(port, S3C2410_UFCON);
257 wr_regl(port, S3C2410_UFCON, ufcon);
258
259 /* Enable tx pio mode */
260 ucon = rd_regl(port, S3C2410_UCON);
261 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
262 ucon |= S3C64XX_UCON_TXMODE_CPU;
263 wr_regl(port, S3C2410_UCON, ucon);
264
265 /* Unmask Tx interrupt */
266 if (s3c24xx_serial_has_interrupt_mask(port))
267 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
268 S3C64XX_UINTM);
269 else
270 enable_irq(ourport->tx_irq);
271
272 ourport->tx_mode = S3C24XX_TX_PIO;
273 }
274
275 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
276 {
277 if (ourport->tx_mode != S3C24XX_TX_PIO)
278 enable_tx_pio(ourport);
279 }
280
281 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
282 unsigned int count)
283 {
284 struct uart_port *port = &ourport->port;
285 struct circ_buf *xmit = &port->state->xmit;
286 struct s3c24xx_uart_dma *dma = ourport->dma;
287
288
289 if (ourport->tx_mode != S3C24XX_TX_DMA)
290 enable_tx_dma(ourport);
291
292 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
293 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
294
295 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
296 dma->tx_size, DMA_TO_DEVICE);
297
298 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
299 dma->tx_transfer_addr, dma->tx_size,
300 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
301 if (!dma->tx_desc) {
302 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
303 return -EIO;
304 }
305
306 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
307 dma->tx_desc->callback_param = ourport;
308 dma->tx_bytes_requested = dma->tx_size;
309
310 ourport->tx_in_progress = S3C24XX_TX_DMA;
311 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
312 dma_async_issue_pending(dma->tx_chan);
313 return 0;
314 }
315
316 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
317 {
318 struct uart_port *port = &ourport->port;
319 struct circ_buf *xmit = &port->state->xmit;
320 unsigned long count;
321
322 /* Get data size up to the end of buffer */
323 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
324
325 if (!count) {
326 s3c24xx_serial_stop_tx(port);
327 return;
328 }
329
330 if (!ourport->dma || !ourport->dma->tx_chan ||
331 count < ourport->min_dma_size ||
332 xmit->tail & (dma_get_cache_alignment() - 1))
333 s3c24xx_serial_start_tx_pio(ourport);
334 else
335 s3c24xx_serial_start_tx_dma(ourport, count);
336 }
337
338 static void s3c24xx_serial_start_tx(struct uart_port *port)
339 {
340 struct s3c24xx_uart_port *ourport = to_ourport(port);
341 struct circ_buf *xmit = &port->state->xmit;
342
343 if (!tx_enabled(port)) {
344 if (port->flags & UPF_CONS_FLOW)
345 s3c24xx_serial_rx_disable(port);
346
347 tx_enabled(port) = 1;
348 if (!ourport->dma || !ourport->dma->tx_chan)
349 s3c24xx_serial_start_tx_pio(ourport);
350 }
351
352 if (ourport->dma && ourport->dma->tx_chan) {
353 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
354 s3c24xx_serial_start_next_tx(ourport);
355 }
356 }
357
358 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
359 struct tty_port *tty, int count)
360 {
361 struct s3c24xx_uart_dma *dma = ourport->dma;
362 int copied;
363
364 if (!count)
365 return;
366
367 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
368 dma->rx_size, DMA_FROM_DEVICE);
369
370 ourport->port.icount.rx += count;
371 if (!tty) {
372 dev_err(ourport->port.dev, "No tty port\n");
373 return;
374 }
375 copied = tty_insert_flip_string(tty,
376 ((unsigned char *)(ourport->dma->rx_buf)), count);
377 if (copied != count) {
378 WARN_ON(1);
379 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
380 }
381 }
382
383 static void s3c24xx_serial_stop_rx(struct uart_port *port)
384 {
385 struct s3c24xx_uart_port *ourport = to_ourport(port);
386 struct s3c24xx_uart_dma *dma = ourport->dma;
387 struct tty_port *t = &port->state->port;
388 struct dma_tx_state state;
389 enum dma_status dma_status;
390 unsigned int received;
391
392 if (rx_enabled(port)) {
393 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
394 if (s3c24xx_serial_has_interrupt_mask(port))
395 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
396 S3C64XX_UINTM);
397 else
398 disable_irq_nosync(ourport->rx_irq);
399 rx_enabled(port) = 0;
400 }
401 if (dma && dma->rx_chan) {
402 dmaengine_pause(dma->tx_chan);
403 dma_status = dmaengine_tx_status(dma->rx_chan,
404 dma->rx_cookie, &state);
405 if (dma_status == DMA_IN_PROGRESS ||
406 dma_status == DMA_PAUSED) {
407 received = dma->rx_bytes_requested - state.residue;
408 dmaengine_terminate_all(dma->rx_chan);
409 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
410 }
411 }
412 }
413
414 static inline struct s3c24xx_uart_info
415 *s3c24xx_port_to_info(struct uart_port *port)
416 {
417 return to_ourport(port)->info;
418 }
419
420 static inline struct s3c2410_uartcfg
421 *s3c24xx_port_to_cfg(struct uart_port *port)
422 {
423 struct s3c24xx_uart_port *ourport;
424
425 if (port->dev == NULL)
426 return NULL;
427
428 ourport = container_of(port, struct s3c24xx_uart_port, port);
429 return ourport->cfg;
430 }
431
432 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
433 unsigned long ufstat)
434 {
435 struct s3c24xx_uart_info *info = ourport->info;
436
437 if (ufstat & info->rx_fifofull)
438 return ourport->port.fifosize;
439
440 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
441 }
442
443 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
444 static void s3c24xx_serial_rx_dma_complete(void *args)
445 {
446 struct s3c24xx_uart_port *ourport = args;
447 struct uart_port *port = &ourport->port;
448
449 struct s3c24xx_uart_dma *dma = ourport->dma;
450 struct tty_port *t = &port->state->port;
451 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
452
453 struct dma_tx_state state;
454 unsigned long flags;
455 int received;
456
457 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
458 received = dma->rx_bytes_requested - state.residue;
459 async_tx_ack(dma->rx_desc);
460
461 spin_lock_irqsave(&port->lock, flags);
462
463 if (received)
464 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
465
466 if (tty) {
467 tty_flip_buffer_push(t);
468 tty_kref_put(tty);
469 }
470
471 s3c64xx_start_rx_dma(ourport);
472
473 spin_unlock_irqrestore(&port->lock, flags);
474 }
475
476 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
477 {
478 struct s3c24xx_uart_dma *dma = ourport->dma;
479
480 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
481 dma->rx_size, DMA_FROM_DEVICE);
482
483 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
484 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
485 DMA_PREP_INTERRUPT);
486 if (!dma->rx_desc) {
487 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
488 return;
489 }
490
491 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
492 dma->rx_desc->callback_param = ourport;
493 dma->rx_bytes_requested = dma->rx_size;
494
495 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
496 dma_async_issue_pending(dma->rx_chan);
497 }
498
499 /* ? - where has parity gone?? */
500 #define S3C2410_UERSTAT_PARITY (0x1000)
501
502 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
503 {
504 struct uart_port *port = &ourport->port;
505 unsigned int ucon;
506
507 /* set Rx mode to DMA mode */
508 ucon = rd_regl(port, S3C2410_UCON);
509 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
510 S3C64XX_UCON_TIMEOUT_MASK |
511 S3C64XX_UCON_EMPTYINT_EN |
512 S3C64XX_UCON_DMASUS_EN |
513 S3C64XX_UCON_TIMEOUT_EN |
514 S3C64XX_UCON_RXMODE_MASK);
515 ucon |= S3C64XX_UCON_RXBURST_16 |
516 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
517 S3C64XX_UCON_EMPTYINT_EN |
518 S3C64XX_UCON_TIMEOUT_EN |
519 S3C64XX_UCON_RXMODE_DMA;
520 wr_regl(port, S3C2410_UCON, ucon);
521
522 ourport->rx_mode = S3C24XX_RX_DMA;
523 }
524
525 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
526 {
527 struct uart_port *port = &ourport->port;
528 unsigned int ucon;
529
530 /* set Rx mode to DMA mode */
531 ucon = rd_regl(port, S3C2410_UCON);
532 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
533 S3C64XX_UCON_EMPTYINT_EN |
534 S3C64XX_UCON_DMASUS_EN |
535 S3C64XX_UCON_TIMEOUT_EN |
536 S3C64XX_UCON_RXMODE_MASK);
537 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
538 S3C64XX_UCON_TIMEOUT_EN |
539 S3C64XX_UCON_RXMODE_CPU;
540 wr_regl(port, S3C2410_UCON, ucon);
541
542 ourport->rx_mode = S3C24XX_RX_PIO;
543 }
544
545 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
546
547 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
548 {
549 unsigned int utrstat, ufstat, received;
550 struct s3c24xx_uart_port *ourport = dev_id;
551 struct uart_port *port = &ourport->port;
552 struct s3c24xx_uart_dma *dma = ourport->dma;
553 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
554 struct tty_port *t = &port->state->port;
555 unsigned long flags;
556 struct dma_tx_state state;
557
558 utrstat = rd_regl(port, S3C2410_UTRSTAT);
559 ufstat = rd_regl(port, S3C2410_UFSTAT);
560
561 spin_lock_irqsave(&port->lock, flags);
562
563 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
564 s3c64xx_start_rx_dma(ourport);
565 if (ourport->rx_mode == S3C24XX_RX_PIO)
566 enable_rx_dma(ourport);
567 goto finish;
568 }
569
570 if (ourport->rx_mode == S3C24XX_RX_DMA) {
571 dmaengine_pause(dma->rx_chan);
572 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
573 dmaengine_terminate_all(dma->rx_chan);
574 received = dma->rx_bytes_requested - state.residue;
575 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
576
577 enable_rx_pio(ourport);
578 }
579
580 s3c24xx_serial_rx_drain_fifo(ourport);
581
582 if (tty) {
583 tty_flip_buffer_push(t);
584 tty_kref_put(tty);
585 }
586
587 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
588
589 finish:
590 spin_unlock_irqrestore(&port->lock, flags);
591
592 return IRQ_HANDLED;
593 }
594
595 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
596 {
597 struct uart_port *port = &ourport->port;
598 unsigned int ufcon, ch, flag, ufstat, uerstat;
599 unsigned int fifocnt = 0;
600 int max_count = port->fifosize;
601
602 while (max_count-- > 0) {
603 /*
604 * Receive all characters known to be in FIFO
605 * before reading FIFO level again
606 */
607 if (fifocnt == 0) {
608 ufstat = rd_regl(port, S3C2410_UFSTAT);
609 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
610 if (fifocnt == 0)
611 break;
612 }
613 fifocnt--;
614
615 uerstat = rd_regl(port, S3C2410_UERSTAT);
616 ch = rd_regb(port, S3C2410_URXH);
617
618 if (port->flags & UPF_CONS_FLOW) {
619 int txe = s3c24xx_serial_txempty_nofifo(port);
620
621 if (rx_enabled(port)) {
622 if (!txe) {
623 rx_enabled(port) = 0;
624 continue;
625 }
626 } else {
627 if (txe) {
628 ufcon = rd_regl(port, S3C2410_UFCON);
629 ufcon |= S3C2410_UFCON_RESETRX;
630 wr_regl(port, S3C2410_UFCON, ufcon);
631 rx_enabled(port) = 1;
632 return;
633 }
634 continue;
635 }
636 }
637
638 /* insert the character into the buffer */
639
640 flag = TTY_NORMAL;
641 port->icount.rx++;
642
643 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
644 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
645 ch, uerstat);
646
647 /* check for break */
648 if (uerstat & S3C2410_UERSTAT_BREAK) {
649 dbg("break!\n");
650 port->icount.brk++;
651 if (uart_handle_break(port))
652 continue; /* Ignore character */
653 }
654
655 if (uerstat & S3C2410_UERSTAT_FRAME)
656 port->icount.frame++;
657 if (uerstat & S3C2410_UERSTAT_OVERRUN)
658 port->icount.overrun++;
659
660 uerstat &= port->read_status_mask;
661
662 if (uerstat & S3C2410_UERSTAT_BREAK)
663 flag = TTY_BREAK;
664 else if (uerstat & S3C2410_UERSTAT_PARITY)
665 flag = TTY_PARITY;
666 else if (uerstat & (S3C2410_UERSTAT_FRAME |
667 S3C2410_UERSTAT_OVERRUN))
668 flag = TTY_FRAME;
669 }
670
671 if (uart_handle_sysrq_char(port, ch))
672 continue; /* Ignore character */
673
674 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
675 ch, flag);
676 }
677
678 tty_flip_buffer_push(&port->state->port);
679 }
680
681 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
682 {
683 struct s3c24xx_uart_port *ourport = dev_id;
684 struct uart_port *port = &ourport->port;
685 unsigned long flags;
686
687 spin_lock_irqsave(&port->lock, flags);
688 s3c24xx_serial_rx_drain_fifo(ourport);
689 spin_unlock_irqrestore(&port->lock, flags);
690
691 return IRQ_HANDLED;
692 }
693
694
695 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
696 {
697 struct s3c24xx_uart_port *ourport = dev_id;
698
699 if (ourport->dma && ourport->dma->rx_chan)
700 return s3c24xx_serial_rx_chars_dma(dev_id);
701 return s3c24xx_serial_rx_chars_pio(dev_id);
702 }
703
704 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
705 {
706 struct s3c24xx_uart_port *ourport = id;
707 struct uart_port *port = &ourport->port;
708 struct circ_buf *xmit = &port->state->xmit;
709 unsigned long flags;
710 int count, dma_count = 0;
711
712 spin_lock_irqsave(&port->lock, flags);
713
714 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
715
716 if (ourport->dma && ourport->dma->tx_chan &&
717 count >= ourport->min_dma_size) {
718 int align = dma_get_cache_alignment() -
719 (xmit->tail & (dma_get_cache_alignment() - 1));
720 if (count-align >= ourport->min_dma_size) {
721 dma_count = count-align;
722 count = align;
723 }
724 }
725
726 if (port->x_char) {
727 wr_regb(port, S3C2410_UTXH, port->x_char);
728 port->icount.tx++;
729 port->x_char = 0;
730 goto out;
731 }
732
733 /* if there isn't anything more to transmit, or the uart is now
734 * stopped, disable the uart and exit
735 */
736
737 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
738 s3c24xx_serial_stop_tx(port);
739 goto out;
740 }
741
742 /* try and drain the buffer... */
743
744 if (count > port->fifosize) {
745 count = port->fifosize;
746 dma_count = 0;
747 }
748
749 while (!uart_circ_empty(xmit) && count > 0) {
750 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
751 break;
752
753 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
754 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
755 port->icount.tx++;
756 count--;
757 }
758
759 if (!count && dma_count) {
760 s3c24xx_serial_start_tx_dma(ourport, dma_count);
761 goto out;
762 }
763
764 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
765 spin_unlock(&port->lock);
766 uart_write_wakeup(port);
767 spin_lock(&port->lock);
768 }
769
770 if (uart_circ_empty(xmit))
771 s3c24xx_serial_stop_tx(port);
772
773 out:
774 spin_unlock_irqrestore(&port->lock, flags);
775 return IRQ_HANDLED;
776 }
777
778 /* interrupt handler for s3c64xx and later SoC's.*/
779 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
780 {
781 struct s3c24xx_uart_port *ourport = id;
782 struct uart_port *port = &ourport->port;
783 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
784 irqreturn_t ret = IRQ_HANDLED;
785
786 if (pend & S3C64XX_UINTM_RXD_MSK) {
787 ret = s3c24xx_serial_rx_chars(irq, id);
788 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
789 }
790 if (pend & S3C64XX_UINTM_TXD_MSK) {
791 ret = s3c24xx_serial_tx_chars(irq, id);
792 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
793 }
794 return ret;
795 }
796
797 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
798 {
799 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
800 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
801 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
802
803 if (ufcon & S3C2410_UFCON_FIFOMODE) {
804 if ((ufstat & info->tx_fifomask) != 0 ||
805 (ufstat & info->tx_fifofull))
806 return 0;
807
808 return 1;
809 }
810
811 return s3c24xx_serial_txempty_nofifo(port);
812 }
813
814 /* no modem control lines */
815 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
816 {
817 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
818
819 if (umstat & S3C2410_UMSTAT_CTS)
820 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
821 else
822 return TIOCM_CAR | TIOCM_DSR;
823 }
824
825 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
826 {
827 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
828
829 if (mctrl & TIOCM_RTS)
830 umcon |= S3C2410_UMCOM_RTS_LOW;
831 else
832 umcon &= ~S3C2410_UMCOM_RTS_LOW;
833
834 wr_regl(port, S3C2410_UMCON, umcon);
835 }
836
837 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
838 {
839 unsigned long flags;
840 unsigned int ucon;
841
842 spin_lock_irqsave(&port->lock, flags);
843
844 ucon = rd_regl(port, S3C2410_UCON);
845
846 if (break_state)
847 ucon |= S3C2410_UCON_SBREAK;
848 else
849 ucon &= ~S3C2410_UCON_SBREAK;
850
851 wr_regl(port, S3C2410_UCON, ucon);
852
853 spin_unlock_irqrestore(&port->lock, flags);
854 }
855
856 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
857 {
858 struct s3c24xx_uart_dma *dma = p->dma;
859 int ret;
860
861 /* Default slave configuration parameters */
862 dma->rx_conf.direction = DMA_DEV_TO_MEM;
863 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
864 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
865 dma->rx_conf.src_maxburst = 16;
866
867 dma->tx_conf.direction = DMA_MEM_TO_DEV;
868 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
869 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
870 if (dma_get_cache_alignment() >= 16)
871 dma->tx_conf.dst_maxburst = 16;
872 else
873 dma->tx_conf.dst_maxburst = 1;
874
875 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
876
877 if (IS_ERR(dma->rx_chan))
878 return PTR_ERR(dma->rx_chan);
879
880 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
881
882 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
883 if (IS_ERR(dma->tx_chan)) {
884 ret = PTR_ERR(dma->tx_chan);
885 goto err_release_rx;
886 }
887
888 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
889
890 /* RX buffer */
891 dma->rx_size = PAGE_SIZE;
892
893 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
894 if (!dma->rx_buf) {
895 ret = -ENOMEM;
896 goto err_release_tx;
897 }
898
899 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
900 dma->rx_size, DMA_FROM_DEVICE);
901 if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
902 ret = -EIO;
903 goto err_free_rx;
904 }
905
906 /* TX buffer */
907 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
908 UART_XMIT_SIZE, DMA_TO_DEVICE);
909 if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
910 ret = -EIO;
911 goto err_unmap_rx;
912 }
913
914 return 0;
915
916 err_unmap_rx:
917 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
918 DMA_FROM_DEVICE);
919 err_free_rx:
920 kfree(dma->rx_buf);
921 err_release_tx:
922 dma_release_channel(dma->tx_chan);
923 err_release_rx:
924 dma_release_channel(dma->rx_chan);
925 return ret;
926 }
927
928 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
929 {
930 struct s3c24xx_uart_dma *dma = p->dma;
931
932 if (dma->rx_chan) {
933 dmaengine_terminate_all(dma->rx_chan);
934 dma_unmap_single(p->port.dev, dma->rx_addr,
935 dma->rx_size, DMA_FROM_DEVICE);
936 kfree(dma->rx_buf);
937 dma_release_channel(dma->rx_chan);
938 dma->rx_chan = NULL;
939 }
940
941 if (dma->tx_chan) {
942 dmaengine_terminate_all(dma->tx_chan);
943 dma_unmap_single(p->port.dev, dma->tx_addr,
944 UART_XMIT_SIZE, DMA_TO_DEVICE);
945 dma_release_channel(dma->tx_chan);
946 dma->tx_chan = NULL;
947 }
948 }
949
950 static void s3c24xx_serial_shutdown(struct uart_port *port)
951 {
952 struct s3c24xx_uart_port *ourport = to_ourport(port);
953
954 if (ourport->tx_claimed) {
955 if (!s3c24xx_serial_has_interrupt_mask(port))
956 free_irq(ourport->tx_irq, ourport);
957 tx_enabled(port) = 0;
958 ourport->tx_claimed = 0;
959 ourport->tx_mode = 0;
960 }
961
962 if (ourport->rx_claimed) {
963 if (!s3c24xx_serial_has_interrupt_mask(port))
964 free_irq(ourport->rx_irq, ourport);
965 ourport->rx_claimed = 0;
966 rx_enabled(port) = 0;
967 }
968
969 /* Clear pending interrupts and mask all interrupts */
970 if (s3c24xx_serial_has_interrupt_mask(port)) {
971 free_irq(port->irq, ourport);
972
973 wr_regl(port, S3C64XX_UINTP, 0xf);
974 wr_regl(port, S3C64XX_UINTM, 0xf);
975 }
976
977 if (ourport->dma)
978 s3c24xx_serial_release_dma(ourport);
979
980 ourport->tx_in_progress = 0;
981 }
982
983 static int s3c24xx_serial_startup(struct uart_port *port)
984 {
985 struct s3c24xx_uart_port *ourport = to_ourport(port);
986 int ret;
987
988 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
989 port, (unsigned long long)port->mapbase, port->membase);
990
991 rx_enabled(port) = 1;
992
993 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
994 s3c24xx_serial_portname(port), ourport);
995
996 if (ret != 0) {
997 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
998 return ret;
999 }
1000
1001 ourport->rx_claimed = 1;
1002
1003 dbg("requesting tx irq...\n");
1004
1005 tx_enabled(port) = 1;
1006
1007 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1008 s3c24xx_serial_portname(port), ourport);
1009
1010 if (ret) {
1011 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1012 goto err;
1013 }
1014
1015 ourport->tx_claimed = 1;
1016
1017 dbg("s3c24xx_serial_startup ok\n");
1018
1019 /* the port reset code should have done the correct
1020 * register setup for the port controls */
1021
1022 return ret;
1023
1024 err:
1025 s3c24xx_serial_shutdown(port);
1026 return ret;
1027 }
1028
1029 static int s3c64xx_serial_startup(struct uart_port *port)
1030 {
1031 struct s3c24xx_uart_port *ourport = to_ourport(port);
1032 unsigned long flags;
1033 unsigned int ufcon;
1034 int ret;
1035
1036 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1037 port, (unsigned long long)port->mapbase, port->membase);
1038
1039 wr_regl(port, S3C64XX_UINTM, 0xf);
1040 if (ourport->dma) {
1041 ret = s3c24xx_serial_request_dma(ourport);
1042 if (ret < 0) {
1043 dev_warn(port->dev,
1044 "DMA request failed, DMA will not be used\n");
1045 devm_kfree(port->dev, ourport->dma);
1046 ourport->dma = NULL;
1047 }
1048 }
1049
1050 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1051 s3c24xx_serial_portname(port), ourport);
1052 if (ret) {
1053 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1054 return ret;
1055 }
1056
1057 /* For compatibility with s3c24xx Soc's */
1058 rx_enabled(port) = 1;
1059 ourport->rx_claimed = 1;
1060 tx_enabled(port) = 0;
1061 ourport->tx_claimed = 1;
1062
1063 spin_lock_irqsave(&port->lock, flags);
1064
1065 ufcon = rd_regl(port, S3C2410_UFCON);
1066 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1067 if (!uart_console(port))
1068 ufcon |= S3C2410_UFCON_RESETTX;
1069 wr_regl(port, S3C2410_UFCON, ufcon);
1070
1071 enable_rx_pio(ourport);
1072
1073 spin_unlock_irqrestore(&port->lock, flags);
1074
1075 /* Enable Rx Interrupt */
1076 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1077
1078 dbg("s3c64xx_serial_startup ok\n");
1079 return ret;
1080 }
1081
1082 /* power power management control */
1083
1084 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1085 unsigned int old)
1086 {
1087 struct s3c24xx_uart_port *ourport = to_ourport(port);
1088 int timeout = 10000;
1089
1090 ourport->pm_level = level;
1091
1092 switch (level) {
1093 case 3:
1094 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1095 udelay(100);
1096
1097 if (!IS_ERR(ourport->baudclk))
1098 clk_disable_unprepare(ourport->baudclk);
1099
1100 clk_disable_unprepare(ourport->clk);
1101 break;
1102
1103 case 0:
1104 clk_prepare_enable(ourport->clk);
1105
1106 if (!IS_ERR(ourport->baudclk))
1107 clk_prepare_enable(ourport->baudclk);
1108
1109 break;
1110 default:
1111 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1112 }
1113 }
1114
1115 /* baud rate calculation
1116 *
1117 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1118 * of different sources, including the peripheral clock ("pclk") and an
1119 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1120 * with a programmable extra divisor.
1121 *
1122 * The following code goes through the clock sources, and calculates the
1123 * baud clocks (and the resultant actual baud rates) and then tries to
1124 * pick the closest one and select that.
1125 *
1126 */
1127
1128 #define MAX_CLK_NAME_LENGTH 15
1129
1130 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1131 {
1132 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1133 unsigned int ucon;
1134
1135 if (info->num_clks == 1)
1136 return 0;
1137
1138 ucon = rd_regl(port, S3C2410_UCON);
1139 ucon &= info->clksel_mask;
1140 return ucon >> info->clksel_shift;
1141 }
1142
1143 static void s3c24xx_serial_setsource(struct uart_port *port,
1144 unsigned int clk_sel)
1145 {
1146 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1147 unsigned int ucon;
1148
1149 if (info->num_clks == 1)
1150 return;
1151
1152 ucon = rd_regl(port, S3C2410_UCON);
1153 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1154 return;
1155
1156 ucon &= ~info->clksel_mask;
1157 ucon |= clk_sel << info->clksel_shift;
1158 wr_regl(port, S3C2410_UCON, ucon);
1159 }
1160
1161 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1162 unsigned int req_baud, struct clk **best_clk,
1163 unsigned int *clk_num)
1164 {
1165 struct s3c24xx_uart_info *info = ourport->info;
1166 struct clk *clk;
1167 unsigned long rate;
1168 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1169 char clkname[MAX_CLK_NAME_LENGTH];
1170 int calc_deviation, deviation = (1 << 30) - 1;
1171
1172 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1173 ourport->info->def_clk_sel;
1174 for (cnt = 0; cnt < info->num_clks; cnt++) {
1175 if (!(clk_sel & (1 << cnt)))
1176 continue;
1177
1178 sprintf(clkname, "clk_uart_baud%d", cnt);
1179 clk = clk_get(ourport->port.dev, clkname);
1180 if (IS_ERR(clk))
1181 continue;
1182
1183 rate = clk_get_rate(clk);
1184 if (!rate)
1185 continue;
1186
1187 if (ourport->info->has_divslot) {
1188 unsigned long div = rate / req_baud;
1189
1190 /* The UDIVSLOT register on the newer UARTs allows us to
1191 * get a divisor adjustment of 1/16th on the baud clock.
1192 *
1193 * We don't keep the UDIVSLOT value (the 16ths we
1194 * calculated by not multiplying the baud by 16) as it
1195 * is easy enough to recalculate.
1196 */
1197
1198 quot = div / 16;
1199 baud = rate / div;
1200 } else {
1201 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1202 baud = rate / (quot * 16);
1203 }
1204 quot--;
1205
1206 calc_deviation = req_baud - baud;
1207 if (calc_deviation < 0)
1208 calc_deviation = -calc_deviation;
1209
1210 if (calc_deviation < deviation) {
1211 *best_clk = clk;
1212 best_quot = quot;
1213 *clk_num = cnt;
1214 deviation = calc_deviation;
1215 }
1216 }
1217
1218 return best_quot;
1219 }
1220
1221 /* udivslot_table[]
1222 *
1223 * This table takes the fractional value of the baud divisor and gives
1224 * the recommended setting for the UDIVSLOT register.
1225 */
1226 static u16 udivslot_table[16] = {
1227 [0] = 0x0000,
1228 [1] = 0x0080,
1229 [2] = 0x0808,
1230 [3] = 0x0888,
1231 [4] = 0x2222,
1232 [5] = 0x4924,
1233 [6] = 0x4A52,
1234 [7] = 0x54AA,
1235 [8] = 0x5555,
1236 [9] = 0xD555,
1237 [10] = 0xD5D5,
1238 [11] = 0xDDD5,
1239 [12] = 0xDDDD,
1240 [13] = 0xDFDD,
1241 [14] = 0xDFDF,
1242 [15] = 0xFFDF,
1243 };
1244
1245 static void s3c24xx_serial_set_termios(struct uart_port *port,
1246 struct ktermios *termios,
1247 struct ktermios *old)
1248 {
1249 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1250 struct s3c24xx_uart_port *ourport = to_ourport(port);
1251 struct clk *clk = ERR_PTR(-EINVAL);
1252 unsigned long flags;
1253 unsigned int baud, quot, clk_sel = 0;
1254 unsigned int ulcon;
1255 unsigned int umcon;
1256 unsigned int udivslot = 0;
1257
1258 /*
1259 * We don't support modem control lines.
1260 */
1261 termios->c_cflag &= ~(HUPCL | CMSPAR);
1262 termios->c_cflag |= CLOCAL;
1263
1264 /*
1265 * Ask the core to calculate the divisor for us.
1266 */
1267
1268 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1269 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1270 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1271 quot = port->custom_divisor;
1272 if (IS_ERR(clk))
1273 return;
1274
1275 /* check to see if we need to change clock source */
1276
1277 if (ourport->baudclk != clk) {
1278 clk_prepare_enable(clk);
1279
1280 s3c24xx_serial_setsource(port, clk_sel);
1281
1282 if (!IS_ERR(ourport->baudclk)) {
1283 clk_disable_unprepare(ourport->baudclk);
1284 ourport->baudclk = ERR_PTR(-EINVAL);
1285 }
1286
1287 ourport->baudclk = clk;
1288 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1289 }
1290
1291 if (ourport->info->has_divslot) {
1292 unsigned int div = ourport->baudclk_rate / baud;
1293
1294 if (cfg->has_fracval) {
1295 udivslot = (div & 15);
1296 dbg("fracval = %04x\n", udivslot);
1297 } else {
1298 udivslot = udivslot_table[div & 15];
1299 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1300 }
1301 }
1302
1303 switch (termios->c_cflag & CSIZE) {
1304 case CS5:
1305 dbg("config: 5bits/char\n");
1306 ulcon = S3C2410_LCON_CS5;
1307 break;
1308 case CS6:
1309 dbg("config: 6bits/char\n");
1310 ulcon = S3C2410_LCON_CS6;
1311 break;
1312 case CS7:
1313 dbg("config: 7bits/char\n");
1314 ulcon = S3C2410_LCON_CS7;
1315 break;
1316 case CS8:
1317 default:
1318 dbg("config: 8bits/char\n");
1319 ulcon = S3C2410_LCON_CS8;
1320 break;
1321 }
1322
1323 /* preserve original lcon IR settings */
1324 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1325
1326 if (termios->c_cflag & CSTOPB)
1327 ulcon |= S3C2410_LCON_STOPB;
1328
1329 if (termios->c_cflag & PARENB) {
1330 if (termios->c_cflag & PARODD)
1331 ulcon |= S3C2410_LCON_PODD;
1332 else
1333 ulcon |= S3C2410_LCON_PEVEN;
1334 } else {
1335 ulcon |= S3C2410_LCON_PNONE;
1336 }
1337
1338 spin_lock_irqsave(&port->lock, flags);
1339
1340 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1341 ulcon, quot, udivslot);
1342
1343 wr_regl(port, S3C2410_ULCON, ulcon);
1344 wr_regl(port, S3C2410_UBRDIV, quot);
1345
1346 umcon = rd_regl(port, S3C2410_UMCON);
1347 if (termios->c_cflag & CRTSCTS) {
1348 umcon |= S3C2410_UMCOM_AFC;
1349 /* Disable RTS when RX FIFO contains 63 bytes */
1350 umcon &= ~S3C2412_UMCON_AFC_8;
1351 } else {
1352 umcon &= ~S3C2410_UMCOM_AFC;
1353 }
1354 wr_regl(port, S3C2410_UMCON, umcon);
1355
1356 if (ourport->info->has_divslot)
1357 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1358
1359 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1360 rd_regl(port, S3C2410_ULCON),
1361 rd_regl(port, S3C2410_UCON),
1362 rd_regl(port, S3C2410_UFCON));
1363
1364 /*
1365 * Update the per-port timeout.
1366 */
1367 uart_update_timeout(port, termios->c_cflag, baud);
1368
1369 /*
1370 * Which character status flags are we interested in?
1371 */
1372 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1373 if (termios->c_iflag & INPCK)
1374 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1375 S3C2410_UERSTAT_PARITY;
1376 /*
1377 * Which character status flags should we ignore?
1378 */
1379 port->ignore_status_mask = 0;
1380 if (termios->c_iflag & IGNPAR)
1381 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1382 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1383 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1384
1385 /*
1386 * Ignore all characters if CREAD is not set.
1387 */
1388 if ((termios->c_cflag & CREAD) == 0)
1389 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1390
1391 spin_unlock_irqrestore(&port->lock, flags);
1392 }
1393
1394 static const char *s3c24xx_serial_type(struct uart_port *port)
1395 {
1396 switch (port->type) {
1397 case PORT_S3C2410:
1398 return "S3C2410";
1399 case PORT_S3C2440:
1400 return "S3C2440";
1401 case PORT_S3C2412:
1402 return "S3C2412";
1403 case PORT_S3C6400:
1404 return "S3C6400/10";
1405 default:
1406 return NULL;
1407 }
1408 }
1409
1410 #define MAP_SIZE (0x100)
1411
1412 static void s3c24xx_serial_release_port(struct uart_port *port)
1413 {
1414 release_mem_region(port->mapbase, MAP_SIZE);
1415 }
1416
1417 static int s3c24xx_serial_request_port(struct uart_port *port)
1418 {
1419 const char *name = s3c24xx_serial_portname(port);
1420 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1421 }
1422
1423 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1424 {
1425 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1426
1427 if (flags & UART_CONFIG_TYPE &&
1428 s3c24xx_serial_request_port(port) == 0)
1429 port->type = info->type;
1430 }
1431
1432 /*
1433 * verify the new serial_struct (for TIOCSSERIAL).
1434 */
1435 static int
1436 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1437 {
1438 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1439
1440 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1441 return -EINVAL;
1442
1443 return 0;
1444 }
1445
1446
1447 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1448
1449 static struct console s3c24xx_serial_console;
1450
1451 static int __init s3c24xx_serial_console_init(void)
1452 {
1453 register_console(&s3c24xx_serial_console);
1454 return 0;
1455 }
1456 console_initcall(s3c24xx_serial_console_init);
1457
1458 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1459 #else
1460 #define S3C24XX_SERIAL_CONSOLE NULL
1461 #endif
1462
1463 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1464 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1465 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1466 unsigned char c);
1467 #endif
1468
1469 static struct uart_ops s3c24xx_serial_ops = {
1470 .pm = s3c24xx_serial_pm,
1471 .tx_empty = s3c24xx_serial_tx_empty,
1472 .get_mctrl = s3c24xx_serial_get_mctrl,
1473 .set_mctrl = s3c24xx_serial_set_mctrl,
1474 .stop_tx = s3c24xx_serial_stop_tx,
1475 .start_tx = s3c24xx_serial_start_tx,
1476 .stop_rx = s3c24xx_serial_stop_rx,
1477 .break_ctl = s3c24xx_serial_break_ctl,
1478 .startup = s3c24xx_serial_startup,
1479 .shutdown = s3c24xx_serial_shutdown,
1480 .set_termios = s3c24xx_serial_set_termios,
1481 .type = s3c24xx_serial_type,
1482 .release_port = s3c24xx_serial_release_port,
1483 .request_port = s3c24xx_serial_request_port,
1484 .config_port = s3c24xx_serial_config_port,
1485 .verify_port = s3c24xx_serial_verify_port,
1486 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1487 .poll_get_char = s3c24xx_serial_get_poll_char,
1488 .poll_put_char = s3c24xx_serial_put_poll_char,
1489 #endif
1490 };
1491
1492 static struct uart_driver s3c24xx_uart_drv = {
1493 .owner = THIS_MODULE,
1494 .driver_name = "s3c2410_serial",
1495 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
1496 .cons = S3C24XX_SERIAL_CONSOLE,
1497 .dev_name = S3C24XX_SERIAL_NAME,
1498 .major = S3C24XX_SERIAL_MAJOR,
1499 .minor = S3C24XX_SERIAL_MINOR,
1500 };
1501
1502 #define __PORT_LOCK_UNLOCKED(i) \
1503 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1504 static struct s3c24xx_uart_port
1505 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1506 [0] = {
1507 .port = {
1508 .lock = __PORT_LOCK_UNLOCKED(0),
1509 .iotype = UPIO_MEM,
1510 .uartclk = 0,
1511 .fifosize = 16,
1512 .ops = &s3c24xx_serial_ops,
1513 .flags = UPF_BOOT_AUTOCONF,
1514 .line = 0,
1515 }
1516 },
1517 [1] = {
1518 .port = {
1519 .lock = __PORT_LOCK_UNLOCKED(1),
1520 .iotype = UPIO_MEM,
1521 .uartclk = 0,
1522 .fifosize = 16,
1523 .ops = &s3c24xx_serial_ops,
1524 .flags = UPF_BOOT_AUTOCONF,
1525 .line = 1,
1526 }
1527 },
1528 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1529
1530 [2] = {
1531 .port = {
1532 .lock = __PORT_LOCK_UNLOCKED(2),
1533 .iotype = UPIO_MEM,
1534 .uartclk = 0,
1535 .fifosize = 16,
1536 .ops = &s3c24xx_serial_ops,
1537 .flags = UPF_BOOT_AUTOCONF,
1538 .line = 2,
1539 }
1540 },
1541 #endif
1542 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1543 [3] = {
1544 .port = {
1545 .lock = __PORT_LOCK_UNLOCKED(3),
1546 .iotype = UPIO_MEM,
1547 .uartclk = 0,
1548 .fifosize = 16,
1549 .ops = &s3c24xx_serial_ops,
1550 .flags = UPF_BOOT_AUTOCONF,
1551 .line = 3,
1552 }
1553 }
1554 #endif
1555 };
1556 #undef __PORT_LOCK_UNLOCKED
1557
1558 /* s3c24xx_serial_resetport
1559 *
1560 * reset the fifos and other the settings.
1561 */
1562
1563 static void s3c24xx_serial_resetport(struct uart_port *port,
1564 struct s3c2410_uartcfg *cfg)
1565 {
1566 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1567 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1568 unsigned int ucon_mask;
1569
1570 ucon_mask = info->clksel_mask;
1571 if (info->type == PORT_S3C2440)
1572 ucon_mask |= S3C2440_UCON0_DIVMASK;
1573
1574 ucon &= ucon_mask;
1575 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1576
1577 /* reset both fifos */
1578 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1579 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1580
1581 /* some delay is required after fifo reset */
1582 udelay(1);
1583 }
1584
1585
1586 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1587
1588 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1589 unsigned long val, void *data)
1590 {
1591 struct s3c24xx_uart_port *port;
1592 struct uart_port *uport;
1593
1594 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1595 uport = &port->port;
1596
1597 /* check to see if port is enabled */
1598
1599 if (port->pm_level != 0)
1600 return 0;
1601
1602 /* try and work out if the baudrate is changing, we can detect
1603 * a change in rate, but we do not have support for detecting
1604 * a disturbance in the clock-rate over the change.
1605 */
1606
1607 if (IS_ERR(port->baudclk))
1608 goto exit;
1609
1610 if (port->baudclk_rate == clk_get_rate(port->baudclk))
1611 goto exit;
1612
1613 if (val == CPUFREQ_PRECHANGE) {
1614 /* we should really shut the port down whilst the
1615 * frequency change is in progress. */
1616
1617 } else if (val == CPUFREQ_POSTCHANGE) {
1618 struct ktermios *termios;
1619 struct tty_struct *tty;
1620
1621 if (uport->state == NULL)
1622 goto exit;
1623
1624 tty = uport->state->port.tty;
1625
1626 if (tty == NULL)
1627 goto exit;
1628
1629 termios = &tty->termios;
1630
1631 if (termios == NULL) {
1632 dev_warn(uport->dev, "%s: no termios?\n", __func__);
1633 goto exit;
1634 }
1635
1636 s3c24xx_serial_set_termios(uport, termios, NULL);
1637 }
1638
1639 exit:
1640 return 0;
1641 }
1642
1643 static inline int
1644 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1645 {
1646 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1647
1648 return cpufreq_register_notifier(&port->freq_transition,
1649 CPUFREQ_TRANSITION_NOTIFIER);
1650 }
1651
1652 static inline void
1653 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1654 {
1655 cpufreq_unregister_notifier(&port->freq_transition,
1656 CPUFREQ_TRANSITION_NOTIFIER);
1657 }
1658
1659 #else
1660 static inline int
1661 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1662 {
1663 return 0;
1664 }
1665
1666 static inline void
1667 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1668 {
1669 }
1670 #endif
1671
1672 /* s3c24xx_serial_init_port
1673 *
1674 * initialise a single serial port from the platform device given
1675 */
1676
1677 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1678 struct platform_device *platdev)
1679 {
1680 struct uart_port *port = &ourport->port;
1681 struct s3c2410_uartcfg *cfg = ourport->cfg;
1682 struct resource *res;
1683 int ret;
1684
1685 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1686
1687 if (platdev == NULL)
1688 return -ENODEV;
1689
1690 if (port->mapbase != 0)
1691 return -EINVAL;
1692
1693 /* setup info for port */
1694 port->dev = &platdev->dev;
1695
1696 /* Startup sequence is different for s3c64xx and higher SoC's */
1697 if (s3c24xx_serial_has_interrupt_mask(port))
1698 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1699
1700 port->uartclk = 1;
1701
1702 if (cfg->uart_flags & UPF_CONS_FLOW) {
1703 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1704 port->flags |= UPF_CONS_FLOW;
1705 }
1706
1707 /* sort our the physical and virtual addresses for each UART */
1708
1709 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1710 if (res == NULL) {
1711 dev_err(port->dev, "failed to find memory resource for uart\n");
1712 return -EINVAL;
1713 }
1714
1715 dbg("resource %pR)\n", res);
1716
1717 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1718 if (!port->membase) {
1719 dev_err(port->dev, "failed to remap controller address\n");
1720 return -EBUSY;
1721 }
1722
1723 port->mapbase = res->start;
1724 ret = platform_get_irq(platdev, 0);
1725 if (ret < 0)
1726 port->irq = 0;
1727 else {
1728 port->irq = ret;
1729 ourport->rx_irq = ret;
1730 ourport->tx_irq = ret + 1;
1731 }
1732
1733 ret = platform_get_irq(platdev, 1);
1734 if (ret > 0)
1735 ourport->tx_irq = ret;
1736 /*
1737 * DMA is currently supported only on DT platforms, if DMA properties
1738 * are specified.
1739 */
1740 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1741 "dmas", NULL)) {
1742 ourport->dma = devm_kzalloc(port->dev,
1743 sizeof(*ourport->dma),
1744 GFP_KERNEL);
1745 if (!ourport->dma) {
1746 ret = -ENOMEM;
1747 goto err;
1748 }
1749 }
1750
1751 ourport->clk = clk_get(&platdev->dev, "uart");
1752 if (IS_ERR(ourport->clk)) {
1753 pr_err("%s: Controller clock not found\n",
1754 dev_name(&platdev->dev));
1755 ret = PTR_ERR(ourport->clk);
1756 goto err;
1757 }
1758
1759 ret = clk_prepare_enable(ourport->clk);
1760 if (ret) {
1761 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1762 clk_put(ourport->clk);
1763 goto err;
1764 }
1765
1766 /* Keep all interrupts masked and cleared */
1767 if (s3c24xx_serial_has_interrupt_mask(port)) {
1768 wr_regl(port, S3C64XX_UINTM, 0xf);
1769 wr_regl(port, S3C64XX_UINTP, 0xf);
1770 wr_regl(port, S3C64XX_UINTSP, 0xf);
1771 }
1772
1773 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1774 &port->mapbase, port->membase, port->irq,
1775 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1776
1777 /* reset the fifos (and setup the uart) */
1778 s3c24xx_serial_resetport(port, cfg);
1779
1780 return 0;
1781
1782 err:
1783 port->mapbase = 0;
1784 return ret;
1785 }
1786
1787 /* Device driver serial port probe */
1788
1789 static const struct of_device_id s3c24xx_uart_dt_match[];
1790 static int probe_index;
1791
1792 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1793 struct platform_device *pdev)
1794 {
1795 #ifdef CONFIG_OF
1796 if (pdev->dev.of_node) {
1797 const struct of_device_id *match;
1798 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1799 return (struct s3c24xx_serial_drv_data *)match->data;
1800 }
1801 #endif
1802 return (struct s3c24xx_serial_drv_data *)
1803 platform_get_device_id(pdev)->driver_data;
1804 }
1805
1806 static int s3c24xx_serial_probe(struct platform_device *pdev)
1807 {
1808 struct device_node *np = pdev->dev.of_node;
1809 struct s3c24xx_uart_port *ourport;
1810 int index = probe_index;
1811 int ret;
1812
1813 if (np) {
1814 ret = of_alias_get_id(np, "serial");
1815 if (ret >= 0)
1816 index = ret;
1817 }
1818
1819 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1820
1821 ourport = &s3c24xx_serial_ports[index];
1822
1823 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1824 if (!ourport->drv_data) {
1825 dev_err(&pdev->dev, "could not find driver data\n");
1826 return -ENODEV;
1827 }
1828
1829 ourport->baudclk = ERR_PTR(-EINVAL);
1830 ourport->info = ourport->drv_data->info;
1831 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1832 dev_get_platdata(&pdev->dev) :
1833 ourport->drv_data->def_cfg;
1834
1835 if (np)
1836 of_property_read_u32(np,
1837 "samsung,uart-fifosize", &ourport->port.fifosize);
1838
1839 if (ourport->drv_data->fifosize[index])
1840 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1841 else if (ourport->info->fifosize)
1842 ourport->port.fifosize = ourport->info->fifosize;
1843
1844 /*
1845 * DMA transfers must be aligned at least to cache line size,
1846 * so find minimal transfer size suitable for DMA mode
1847 */
1848 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1849 dma_get_cache_alignment());
1850
1851 dbg("%s: initialising port %p...\n", __func__, ourport);
1852
1853 ret = s3c24xx_serial_init_port(ourport, pdev);
1854 if (ret < 0)
1855 return ret;
1856
1857 if (!s3c24xx_uart_drv.state) {
1858 ret = uart_register_driver(&s3c24xx_uart_drv);
1859 if (ret < 0) {
1860 pr_err("Failed to register Samsung UART driver\n");
1861 return ret;
1862 }
1863 }
1864
1865 dbg("%s: adding port\n", __func__);
1866 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1867 platform_set_drvdata(pdev, &ourport->port);
1868
1869 /*
1870 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1871 * so that a potential re-enablement through the pm-callback overlaps
1872 * and keeps the clock enabled in this case.
1873 */
1874 clk_disable_unprepare(ourport->clk);
1875
1876 ret = s3c24xx_serial_cpufreq_register(ourport);
1877 if (ret < 0)
1878 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1879
1880 probe_index++;
1881
1882 return 0;
1883 }
1884
1885 static int s3c24xx_serial_remove(struct platform_device *dev)
1886 {
1887 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1888
1889 if (port) {
1890 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1891 uart_remove_one_port(&s3c24xx_uart_drv, port);
1892 }
1893
1894 uart_unregister_driver(&s3c24xx_uart_drv);
1895
1896 return 0;
1897 }
1898
1899 /* UART power management code */
1900 #ifdef CONFIG_PM_SLEEP
1901 static int s3c24xx_serial_suspend(struct device *dev)
1902 {
1903 struct uart_port *port = s3c24xx_dev_to_port(dev);
1904
1905 if (port)
1906 uart_suspend_port(&s3c24xx_uart_drv, port);
1907
1908 return 0;
1909 }
1910
1911 static int s3c24xx_serial_resume(struct device *dev)
1912 {
1913 struct uart_port *port = s3c24xx_dev_to_port(dev);
1914 struct s3c24xx_uart_port *ourport = to_ourport(port);
1915
1916 if (port) {
1917 clk_prepare_enable(ourport->clk);
1918 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1919 clk_disable_unprepare(ourport->clk);
1920
1921 uart_resume_port(&s3c24xx_uart_drv, port);
1922 }
1923
1924 return 0;
1925 }
1926
1927 static int s3c24xx_serial_resume_noirq(struct device *dev)
1928 {
1929 struct uart_port *port = s3c24xx_dev_to_port(dev);
1930 struct s3c24xx_uart_port *ourport = to_ourport(port);
1931
1932 if (port) {
1933 /* restore IRQ mask */
1934 if (s3c24xx_serial_has_interrupt_mask(port)) {
1935 unsigned int uintm = 0xf;
1936 if (tx_enabled(port))
1937 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1938 if (rx_enabled(port))
1939 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1940 clk_prepare_enable(ourport->clk);
1941 wr_regl(port, S3C64XX_UINTM, uintm);
1942 clk_disable_unprepare(ourport->clk);
1943 }
1944 }
1945
1946 return 0;
1947 }
1948
1949 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1950 .suspend = s3c24xx_serial_suspend,
1951 .resume = s3c24xx_serial_resume,
1952 .resume_noirq = s3c24xx_serial_resume_noirq,
1953 };
1954 #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1955
1956 #else /* !CONFIG_PM_SLEEP */
1957
1958 #define SERIAL_SAMSUNG_PM_OPS NULL
1959 #endif /* CONFIG_PM_SLEEP */
1960
1961 /* Console code */
1962
1963 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1964
1965 static struct uart_port *cons_uart;
1966
1967 static int
1968 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1969 {
1970 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1971 unsigned long ufstat, utrstat;
1972
1973 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1974 /* fifo mode - check amount of data in fifo registers... */
1975
1976 ufstat = rd_regl(port, S3C2410_UFSTAT);
1977 return (ufstat & info->tx_fifofull) ? 0 : 1;
1978 }
1979
1980 /* in non-fifo mode, we go and use the tx buffer empty */
1981
1982 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1983 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1984 }
1985
1986 static bool
1987 s3c24xx_port_configured(unsigned int ucon)
1988 {
1989 /* consider the serial port configured if the tx/rx mode set */
1990 return (ucon & 0xf) != 0;
1991 }
1992
1993 #ifdef CONFIG_CONSOLE_POLL
1994 /*
1995 * Console polling routines for writing and reading from the uart while
1996 * in an interrupt or debug context.
1997 */
1998
1999 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2000 {
2001 struct s3c24xx_uart_port *ourport = to_ourport(port);
2002 unsigned int ufstat;
2003
2004 ufstat = rd_regl(port, S3C2410_UFSTAT);
2005 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2006 return NO_POLL_CHAR;
2007
2008 return rd_regb(port, S3C2410_URXH);
2009 }
2010
2011 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2012 unsigned char c)
2013 {
2014 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2015 unsigned int ucon = rd_regl(port, S3C2410_UCON);
2016
2017 /* not possible to xmit on unconfigured port */
2018 if (!s3c24xx_port_configured(ucon))
2019 return;
2020
2021 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2022 cpu_relax();
2023 wr_regb(port, S3C2410_UTXH, c);
2024 }
2025
2026 #endif /* CONFIG_CONSOLE_POLL */
2027
2028 static void
2029 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2030 {
2031 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2032
2033 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2034 cpu_relax();
2035 wr_regb(port, S3C2410_UTXH, ch);
2036 }
2037
2038 static void
2039 s3c24xx_serial_console_write(struct console *co, const char *s,
2040 unsigned int count)
2041 {
2042 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2043
2044 /* not possible to xmit on unconfigured port */
2045 if (!s3c24xx_port_configured(ucon))
2046 return;
2047
2048 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2049 }
2050
2051 static void __init
2052 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2053 int *parity, int *bits)
2054 {
2055 struct clk *clk;
2056 unsigned int ulcon;
2057 unsigned int ucon;
2058 unsigned int ubrdiv;
2059 unsigned long rate;
2060 unsigned int clk_sel;
2061 char clk_name[MAX_CLK_NAME_LENGTH];
2062
2063 ulcon = rd_regl(port, S3C2410_ULCON);
2064 ucon = rd_regl(port, S3C2410_UCON);
2065 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2066
2067 dbg("s3c24xx_serial_get_options: port=%p\n"
2068 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2069 port, ulcon, ucon, ubrdiv);
2070
2071 if (s3c24xx_port_configured(ucon)) {
2072 switch (ulcon & S3C2410_LCON_CSMASK) {
2073 case S3C2410_LCON_CS5:
2074 *bits = 5;
2075 break;
2076 case S3C2410_LCON_CS6:
2077 *bits = 6;
2078 break;
2079 case S3C2410_LCON_CS7:
2080 *bits = 7;
2081 break;
2082 case S3C2410_LCON_CS8:
2083 default:
2084 *bits = 8;
2085 break;
2086 }
2087
2088 switch (ulcon & S3C2410_LCON_PMASK) {
2089 case S3C2410_LCON_PEVEN:
2090 *parity = 'e';
2091 break;
2092
2093 case S3C2410_LCON_PODD:
2094 *parity = 'o';
2095 break;
2096
2097 case S3C2410_LCON_PNONE:
2098 default:
2099 *parity = 'n';
2100 }
2101
2102 /* now calculate the baud rate */
2103
2104 clk_sel = s3c24xx_serial_getsource(port);
2105 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2106
2107 clk = clk_get(port->dev, clk_name);
2108 if (!IS_ERR(clk))
2109 rate = clk_get_rate(clk);
2110 else
2111 rate = 1;
2112
2113 *baud = rate / (16 * (ubrdiv + 1));
2114 dbg("calculated baud %d\n", *baud);
2115 }
2116
2117 }
2118
2119 static int __init
2120 s3c24xx_serial_console_setup(struct console *co, char *options)
2121 {
2122 struct uart_port *port;
2123 int baud = 9600;
2124 int bits = 8;
2125 int parity = 'n';
2126 int flow = 'n';
2127
2128 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2129 co, co->index, options);
2130
2131 /* is this a valid port */
2132
2133 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2134 co->index = 0;
2135
2136 port = &s3c24xx_serial_ports[co->index].port;
2137
2138 /* is the port configured? */
2139
2140 if (port->mapbase == 0x0)
2141 return -ENODEV;
2142
2143 cons_uart = port;
2144
2145 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2146
2147 /*
2148 * Check whether an invalid uart number has been specified, and
2149 * if so, search for the first available port that does have
2150 * console support.
2151 */
2152 if (options)
2153 uart_parse_options(options, &baud, &parity, &bits, &flow);
2154 else
2155 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2156
2157 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2158
2159 return uart_set_options(port, co, baud, parity, bits, flow);
2160 }
2161
2162 static struct console s3c24xx_serial_console = {
2163 .name = S3C24XX_SERIAL_NAME,
2164 .device = uart_console_device,
2165 .flags = CON_PRINTBUFFER,
2166 .index = -1,
2167 .write = s3c24xx_serial_console_write,
2168 .setup = s3c24xx_serial_console_setup,
2169 .data = &s3c24xx_uart_drv,
2170 };
2171 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2172
2173 #ifdef CONFIG_CPU_S3C2410
2174 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2175 .info = &(struct s3c24xx_uart_info) {
2176 .name = "Samsung S3C2410 UART",
2177 .type = PORT_S3C2410,
2178 .fifosize = 16,
2179 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2180 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2181 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2182 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2183 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2184 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2185 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2186 .num_clks = 2,
2187 .clksel_mask = S3C2410_UCON_CLKMASK,
2188 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2189 },
2190 .def_cfg = &(struct s3c2410_uartcfg) {
2191 .ucon = S3C2410_UCON_DEFAULT,
2192 .ufcon = S3C2410_UFCON_DEFAULT,
2193 },
2194 };
2195 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2196 #else
2197 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2198 #endif
2199
2200 #ifdef CONFIG_CPU_S3C2412
2201 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2202 .info = &(struct s3c24xx_uart_info) {
2203 .name = "Samsung S3C2412 UART",
2204 .type = PORT_S3C2412,
2205 .fifosize = 64,
2206 .has_divslot = 1,
2207 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2208 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2209 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2210 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2211 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2212 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2213 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2214 .num_clks = 4,
2215 .clksel_mask = S3C2412_UCON_CLKMASK,
2216 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2217 },
2218 .def_cfg = &(struct s3c2410_uartcfg) {
2219 .ucon = S3C2410_UCON_DEFAULT,
2220 .ufcon = S3C2410_UFCON_DEFAULT,
2221 },
2222 };
2223 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2224 #else
2225 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2226 #endif
2227
2228 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2229 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2230 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2231 .info = &(struct s3c24xx_uart_info) {
2232 .name = "Samsung S3C2440 UART",
2233 .type = PORT_S3C2440,
2234 .fifosize = 64,
2235 .has_divslot = 1,
2236 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2237 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2238 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2239 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2240 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2241 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2242 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2243 .num_clks = 4,
2244 .clksel_mask = S3C2412_UCON_CLKMASK,
2245 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2246 },
2247 .def_cfg = &(struct s3c2410_uartcfg) {
2248 .ucon = S3C2410_UCON_DEFAULT,
2249 .ufcon = S3C2410_UFCON_DEFAULT,
2250 },
2251 };
2252 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2253 #else
2254 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2255 #endif
2256
2257 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2258 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2259 .info = &(struct s3c24xx_uart_info) {
2260 .name = "Samsung S3C6400 UART",
2261 .type = PORT_S3C6400,
2262 .fifosize = 64,
2263 .has_divslot = 1,
2264 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2265 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2266 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2267 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2268 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2269 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2270 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2271 .num_clks = 4,
2272 .clksel_mask = S3C6400_UCON_CLKMASK,
2273 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2274 },
2275 .def_cfg = &(struct s3c2410_uartcfg) {
2276 .ucon = S3C2410_UCON_DEFAULT,
2277 .ufcon = S3C2410_UFCON_DEFAULT,
2278 },
2279 };
2280 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2281 #else
2282 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2283 #endif
2284
2285 #ifdef CONFIG_CPU_S5PV210
2286 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2287 .info = &(struct s3c24xx_uart_info) {
2288 .name = "Samsung S5PV210 UART",
2289 .type = PORT_S3C6400,
2290 .has_divslot = 1,
2291 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2292 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2293 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2294 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2295 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2296 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2297 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2298 .num_clks = 2,
2299 .clksel_mask = S5PV210_UCON_CLKMASK,
2300 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2301 },
2302 .def_cfg = &(struct s3c2410_uartcfg) {
2303 .ucon = S5PV210_UCON_DEFAULT,
2304 .ufcon = S5PV210_UFCON_DEFAULT,
2305 },
2306 .fifosize = { 256, 64, 16, 16 },
2307 };
2308 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2309 #else
2310 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2311 #endif
2312
2313 #if defined(CONFIG_ARCH_EXYNOS)
2314 #define EXYNOS_COMMON_SERIAL_DRV_DATA \
2315 .info = &(struct s3c24xx_uart_info) { \
2316 .name = "Samsung Exynos UART", \
2317 .type = PORT_S3C6400, \
2318 .has_divslot = 1, \
2319 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2320 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2321 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2322 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2323 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2324 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2325 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2326 .num_clks = 1, \
2327 .clksel_mask = 0, \
2328 .clksel_shift = 0, \
2329 }, \
2330 .def_cfg = &(struct s3c2410_uartcfg) { \
2331 .ucon = S5PV210_UCON_DEFAULT, \
2332 .ufcon = S5PV210_UFCON_DEFAULT, \
2333 .has_fracval = 1, \
2334 } \
2335
2336 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2337 EXYNOS_COMMON_SERIAL_DRV_DATA,
2338 .fifosize = { 256, 64, 16, 16 },
2339 };
2340
2341 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2342 EXYNOS_COMMON_SERIAL_DRV_DATA,
2343 .fifosize = { 64, 256, 16, 256 },
2344 };
2345
2346 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2347 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2348 #else
2349 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2350 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2351 #endif
2352
2353 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2354 {
2355 .name = "s3c2410-uart",
2356 .driver_data = S3C2410_SERIAL_DRV_DATA,
2357 }, {
2358 .name = "s3c2412-uart",
2359 .driver_data = S3C2412_SERIAL_DRV_DATA,
2360 }, {
2361 .name = "s3c2440-uart",
2362 .driver_data = S3C2440_SERIAL_DRV_DATA,
2363 }, {
2364 .name = "s3c6400-uart",
2365 .driver_data = S3C6400_SERIAL_DRV_DATA,
2366 }, {
2367 .name = "s5pv210-uart",
2368 .driver_data = S5PV210_SERIAL_DRV_DATA,
2369 }, {
2370 .name = "exynos4210-uart",
2371 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
2372 }, {
2373 .name = "exynos5433-uart",
2374 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
2375 },
2376 { },
2377 };
2378 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2379
2380 #ifdef CONFIG_OF
2381 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2382 { .compatible = "samsung,s3c2410-uart",
2383 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2384 { .compatible = "samsung,s3c2412-uart",
2385 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2386 { .compatible = "samsung,s3c2440-uart",
2387 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2388 { .compatible = "samsung,s3c6400-uart",
2389 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2390 { .compatible = "samsung,s5pv210-uart",
2391 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2392 { .compatible = "samsung,exynos4210-uart",
2393 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2394 { .compatible = "samsung,exynos5433-uart",
2395 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2396 {},
2397 };
2398 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2399 #endif
2400
2401 static struct platform_driver samsung_serial_driver = {
2402 .probe = s3c24xx_serial_probe,
2403 .remove = s3c24xx_serial_remove,
2404 .id_table = s3c24xx_serial_driver_ids,
2405 .driver = {
2406 .name = "samsung-uart",
2407 .pm = SERIAL_SAMSUNG_PM_OPS,
2408 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2409 },
2410 };
2411
2412 module_platform_driver(samsung_serial_driver);
2413
2414 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2415 /*
2416 * Early console.
2417 */
2418
2419 struct samsung_early_console_data {
2420 u32 txfull_mask;
2421 };
2422
2423 static void samsung_early_busyuart(struct uart_port *port)
2424 {
2425 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2426 ;
2427 }
2428
2429 static void samsung_early_busyuart_fifo(struct uart_port *port)
2430 {
2431 struct samsung_early_console_data *data = port->private_data;
2432
2433 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2434 ;
2435 }
2436
2437 static void samsung_early_putc(struct uart_port *port, int c)
2438 {
2439 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2440 samsung_early_busyuart_fifo(port);
2441 else
2442 samsung_early_busyuart(port);
2443
2444 writeb(c, port->membase + S3C2410_UTXH);
2445 }
2446
2447 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2448 {
2449 struct earlycon_device *dev = con->data;
2450
2451 uart_console_write(&dev->port, s, n, samsung_early_putc);
2452 }
2453
2454 static int __init samsung_early_console_setup(struct earlycon_device *device,
2455 const char *opt)
2456 {
2457 if (!device->port.membase)
2458 return -ENODEV;
2459
2460 device->con->write = samsung_early_write;
2461 return 0;
2462 }
2463
2464 /* S3C2410 */
2465 static struct samsung_early_console_data s3c2410_early_console_data = {
2466 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2467 };
2468
2469 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2470 const char *opt)
2471 {
2472 device->port.private_data = &s3c2410_early_console_data;
2473 return samsung_early_console_setup(device, opt);
2474 }
2475 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2476 s3c2410_early_console_setup);
2477
2478 /* S3C2412, S3C2440, S3C64xx */
2479 static struct samsung_early_console_data s3c2440_early_console_data = {
2480 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2481 };
2482
2483 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2484 const char *opt)
2485 {
2486 device->port.private_data = &s3c2440_early_console_data;
2487 return samsung_early_console_setup(device, opt);
2488 }
2489 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2490 s3c2440_early_console_setup);
2491 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2492 s3c2440_early_console_setup);
2493 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2494 s3c2440_early_console_setup);
2495
2496 /* S5PV210, EXYNOS */
2497 static struct samsung_early_console_data s5pv210_early_console_data = {
2498 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2499 };
2500
2501 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2502 const char *opt)
2503 {
2504 device->port.private_data = &s5pv210_early_console_data;
2505 return samsung_early_console_setup(device, opt);
2506 }
2507 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2508 s5pv210_early_console_setup);
2509 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2510 s5pv210_early_console_setup);
2511 #endif
2512
2513 MODULE_ALIAS("platform:samsung-uart");
2514 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2515 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2516 MODULE_LICENSE("GPL v2");
CRIS linux kernel tree