| blob | 55655ab0a4c47a2c538f7e866409a5361be285f8 |
1 /*
2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
19 /* core clocks */
20 #define PLL_APLL 1
21 #define PLL_DPLL 2
22 #define PLL_CPLL 3
23 #define PLL_GPLL 4
24 #define ARMCLK 5
26 /* sclk gates (special clocks) */
27 #define SCLK_SPI0 65
28 #define SCLK_NANDC 67
29 #define SCLK_SDMMC 68
30 #define SCLK_SDIO 69
31 #define SCLK_EMMC 71
32 #define SCLK_TSADC 72
33 #define SCLK_UART0 77
34 #define SCLK_UART1 78
35 #define SCLK_UART2 79
36 #define SCLK_I2S0 80
37 #define SCLK_I2S1 81
38 #define SCLK_I2S2 82
39 #define SCLK_SPDIF 83
40 #define SCLK_TIMER0 85
41 #define SCLK_TIMER1 86
42 #define SCLK_TIMER2 87
43 #define SCLK_TIMER3 88
44 #define SCLK_TIMER4 89
45 #define SCLK_TIMER5 90
46 #define SCLK_I2S_OUT 113
47 #define SCLK_SDMMC_DRV 114
48 #define SCLK_SDIO_DRV 115
49 #define SCLK_EMMC_DRV 117
50 #define SCLK_SDMMC_SAMPLE 118
51 #define SCLK_SDIO_SAMPLE 119
52 #define SCLK_SDIO_SRC 120
53 #define SCLK_EMMC_SAMPLE 121
54 #define SCLK_VOP 122
55 #define SCLK_HDMI_HDCP 123
56 #define SCLK_MAC_SRC 124
57 #define SCLK_MAC_EXTCLK 125
58 #define SCLK_MAC 126
59 #define SCLK_MAC_REFOUT 127
60 #define SCLK_MAC_REF 128
61 #define SCLK_MAC_RX 129
62 #define SCLK_MAC_TX 130
63 #define SCLK_MAC_PHY 131
64 #define SCLK_MAC_OUT 132
65 #define SCLK_VDEC_CABAC 133
66 #define SCLK_VDEC_CORE 134
67 #define SCLK_RGA 135
68 #define SCLK_HDCP 136
69 #define SCLK_HDMI_CEC 137
70 #define SCLK_CRYPTO 138
71 #define SCLK_TSP 139
72 #define SCLK_HSADC 140
73 #define SCLK_WIFI 141
74 #define SCLK_OTGPHY0 142
75 #define SCLK_OTGPHY1 143
77 /* dclk gates */
78 #define DCLK_VOP 190
79 #define DCLK_HDMI_PHY 191
81 /* aclk gates */
82 #define ACLK_DMAC 194
83 #define ACLK_CPU 195
84 #define ACLK_VPU_PRE 196
85 #define ACLK_RKVDEC_PRE 197
86 #define ACLK_RGA_PRE 198
87 #define ACLK_IEP_PRE 199
88 #define ACLK_HDCP_PRE 200
89 #define ACLK_VOP_PRE 201
90 #define ACLK_VPU 202
91 #define ACLK_RKVDEC 203
92 #define ACLK_IEP 204
93 #define ACLK_RGA 205
94 #define ACLK_HDCP 206
95 #define ACLK_PERI 210
96 #define ACLK_VOP 211
97 #define ACLK_GMAC 212
98 #define ACLK_GPU 213
100 /* pclk gates */
101 #define PCLK_GPIO0 320
102 #define PCLK_GPIO1 321
103 #define PCLK_GPIO2 322
104 #define PCLK_GPIO3 323
105 #define PCLK_VIO_H2P 324
106 #define PCLK_HDCP 325
107 #define PCLK_EFUSE_1024 326
108 #define PCLK_EFUSE_256 327
109 #define PCLK_GRF 329
110 #define PCLK_I2C0 332
111 #define PCLK_I2C1 333
112 #define PCLK_I2C2 334
113 #define PCLK_I2C3 335
114 #define PCLK_SPI0 338
115 #define PCLK_UART0 341
116 #define PCLK_UART1 342
117 #define PCLK_UART2 343
118 #define PCLK_TSADC 344
119 #define PCLK_PWM 350
120 #define PCLK_TIMER 353
121 #define PCLK_CPU 354
122 #define PCLK_PERI 363
123 #define PCLK_HDMI_CTRL 364
124 #define PCLK_HDMI_PHY 365
125 #define PCLK_GMAC 367
127 /* hclk gates */
128 #define HCLK_I2S0_8CH 442
129 #define HCLK_I2S1_8CH 443
130 #define HCLK_I2S2_2CH 444
131 #define HCLK_SPDIF_8CH 445
132 #define HCLK_VOP 452
133 #define HCLK_NANDC 453
134 #define HCLK_SDMMC 456
135 #define HCLK_SDIO 457
136 #define HCLK_EMMC 459
137 #define HCLK_CPU 460
138 #define HCLK_VPU_PRE 461
139 #define HCLK_RKVDEC_PRE 462
140 #define HCLK_VIO_PRE 463
141 #define HCLK_VPU 464
142 #define HCLK_RKVDEC 465
143 #define HCLK_VIO 466
144 #define HCLK_RGA 467
145 #define HCLK_IEP 468
146 #define HCLK_VIO_H2P 469
147 #define HCLK_HDCP_MMU 470
148 #define HCLK_HOST0 471
149 #define HCLK_HOST1 472
150 #define HCLK_HOST2 473
151 #define HCLK_OTG 474
152 #define HCLK_TSP 475
153 #define HCLK_M_CRYPTO 476
154 #define HCLK_S_CRYPTO 477
155 #define HCLK_PERI 478
157 #define CLK_NR_CLKS (HCLK_PERI + 1)
159 /* soft-reset indices */
160 #define SRST_CORE0_PO 0
161 #define SRST_CORE1_PO 1
162 #define SRST_CORE2_PO 2
163 #define SRST_CORE3_PO 3
164 #define SRST_CORE0 4
165 #define SRST_CORE1 5
166 #define SRST_CORE2 6
167 #define SRST_CORE3 7
168 #define SRST_CORE0_DBG 8
169 #define SRST_CORE1_DBG 9
170 #define SRST_CORE2_DBG 10
171 #define SRST_CORE3_DBG 11
172 #define SRST_TOPDBG 12
173 #define SRST_ACLK_CORE 13
174 #define SRST_NOC 14
175 #define SRST_L2C 15
177 #define SRST_CPUSYS_H 18
178 #define SRST_BUSSYS_H 19
179 #define SRST_SPDIF 20
180 #define SRST_INTMEM 21
181 #define SRST_ROM 22
182 #define SRST_OTG_ADP 23
183 #define SRST_I2S0 24
184 #define SRST_I2S1 25
185 #define SRST_I2S2 26
186 #define SRST_ACODEC_P 27
187 #define SRST_DFIMON 28
188 #define SRST_MSCH 29
189 #define SRST_EFUSE1024 30
190 #define SRST_EFUSE256 31
192 #define SRST_GPIO0 32
193 #define SRST_GPIO1 33
194 #define SRST_GPIO2 34
195 #define SRST_GPIO3 35
196 #define SRST_PERIPH_NOC_A 36
197 #define SRST_PERIPH_NOC_BUS_H 37
198 #define SRST_PERIPH_NOC_P 38
199 #define SRST_UART0 39
200 #define SRST_UART1 40
201 #define SRST_UART2 41
202 #define SRST_PHYNOC 42
203 #define SRST_I2C0 43
204 #define SRST_I2C1 44
205 #define SRST_I2C2 45
206 #define SRST_I2C3 46
208 #define SRST_PWM 48
209 #define SRST_A53_GIC 49
210 #define SRST_DAP 51
211 #define SRST_DAP_NOC 52
212 #define SRST_CRYPTO 53
213 #define SRST_SGRF 54
214 #define SRST_GRF 55
215 #define SRST_GMAC 56
216 #define SRST_PERIPH_NOC_H 58
217 #define SRST_MACPHY 63
219 #define SRST_DMA 64
220 #define SRST_NANDC 68
221 #define SRST_USBOTG 69
222 #define SRST_OTGC 70
223 #define SRST_USBHOST0 71
224 #define SRST_HOST_CTRL0 72
225 #define SRST_USBHOST1 73
226 #define SRST_HOST_CTRL1 74
227 #define SRST_USBHOST2 75
228 #define SRST_HOST_CTRL2 76
229 #define SRST_USBPOR0 77
230 #define SRST_USBPOR1 78
231 #define SRST_DDRMSCH 79
233 #define SRST_SMART_CARD 80
234 #define SRST_SDMMC 81
235 #define SRST_SDIO 82
236 #define SRST_EMMC 83
237 #define SRST_SPI 84
238 #define SRST_TSP_H 85
239 #define SRST_TSP 86
240 #define SRST_TSADC 87
241 #define SRST_DDRPHY 88
242 #define SRST_DDRPHY_P 89
243 #define SRST_DDRCTRL 90
244 #define SRST_DDRCTRL_P 91
245 #define SRST_HOST0_ECHI 92
246 #define SRST_HOST1_ECHI 93
247 #define SRST_HOST2_ECHI 94
248 #define SRST_VOP_NOC_A 95
250 #define SRST_HDMI_P 96
251 #define SRST_VIO_ARBI_H 97
252 #define SRST_IEP_NOC_A 98
253 #define SRST_VIO_NOC_H 99
254 #define SRST_VOP_A 100
255 #define SRST_VOP_H 101
256 #define SRST_VOP_D 102
257 #define SRST_UTMI0 103
258 #define SRST_UTMI1 104
259 #define SRST_UTMI2 105
260 #define SRST_UTMI3 106
261 #define SRST_RGA 107
262 #define SRST_RGA_NOC_A 108
263 #define SRST_RGA_A 109
264 #define SRST_RGA_H 110
265 #define SRST_HDCP_A 111
267 #define SRST_VPU_A 112
268 #define SRST_VPU_H 113
269 #define SRST_VPU_NOC_A 116
270 #define SRST_VPU_NOC_H 117
271 #define SRST_RKVDEC_A 118
272 #define SRST_RKVDEC_NOC_A 119
273 #define SRST_RKVDEC_H 120
274 #define SRST_RKVDEC_NOC_H 121
275 #define SRST_RKVDEC_CORE 122
276 #define SRST_RKVDEC_CABAC 123
277 #define SRST_IEP_A 124
278 #define SRST_IEP_H 125
279 #define SRST_GPU_A 126
280 #define SRST_GPU_NOC_A 127
282 #define SRST_CORE_DBG 128
283 #define SRST_DBG_P 129
284 #define SRST_TIMER0 130
285 #define SRST_TIMER1 131
286 #define SRST_TIMER2 132
287 #define SRST_TIMER3 133
288 #define SRST_TIMER4 134
289 #define SRST_TIMER5 135
290 #define SRST_VIO_H2P 136
291 #define SRST_HDMIPHY 139
292 #define SRST_VDAC 140
293 #define SRST_TIMER_6CH_P 141
295 #endif