include/linux/cache.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __LINUX_CACHE_H
   3 #define __LINUX_CACHE_H
   4
   5 #include <uapi/linux/kernel.h>
   6 #include <asm/cache.h>
   7
   8 #ifndef L1_CACHE_ALIGN
   9 #define L1_CACHE_ALIGN(x) __ALIGN_KERNEL(x, L1_CACHE_BYTES)
  10 #endif
  11
  12 #ifndef SMP_CACHE_BYTES
  13 #define SMP_CACHE_BYTES L1_CACHE_BYTES
  14 #endif
  15
  16 /*
  17  * __read_mostly is used to keep rarely changing variables out of frequently
  18  * updated cachelines. If an architecture doesn't support it, ignore the
  19  * hint.
  20  */
  21 #ifndef __read_mostly
  22 #define __read_mostly
  23 #endif
  24
  25 /*
  26  * __ro_after_init is used to mark things that are read-only after init (i.e.
  27  * after mark_rodata_ro() has been called). These are effectively read-only,
  28  * but may get written to during init, so can't live in .rodata (via "const").
  29  */
  30 #ifndef __ro_after_init
  31 #define __ro_after_init __attribute__((__section__(".data..ro_after_init")))
  32 #endif
  33
  34 #ifndef ____cacheline_aligned
  35 #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
  36 #endif
  37
  38 #ifndef ____cacheline_aligned_in_smp
  39 #ifdef CONFIG_SMP
  40 #define ____cacheline_aligned_in_smp ____cacheline_aligned
  41 #else
  42 #define ____cacheline_aligned_in_smp
  43 #endif /* CONFIG_SMP */
  44 #endif
  45
  46 #ifndef __cacheline_aligned
  47 #define __cacheline_aligned                                     \
  48   __attribute__((__aligned__(SMP_CACHE_BYTES),                  \
  49                  __section__(".data..cacheline_aligned")))
  50 #endif /* __cacheline_aligned */
  51
  52 #ifndef __cacheline_aligned_in_smp
  53 #ifdef CONFIG_SMP
  54 #define __cacheline_aligned_in_smp __cacheline_aligned
  55 #else
  56 #define __cacheline_aligned_in_smp
  57 #endif /* CONFIG_SMP */
  58 #endif
  59
  60 /*
  61  * The maximum alignment needed for some critical structures
  62  * These could be inter-node cacheline sizes/L3 cacheline
  63  * size etc.  Define this in asm/cache.h for your arch
  64  */
  65 #ifndef INTERNODE_CACHE_SHIFT
  66 #define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
  67 #endif
  68
  69 #if !defined(____cacheline_internodealigned_in_smp)
  70 #if defined(CONFIG_SMP)
  71 #define ____cacheline_internodealigned_in_smp \
  72         __attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))
  73 #else
  74 #define ____cacheline_internodealigned_in_smp
  75 #endif
  76 #endif
  77
  78 #ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
  79 #define cache_line_size()       L1_CACHE_BYTES
  80 #endif
  81
  82 #endif /* __LINUX_CACHE_H */