include/linux/gpio/driver.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __LINUX_GPIO_DRIVER_H
   3 #define __LINUX_GPIO_DRIVER_H
   4
   5 #include <linux/device.h>
   6 #include <linux/types.h>
   7 #include <linux/irq.h>
   8 #include <linux/irqchip/chained_irq.h>
   9 #include <linux/irqdomain.h>
  10 #include <linux/lockdep.h>
  11 #include <linux/pinctrl/pinctrl.h>
  12 #include <linux/pinctrl/pinconf-generic.h>
  13
  14 struct gpio_desc;
  15 struct of_phandle_args;
  16 struct device_node;
  17 struct seq_file;
  18 struct gpio_device;
  19 struct module;
  20
  21 #ifdef CONFIG_GPIOLIB
  22
  23 #ifdef CONFIG_GPIOLIB_IRQCHIP
  24 /**
  25  * struct gpio_irq_chip - GPIO interrupt controller
  26  */
  27 struct gpio_irq_chip {
  28         /**
  29          * @chip:
  30          *
  31          * GPIO IRQ chip implementation, provided by GPIO driver.
  32          */
  33         struct irq_chip *chip;
  34
  35         /**
  36          * @domain:
  37          *
  38          * Interrupt translation domain; responsible for mapping between GPIO
  39          * hwirq number and Linux IRQ number.
  40          */
  41         struct irq_domain *domain;
  42
  43         /**
  44          * @domain_ops:
  45          *
  46          * Table of interrupt domain operations for this IRQ chip.
  47          */
  48         const struct irq_domain_ops *domain_ops;
  49
  50         /**
  51          * @handler:
  52          *
  53          * The IRQ handler to use (often a predefined IRQ core function) for
  54          * GPIO IRQs, provided by GPIO driver.
  55          */
  56         irq_flow_handler_t handler;
  57
  58         /**
  59          * @default_type:
  60          *
  61          * Default IRQ triggering type applied during GPIO driver
  62          * initialization, provided by GPIO driver.
  63          */
  64         unsigned int default_type;
  65
  66         /**
  67          * @lock_key:
  68          *
  69          * Per GPIO IRQ chip lockdep classes.
  70          */
  71         struct lock_class_key *lock_key;
  72         struct lock_class_key *request_key;
  73
  74         /**
  75          * @parent_handler:
  76          *
  77          * The interrupt handler for the GPIO chip's parent interrupts, may be
  78          * NULL if the parent interrupts are nested rather than cascaded.
  79          */
  80         irq_flow_handler_t parent_handler;
  81
  82         /**
  83          * @parent_handler_data:
  84          *
  85          * Data associated, and passed to, the handler for the parent
  86          * interrupt.
  87          */
  88         void *parent_handler_data;
  89
  90         /**
  91          * @num_parents:
  92          *
  93          * The number of interrupt parents of a GPIO chip.
  94          */
  95         unsigned int num_parents;
  96
  97         /**
  98          * @parents:
  99          *
 100          * A list of interrupt parents of a GPIO chip. This is owned by the
 101          * driver, so the core will only reference this list, not modify it.
 102          */
 103         unsigned int *parents;
 104
 105         /**
 106          * @map:
 107          *
 108          * A list of interrupt parents for each line of a GPIO chip.
 109          */
 110         unsigned int *map;
 111
 112         /**
 113          * @threaded:
 114          *
 115          * True if set the interrupt handling uses nested threads.
 116          */
 117         bool threaded;
 118
 119         /**
 120          * @need_valid_mask:
 121          *
 122          * If set core allocates @valid_mask with all bits set to one.
 123          */
 124         bool need_valid_mask;
 125
 126         /**
 127          * @valid_mask:
 128          *
 129          * If not %NULL holds bitmask of GPIOs which are valid to be included
 130          * in IRQ domain of the chip.
 131          */
 132         unsigned long *valid_mask;
 133
 134         /**
 135          * @first:
 136          *
 137          * Required for static IRQ allocation. If set, irq_domain_add_simple()
 138          * will allocate and map all IRQs during initialization.
 139          */
 140         unsigned int first;
 141 };
 142
 143 static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)
 144 {
 145         return container_of(chip, struct gpio_irq_chip, chip);
 146 }
 147 #endif
 148
 149 /**
 150  * struct gpio_chip - abstract a GPIO controller
 151  * @label: a functional name for the GPIO device, such as a part
 152  *      number or the name of the SoC IP-block implementing it.
 153  * @gpiodev: the internal state holder, opaque struct
 154  * @parent: optional parent device providing the GPIOs
 155  * @owner: helps prevent removal of modules exporting active GPIOs
 156  * @request: optional hook for chip-specific activation, such as
 157  *      enabling module power and clock; may sleep
 158  * @free: optional hook for chip-specific deactivation, such as
 159  *      disabling module power and clock; may sleep
 160  * @get_direction: returns direction for signal "offset", 0=out, 1=in,
 161  *      (same as GPIOF_DIR_XXX), or negative error
 162  * @direction_input: configures signal "offset" as input, or returns error
 163  * @direction_output: configures signal "offset" as output, or returns error
 164  * @get: returns value for signal "offset", 0=low, 1=high, or negative error
 165  * @get_multiple: reads values for multiple signals defined by "mask" and
 166  *      stores them in "bits", returns 0 on success or negative error
 167  * @set: assigns output value for signal "offset"
 168  * @set_multiple: assigns output values for multiple signals defined by "mask"
 169  * @set_config: optional hook for all kinds of settings. Uses the same
 170  *      packed config format as generic pinconf.
 171  * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
 172  *      implementation may not sleep
 173  * @dbg_show: optional routine to show contents in debugfs; default code
 174  *      will be used when this is omitted, but custom code can show extra
 175  *      state (such as pullup/pulldown configuration).
 176  * @base: identifies the first GPIO number handled by this chip;
 177  *      or, if negative during registration, requests dynamic ID allocation.
 178  *      DEPRECATION: providing anything non-negative and nailing the base
 179  *      offset of GPIO chips is deprecated. Please pass -1 as base to
 180  *      let gpiolib select the chip base in all possible cases. We want to
 181  *      get rid of the static GPIO number space in the long run.
 182  * @ngpio: the number of GPIOs handled by this controller; the last GPIO
 183  *      handled is (base + ngpio - 1).
 184  * @names: if set, must be an array of strings to use as alternative
 185  *      names for the GPIOs in this chip. Any entry in the array
 186  *      may be NULL if there is no alias for the GPIO, however the
 187  *      array must be @ngpio entries long.  A name can include a single printk
 188  *      format specifier for an unsigned int.  It is substituted by the actual
 189  *      number of the gpio.
 190  * @can_sleep: flag must be set iff get()/set() methods sleep, as they
 191  *      must while accessing GPIO expander chips over I2C or SPI. This
 192  *      implies that if the chip supports IRQs, these IRQs need to be threaded
 193  *      as the chip access may sleep when e.g. reading out the IRQ status
 194  *      registers.
 195  * @read_reg: reader function for generic GPIO
 196  * @write_reg: writer function for generic GPIO
 197  * @be_bits: if the generic GPIO has big endian bit order (bit 31 is representing
 198  *      line 0, bit 30 is line 1 ... bit 0 is line 31) this is set to true by the
 199  *      generic GPIO core. It is for internal housekeeping only.
 200  * @reg_dat: data (in) register for generic GPIO
 201  * @reg_set: output set register (out=high) for generic GPIO
 202  * @reg_clr: output clear register (out=low) for generic GPIO
 203  * @reg_dir: direction setting register for generic GPIO
 204  * @bgpio_bits: number of register bits used for a generic GPIO i.e.
 205  *      <register width> * 8
 206  * @bgpio_lock: used to lock chip->bgpio_data. Also, this is needed to keep
 207  *      shadowed and real data registers writes together.
 208  * @bgpio_data: shadowed data register for generic GPIO to clear/set bits
 209  *      safely.
 210  * @bgpio_dir: shadowed direction register for generic GPIO to clear/set
 211  *      direction safely.
 212  *
 213  * A gpio_chip can help platforms abstract various sources of GPIOs so
 214  * they can all be accessed through a common programing interface.
 215  * Example sources would be SOC controllers, FPGAs, multifunction
 216  * chips, dedicated GPIO expanders, and so on.
 217  *
 218  * Each chip controls a number of signals, identified in method calls
 219  * by "offset" values in the range 0..(@ngpio - 1).  When those signals
 220  * are referenced through calls like gpio_get_value(gpio), the offset
 221  * is calculated by subtracting @base from the gpio number.
 222  */
 223 struct gpio_chip {
 224         const char              *label;
 225         struct gpio_device      *gpiodev;
 226         struct device           *parent;
 227         struct module           *owner;
 228
 229         int                     (*request)(struct gpio_chip *chip,
 230                                                 unsigned offset);
 231         void                    (*free)(struct gpio_chip *chip,
 232                                                 unsigned offset);
 233         int                     (*get_direction)(struct gpio_chip *chip,
 234                                                 unsigned offset);
 235         int                     (*direction_input)(struct gpio_chip *chip,
 236                                                 unsigned offset);
 237         int                     (*direction_output)(struct gpio_chip *chip,
 238                                                 unsigned offset, int value);
 239         int                     (*get)(struct gpio_chip *chip,
 240                                                 unsigned offset);
 241         int                     (*get_multiple)(struct gpio_chip *chip,
 242                                                 unsigned long *mask,
 243                                                 unsigned long *bits);
 244         void                    (*set)(struct gpio_chip *chip,
 245                                                 unsigned offset, int value);
 246         void                    (*set_multiple)(struct gpio_chip *chip,
 247                                                 unsigned long *mask,
 248                                                 unsigned long *bits);
 249         int                     (*set_config)(struct gpio_chip *chip,
 250                                               unsigned offset,
 251                                               unsigned long config);
 252         int                     (*to_irq)(struct gpio_chip *chip,
 253                                                 unsigned offset);
 254
 255         void                    (*dbg_show)(struct seq_file *s,
 256                                                 struct gpio_chip *chip);
 257         int                     base;
 258         u16                     ngpio;
 259         const char              *const *names;
 260         bool                    can_sleep;
 261
 262 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
 263         unsigned long (*read_reg)(void __iomem *reg);
 264         void (*write_reg)(void __iomem *reg, unsigned long data);
 265         bool be_bits;
 266         void __iomem *reg_dat;
 267         void __iomem *reg_set;
 268         void __iomem *reg_clr;
 269         void __iomem *reg_dir;
 270         int bgpio_bits;
 271         spinlock_t bgpio_lock;
 272         unsigned long bgpio_data;
 273         unsigned long bgpio_dir;
 274 #endif
 275
 276 #ifdef CONFIG_GPIOLIB_IRQCHIP
 277         /*
 278          * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib
 279          * to handle IRQs for most practical cases.
 280          */
 281
 282         /**
 283          * @irq:
 284          *
 285          * Integrates interrupt chip functionality with the GPIO chip. Can be
 286          * used to handle IRQs for most practical cases.
 287          */
 288         struct gpio_irq_chip irq;
 289 #endif
 290
 291 #if defined(CONFIG_OF_GPIO)
 292         /*
 293          * If CONFIG_OF is enabled, then all GPIO controllers described in the
 294          * device tree automatically may have an OF translation
 295          */
 296
 297         /**
 298          * @of_node:
 299          *
 300          * Pointer to a device tree node representing this GPIO controller.
 301          */
 302         struct device_node *of_node;
 303
 304         /**
 305          * @of_gpio_n_cells:
 306          *
 307          * Number of cells used to form the GPIO specifier.
 308          */
 309         unsigned int of_gpio_n_cells;
 310
 311         /**
 312          * @of_xlate:
 313          *
 314          * Callback to translate a device tree GPIO specifier into a chip-
 315          * relative GPIO number and flags.
 316          */
 317         int (*of_xlate)(struct gpio_chip *gc,
 318                         const struct of_phandle_args *gpiospec, u32 *flags);
 319 #endif
 320 };
 321
 322 extern const char *gpiochip_is_requested(struct gpio_chip *chip,
 323                         unsigned offset);
 324
 325 /* add/remove chips */
 326 extern int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
 327                                       struct lock_class_key *lock_key,
 328                                       struct lock_class_key *request_key);
 329
 330 /**
 331  * gpiochip_add_data() - register a gpio_chip
 332  * @chip: the chip to register, with chip->base initialized
 333  * @data: driver-private data associated with this chip
 334  *
 335  * Context: potentially before irqs will work
 336  *
 337  * When gpiochip_add_data() is called very early during boot, so that GPIOs
 338  * can be freely used, the chip->parent device must be registered before
 339  * the gpio framework's arch_initcall().  Otherwise sysfs initialization
 340  * for GPIOs will fail rudely.
 341  *
 342  * gpiochip_add_data() must only be called after gpiolib initialization,
 343  * ie after core_initcall().
 344  *
 345  * If chip->base is negative, this requests dynamic assignment of
 346  * a range of valid GPIOs.
 347  *
 348  * Returns:
 349  * A negative errno if the chip can't be registered, such as because the
 350  * chip->base is invalid or already associated with a different chip.
 351  * Otherwise it returns zero as a success code.
 352  */
 353 #ifdef CONFIG_LOCKDEP
 354 #define gpiochip_add_data(chip, data) ({                \
 355                 static struct lock_class_key lock_key;  \
 356                 static struct lock_class_key request_key;         \
 357                 gpiochip_add_data_with_key(chip, data, &lock_key, \
 358                                            &request_key);         \
 359         })
 360 #else
 361 #define gpiochip_add_data(chip, data) gpiochip_add_data_with_key(chip, data, NULL, NULL)
 362 #endif
 363
 364 static inline int gpiochip_add(struct gpio_chip *chip)
 365 {
 366         return gpiochip_add_data(chip, NULL);
 367 }
 368 extern void gpiochip_remove(struct gpio_chip *chip);
 369 extern int devm_gpiochip_add_data(struct device *dev, struct gpio_chip *chip,
 370                                   void *data);
 371 extern void devm_gpiochip_remove(struct device *dev, struct gpio_chip *chip);
 372
 373 extern struct gpio_chip *gpiochip_find(void *data,
 374                               int (*match)(struct gpio_chip *chip, void *data));
 375
 376 /* lock/unlock as IRQ */
 377 int gpiochip_lock_as_irq(struct gpio_chip *chip, unsigned int offset);
 378 void gpiochip_unlock_as_irq(struct gpio_chip *chip, unsigned int offset);
 379 bool gpiochip_line_is_irq(struct gpio_chip *chip, unsigned int offset);
 380
 381 /* Line status inquiry for drivers */
 382 bool gpiochip_line_is_open_drain(struct gpio_chip *chip, unsigned int offset);
 383 bool gpiochip_line_is_open_source(struct gpio_chip *chip, unsigned int offset);
 384
 385 /* Sleep persistence inquiry for drivers */
 386 bool gpiochip_line_is_persistent(struct gpio_chip *chip, unsigned int offset);
 387
 388 /* get driver data */
 389 void *gpiochip_get_data(struct gpio_chip *chip);
 390
 391 struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc);
 392
 393 struct bgpio_pdata {
 394         const char *label;
 395         int base;
 396         int ngpio;
 397 };
 398
 399 #if IS_ENABLED(CONFIG_GPIO_GENERIC)
 400
 401 int bgpio_init(struct gpio_chip *gc, struct device *dev,
 402                unsigned long sz, void __iomem *dat, void __iomem *set,
 403                void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
 404                unsigned long flags);
 405
 406 #define BGPIOF_BIG_ENDIAN               BIT(0)
 407 #define BGPIOF_UNREADABLE_REG_SET       BIT(1) /* reg_set is unreadable */
 408 #define BGPIOF_UNREADABLE_REG_DIR       BIT(2) /* reg_dir is unreadable */
 409 #define BGPIOF_BIG_ENDIAN_BYTE_ORDER    BIT(3)
 410 #define BGPIOF_READ_OUTPUT_REG_SET      BIT(4) /* reg_set stores output value */
 411 #define BGPIOF_NO_OUTPUT                BIT(5) /* only input */
 412
 413 #endif
 414
 415 #ifdef CONFIG_GPIOLIB_IRQCHIP
 416
 417 int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
 418                      irq_hw_number_t hwirq);
 419 void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq);
 420
 421 void gpiochip_set_chained_irqchip(struct gpio_chip *gpiochip,
 422                 struct irq_chip *irqchip,
 423                 unsigned int parent_irq,
 424                 irq_flow_handler_t parent_handler);
 425
 426 void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,
 427                 struct irq_chip *irqchip,
 428                 unsigned int parent_irq);
 429
 430 int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,
 431                              struct irq_chip *irqchip,
 432                              unsigned int first_irq,
 433                              irq_flow_handler_t handler,
 434                              unsigned int type,
 435                              bool threaded,
 436                              struct lock_class_key *lock_key,
 437                              struct lock_class_key *request_key);
 438
 439 bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
 440                                 unsigned int offset);
 441
 442 #ifdef CONFIG_LOCKDEP
 443
 444 /*
 445  * Lockdep requires that each irqchip instance be created with a
 446  * unique key so as to avoid unnecessary warnings. This upfront
 447  * boilerplate static inlines provides such a key for each
 448  * unique instance.
 449  */
 450 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
 451                                        struct irq_chip *irqchip,
 452                                        unsigned int first_irq,
 453                                        irq_flow_handler_t handler,
 454                                        unsigned int type)
 455 {
 456         static struct lock_class_key lock_key;
 457         static struct lock_class_key request_key;
 458
 459         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
 460                                         handler, type, false,
 461                                         &lock_key, &request_key);
 462 }
 463
 464 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
 465                           struct irq_chip *irqchip,
 466                           unsigned int first_irq,
 467                           irq_flow_handler_t handler,
 468                           unsigned int type)
 469 {
 470
 471         static struct lock_class_key lock_key;
 472         static struct lock_class_key request_key;
 473
 474         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
 475                                         handler, type, true,
 476                                         &lock_key, &request_key);
 477 }
 478 #else
 479 static inline int gpiochip_irqchip_add(struct gpio_chip *gpiochip,
 480                                        struct irq_chip *irqchip,
 481                                        unsigned int first_irq,
 482                                        irq_flow_handler_t handler,
 483                                        unsigned int type)
 484 {
 485         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
 486                                         handler, type, false, NULL, NULL);
 487 }
 488
 489 static inline int gpiochip_irqchip_add_nested(struct gpio_chip *gpiochip,
 490                           struct irq_chip *irqchip,
 491                           unsigned int first_irq,
 492                           irq_flow_handler_t handler,
 493                           unsigned int type)
 494 {
 495         return gpiochip_irqchip_add_key(gpiochip, irqchip, first_irq,
 496                                         handler, type, true, NULL, NULL);
 497 }
 498 #endif /* CONFIG_LOCKDEP */
 499
 500 #endif /* CONFIG_GPIOLIB_IRQCHIP */
 501
 502 int gpiochip_generic_request(struct gpio_chip *chip, unsigned offset);
 503 void gpiochip_generic_free(struct gpio_chip *chip, unsigned offset);
 504 int gpiochip_generic_config(struct gpio_chip *chip, unsigned offset,
 505                             unsigned long config);
 506
 507 #ifdef CONFIG_PINCTRL
 508
 509 /**
 510  * struct gpio_pin_range - pin range controlled by a gpio chip
 511  * @node: list for maintaining set of pin ranges, used internally
 512  * @pctldev: pinctrl device which handles corresponding pins
 513  * @range: actual range of pins controlled by a gpio controller
 514  */
 515 struct gpio_pin_range {
 516         struct list_head node;
 517         struct pinctrl_dev *pctldev;
 518         struct pinctrl_gpio_range range;
 519 };
 520
 521 int gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
 522                            unsigned int gpio_offset, unsigned int pin_offset,
 523                            unsigned int npins);
 524 int gpiochip_add_pingroup_range(struct gpio_chip *chip,
 525                         struct pinctrl_dev *pctldev,
 526                         unsigned int gpio_offset, const char *pin_group);
 527 void gpiochip_remove_pin_ranges(struct gpio_chip *chip);
 528
 529 #else
 530
 531 static inline int
 532 gpiochip_add_pin_range(struct gpio_chip *chip, const char *pinctl_name,
 533                        unsigned int gpio_offset, unsigned int pin_offset,
 534                        unsigned int npins)
 535 {
 536         return 0;
 537 }
 538 static inline int
 539 gpiochip_add_pingroup_range(struct gpio_chip *chip,
 540                         struct pinctrl_dev *pctldev,
 541                         unsigned int gpio_offset, const char *pin_group)
 542 {
 543         return 0;
 544 }
 545
 546 static inline void
 547 gpiochip_remove_pin_ranges(struct gpio_chip *chip)
 548 {
 549 }
 550
 551 #endif /* CONFIG_PINCTRL */
 552
 553 struct gpio_desc *gpiochip_request_own_desc(struct gpio_chip *chip, u16 hwnum,
 554                                             const char *label);
 555 void gpiochip_free_own_desc(struct gpio_desc *desc);
 556
 557 #else /* CONFIG_GPIOLIB */
 558
 559 static inline struct gpio_chip *gpiod_to_chip(const struct gpio_desc *desc)
 560 {
 561         /* GPIO can never have been requested */
 562         WARN_ON(1);
 563         return ERR_PTR(-ENODEV);
 564 }
 565
 566 #endif /* CONFIG_GPIOLIB */
 567
 568 #endif