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Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[cris-mirror.git] / include / linux / nvme.h
blob4112e2bd747f5828f031e5ac638888d4f38384cd
1 /*
2 * Definitions for the NVM Express interface
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #ifndef _LINUX_NVME_H
16 #define _LINUX_NVME_H
17
18 #include <linux/types.h>
19 #include <linux/uuid.h>
20
21 /* NQN names in commands fields specified one size */
22 #define NVMF_NQN_FIELD_LEN 256
23
24 /* However the max length of a qualified name is another size */
25 #define NVMF_NQN_SIZE 223
26
27 #define NVMF_TRSVCID_SIZE 32
28 #define NVMF_TRADDR_SIZE 256
29 #define NVMF_TSAS_SIZE 256
30
31 #define NVME_DISC_SUBSYS_NAME "nqn.2014-08.org.nvmexpress.discovery"
32
33 #define NVME_RDMA_IP_PORT 4420
34
35 #define NVME_NSID_ALL 0xffffffff
36
37 enum nvme_subsys_type {
38 NVME_NQN_DISC = 1, /* Discovery type target subsystem */
39 NVME_NQN_NVME = 2, /* NVME type target subsystem */
40 };
41
42 /* Address Family codes for Discovery Log Page entry ADRFAM field */
43 enum {
44 NVMF_ADDR_FAMILY_PCI = 0, /* PCIe */
45 NVMF_ADDR_FAMILY_IP4 = 1, /* IP4 */
46 NVMF_ADDR_FAMILY_IP6 = 2, /* IP6 */
47 NVMF_ADDR_FAMILY_IB = 3, /* InfiniBand */
48 NVMF_ADDR_FAMILY_FC = 4, /* Fibre Channel */
49 };
50
51 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
52 enum {
53 NVMF_TRTYPE_RDMA = 1, /* RDMA */
54 NVMF_TRTYPE_FC = 2, /* Fibre Channel */
55 NVMF_TRTYPE_LOOP = 254, /* Reserved for host usage */
56 NVMF_TRTYPE_MAX,
57 };
58
59 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
60 enum {
61 NVMF_TREQ_NOT_SPECIFIED = 0, /* Not specified */
62 NVMF_TREQ_REQUIRED = 1, /* Required */
63 NVMF_TREQ_NOT_REQUIRED = 2, /* Not Required */
64 };
65
66 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
67 * RDMA_QPTYPE field
68 */
69 enum {
70 NVMF_RDMA_QPTYPE_CONNECTED = 1, /* Reliable Connected */
71 NVMF_RDMA_QPTYPE_DATAGRAM = 2, /* Reliable Datagram */
72 };
73
74 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
75 * RDMA_QPTYPE field
76 */
77 enum {
78 NVMF_RDMA_PRTYPE_NOT_SPECIFIED = 1, /* No Provider Specified */
79 NVMF_RDMA_PRTYPE_IB = 2, /* InfiniBand */
80 NVMF_RDMA_PRTYPE_ROCE = 3, /* InfiniBand RoCE */
81 NVMF_RDMA_PRTYPE_ROCEV2 = 4, /* InfiniBand RoCEV2 */
82 NVMF_RDMA_PRTYPE_IWARP = 5, /* IWARP */
83 };
84
85 /* RDMA Connection Management Service Type codes for Discovery Log Page
86 * entry TSAS RDMA_CMS field
87 */
88 enum {
89 NVMF_RDMA_CMS_RDMA_CM = 1, /* Sockets based endpoint addressing */
90 };
91
92 #define NVME_AQ_DEPTH 32
93 #define NVME_NR_AEN_COMMANDS 1
94 #define NVME_AQ_BLK_MQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
95
96 /*
97 * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
98 * NVM-Express 1.2 specification, section 4.1.2.
99 */
100 #define NVME_AQ_MQ_TAG_DEPTH (NVME_AQ_BLK_MQ_DEPTH - 1)
101
102 enum {
103 NVME_REG_CAP = 0x0000, /* Controller Capabilities */
104 NVME_REG_VS = 0x0008, /* Version */
105 NVME_REG_INTMS = 0x000c, /* Interrupt Mask Set */
106 NVME_REG_INTMC = 0x0010, /* Interrupt Mask Clear */
107 NVME_REG_CC = 0x0014, /* Controller Configuration */
108 NVME_REG_CSTS = 0x001c, /* Controller Status */
109 NVME_REG_NSSR = 0x0020, /* NVM Subsystem Reset */
110 NVME_REG_AQA = 0x0024, /* Admin Queue Attributes */
111 NVME_REG_ASQ = 0x0028, /* Admin SQ Base Address */
112 NVME_REG_ACQ = 0x0030, /* Admin CQ Base Address */
113 NVME_REG_CMBLOC = 0x0038, /* Controller Memory Buffer Location */
114 NVME_REG_CMBSZ = 0x003c, /* Controller Memory Buffer Size */
115 NVME_REG_DBS = 0x1000, /* SQ 0 Tail Doorbell */
116 };
117
118 #define NVME_CAP_MQES(cap) ((cap) & 0xffff)
119 #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
120 #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
121 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
122 #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
123 #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
124
125 #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7)
126 #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff)
127
128 enum {
129 NVME_CMBSZ_SQS = 1 << 0,
130 NVME_CMBSZ_CQS = 1 << 1,
131 NVME_CMBSZ_LISTS = 1 << 2,
132 NVME_CMBSZ_RDS = 1 << 3,
133 NVME_CMBSZ_WDS = 1 << 4,
134
135 NVME_CMBSZ_SZ_SHIFT = 12,
136 NVME_CMBSZ_SZ_MASK = 0xfffff,
137
138 NVME_CMBSZ_SZU_SHIFT = 8,
139 NVME_CMBSZ_SZU_MASK = 0xf,
140 };
141
142 /*
143 * Submission and Completion Queue Entry Sizes for the NVM command set.
144 * (In bytes and specified as a power of two (2^n)).
145 */
146 #define NVME_NVM_IOSQES 6
147 #define NVME_NVM_IOCQES 4
148
149 enum {
150 NVME_CC_ENABLE = 1 << 0,
151 NVME_CC_CSS_NVM = 0 << 4,
152 NVME_CC_EN_SHIFT = 0,
153 NVME_CC_CSS_SHIFT = 4,
154 NVME_CC_MPS_SHIFT = 7,
155 NVME_CC_AMS_SHIFT = 11,
156 NVME_CC_SHN_SHIFT = 14,
157 NVME_CC_IOSQES_SHIFT = 16,
158 NVME_CC_IOCQES_SHIFT = 20,
159 NVME_CC_AMS_RR = 0 << NVME_CC_AMS_SHIFT,
160 NVME_CC_AMS_WRRU = 1 << NVME_CC_AMS_SHIFT,
161 NVME_CC_AMS_VS = 7 << NVME_CC_AMS_SHIFT,
162 NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
163 NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
164 NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
165 NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
166 NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
167 NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
168 NVME_CSTS_RDY = 1 << 0,
169 NVME_CSTS_CFS = 1 << 1,
170 NVME_CSTS_NSSRO = 1 << 4,
171 NVME_CSTS_PP = 1 << 5,
172 NVME_CSTS_SHST_NORMAL = 0 << 2,
173 NVME_CSTS_SHST_OCCUR = 1 << 2,
174 NVME_CSTS_SHST_CMPLT = 2 << 2,
175 NVME_CSTS_SHST_MASK = 3 << 2,
176 };
177
178 struct nvme_id_power_state {
179 __le16 max_power; /* centiwatts */
180 __u8 rsvd2;
181 __u8 flags;
182 __le32 entry_lat; /* microseconds */
183 __le32 exit_lat; /* microseconds */
184 __u8 read_tput;
185 __u8 read_lat;
186 __u8 write_tput;
187 __u8 write_lat;
188 __le16 idle_power;
189 __u8 idle_scale;
190 __u8 rsvd19;
191 __le16 active_power;
192 __u8 active_work_scale;
193 __u8 rsvd23[9];
194 };
195
196 enum {
197 NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
198 NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
199 };
200
201 struct nvme_id_ctrl {
202 __le16 vid;
203 __le16 ssvid;
204 char sn[20];
205 char mn[40];
206 char fr[8];
207 __u8 rab;
208 __u8 ieee[3];
209 __u8 cmic;
210 __u8 mdts;
211 __le16 cntlid;
212 __le32 ver;
213 __le32 rtd3r;
214 __le32 rtd3e;
215 __le32 oaes;
216 __le32 ctratt;
217 __u8 rsvd100[156];
218 __le16 oacs;
219 __u8 acl;
220 __u8 aerl;
221 __u8 frmw;
222 __u8 lpa;
223 __u8 elpe;
224 __u8 npss;
225 __u8 avscc;
226 __u8 apsta;
227 __le16 wctemp;
228 __le16 cctemp;
229 __le16 mtfa;
230 __le32 hmpre;
231 __le32 hmmin;
232 __u8 tnvmcap[16];
233 __u8 unvmcap[16];
234 __le32 rpmbs;
235 __le16 edstt;
236 __u8 dsto;
237 __u8 fwug;
238 __le16 kas;
239 __le16 hctma;
240 __le16 mntmt;
241 __le16 mxtmt;
242 __le32 sanicap;
243 __le32 hmminds;
244 __le16 hmmaxd;
245 __u8 rsvd338[174];
246 __u8 sqes;
247 __u8 cqes;
248 __le16 maxcmd;
249 __le32 nn;
250 __le16 oncs;
251 __le16 fuses;
252 __u8 fna;
253 __u8 vwc;
254 __le16 awun;
255 __le16 awupf;
256 __u8 nvscc;
257 __u8 rsvd531;
258 __le16 acwu;
259 __u8 rsvd534[2];
260 __le32 sgls;
261 __u8 rsvd540[228];
262 char subnqn[256];
263 __u8 rsvd1024[768];
264 __le32 ioccsz;
265 __le32 iorcsz;
266 __le16 icdoff;
267 __u8 ctrattr;
268 __u8 msdbd;
269 __u8 rsvd1804[244];
270 struct nvme_id_power_state psd[32];
271 __u8 vs[1024];
272 };
273
274 enum {
275 NVME_CTRL_ONCS_COMPARE = 1 << 0,
276 NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
277 NVME_CTRL_ONCS_DSM = 1 << 2,
278 NVME_CTRL_ONCS_WRITE_ZEROES = 1 << 3,
279 NVME_CTRL_ONCS_TIMESTAMP = 1 << 6,
280 NVME_CTRL_VWC_PRESENT = 1 << 0,
281 NVME_CTRL_OACS_SEC_SUPP = 1 << 0,
282 NVME_CTRL_OACS_DIRECTIVES = 1 << 5,
283 NVME_CTRL_OACS_DBBUF_SUPP = 1 << 8,
284 NVME_CTRL_LPA_CMD_EFFECTS_LOG = 1 << 1,
285 };
286
287 struct nvme_lbaf {
288 __le16 ms;
289 __u8 ds;
290 __u8 rp;
291 };
292
293 struct nvme_id_ns {
294 __le64 nsze;
295 __le64 ncap;
296 __le64 nuse;
297 __u8 nsfeat;
298 __u8 nlbaf;
299 __u8 flbas;
300 __u8 mc;
301 __u8 dpc;
302 __u8 dps;
303 __u8 nmic;
304 __u8 rescap;
305 __u8 fpi;
306 __u8 rsvd33;
307 __le16 nawun;
308 __le16 nawupf;
309 __le16 nacwu;
310 __le16 nabsn;
311 __le16 nabo;
312 __le16 nabspf;
313 __le16 noiob;
314 __u8 nvmcap[16];
315 __u8 rsvd64[40];
316 __u8 nguid[16];
317 __u8 eui64[8];
318 struct nvme_lbaf lbaf[16];
319 __u8 rsvd192[192];
320 __u8 vs[3712];
321 };
322
323 enum {
324 NVME_ID_CNS_NS = 0x00,
325 NVME_ID_CNS_CTRL = 0x01,
326 NVME_ID_CNS_NS_ACTIVE_LIST = 0x02,
327 NVME_ID_CNS_NS_DESC_LIST = 0x03,
328 NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
329 NVME_ID_CNS_NS_PRESENT = 0x11,
330 NVME_ID_CNS_CTRL_NS_LIST = 0x12,
331 NVME_ID_CNS_CTRL_LIST = 0x13,
332 };
333
334 enum {
335 NVME_DIR_IDENTIFY = 0x00,
336 NVME_DIR_STREAMS = 0x01,
337 NVME_DIR_SND_ID_OP_ENABLE = 0x01,
338 NVME_DIR_SND_ST_OP_REL_ID = 0x01,
339 NVME_DIR_SND_ST_OP_REL_RSC = 0x02,
340 NVME_DIR_RCV_ID_OP_PARAM = 0x01,
341 NVME_DIR_RCV_ST_OP_PARAM = 0x01,
342 NVME_DIR_RCV_ST_OP_STATUS = 0x02,
343 NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
344 NVME_DIR_ENDIR = 0x01,
345 };
346
347 enum {
348 NVME_NS_FEAT_THIN = 1 << 0,
349 NVME_NS_FLBAS_LBA_MASK = 0xf,
350 NVME_NS_FLBAS_META_EXT = 0x10,
351 NVME_LBAF_RP_BEST = 0,
352 NVME_LBAF_RP_BETTER = 1,
353 NVME_LBAF_RP_GOOD = 2,
354 NVME_LBAF_RP_DEGRADED = 3,
355 NVME_NS_DPC_PI_LAST = 1 << 4,
356 NVME_NS_DPC_PI_FIRST = 1 << 3,
357 NVME_NS_DPC_PI_TYPE3 = 1 << 2,
358 NVME_NS_DPC_PI_TYPE2 = 1 << 1,
359 NVME_NS_DPC_PI_TYPE1 = 1 << 0,
360 NVME_NS_DPS_PI_FIRST = 1 << 3,
361 NVME_NS_DPS_PI_MASK = 0x7,
362 NVME_NS_DPS_PI_TYPE1 = 1,
363 NVME_NS_DPS_PI_TYPE2 = 2,
364 NVME_NS_DPS_PI_TYPE3 = 3,
365 };
366
367 struct nvme_ns_id_desc {
368 __u8 nidt;
369 __u8 nidl;
370 __le16 reserved;
371 };
372
373 #define NVME_NIDT_EUI64_LEN 8
374 #define NVME_NIDT_NGUID_LEN 16
375 #define NVME_NIDT_UUID_LEN 16
376
377 enum {
378 NVME_NIDT_EUI64 = 0x01,
379 NVME_NIDT_NGUID = 0x02,
380 NVME_NIDT_UUID = 0x03,
381 };
382
383 struct nvme_smart_log {
384 __u8 critical_warning;
385 __u8 temperature[2];
386 __u8 avail_spare;
387 __u8 spare_thresh;
388 __u8 percent_used;
389 __u8 rsvd6[26];
390 __u8 data_units_read[16];
391 __u8 data_units_written[16];
392 __u8 host_reads[16];
393 __u8 host_writes[16];
394 __u8 ctrl_busy_time[16];
395 __u8 power_cycles[16];
396 __u8 power_on_hours[16];
397 __u8 unsafe_shutdowns[16];
398 __u8 media_errors[16];
399 __u8 num_err_log_entries[16];
400 __le32 warning_temp_time;
401 __le32 critical_comp_time;
402 __le16 temp_sensor[8];
403 __u8 rsvd216[296];
404 };
405
406 struct nvme_fw_slot_info_log {
407 __u8 afi;
408 __u8 rsvd1[7];
409 __le64 frs[7];
410 __u8 rsvd64[448];
411 };
412
413 enum {
414 NVME_CMD_EFFECTS_CSUPP = 1 << 0,
415 NVME_CMD_EFFECTS_LBCC = 1 << 1,
416 NVME_CMD_EFFECTS_NCC = 1 << 2,
417 NVME_CMD_EFFECTS_NIC = 1 << 3,
418 NVME_CMD_EFFECTS_CCC = 1 << 4,
419 NVME_CMD_EFFECTS_CSE_MASK = 3 << 16,
420 };
421
422 struct nvme_effects_log {
423 __le32 acs[256];
424 __le32 iocs[256];
425 __u8 resv[2048];
426 };
427
428 enum {
429 NVME_SMART_CRIT_SPARE = 1 << 0,
430 NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
431 NVME_SMART_CRIT_RELIABILITY = 1 << 2,
432 NVME_SMART_CRIT_MEDIA = 1 << 3,
433 NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
434 };
435
436 enum {
437 NVME_AER_ERROR = 0,
438 NVME_AER_SMART = 1,
439 NVME_AER_CSS = 6,
440 NVME_AER_VS = 7,
441 NVME_AER_NOTICE_NS_CHANGED = 0x0002,
442 NVME_AER_NOTICE_FW_ACT_STARTING = 0x0102,
443 };
444
445 struct nvme_lba_range_type {
446 __u8 type;
447 __u8 attributes;
448 __u8 rsvd2[14];
449 __u64 slba;
450 __u64 nlb;
451 __u8 guid[16];
452 __u8 rsvd48[16];
453 };
454
455 enum {
456 NVME_LBART_TYPE_FS = 0x01,
457 NVME_LBART_TYPE_RAID = 0x02,
458 NVME_LBART_TYPE_CACHE = 0x03,
459 NVME_LBART_TYPE_SWAP = 0x04,
460
461 NVME_LBART_ATTRIB_TEMP = 1 << 0,
462 NVME_LBART_ATTRIB_HIDE = 1 << 1,
463 };
464
465 struct nvme_reservation_status {
466 __le32 gen;
467 __u8 rtype;
468 __u8 regctl[2];
469 __u8 resv5[2];
470 __u8 ptpls;
471 __u8 resv10[13];
472 struct {
473 __le16 cntlid;
474 __u8 rcsts;
475 __u8 resv3[5];
476 __le64 hostid;
477 __le64 rkey;
478 } regctl_ds[];
479 };
480
481 enum nvme_async_event_type {
482 NVME_AER_TYPE_ERROR = 0,
483 NVME_AER_TYPE_SMART = 1,
484 NVME_AER_TYPE_NOTICE = 2,
485 };
486
487 /* I/O commands */
488
489 enum nvme_opcode {
490 nvme_cmd_flush = 0x00,
491 nvme_cmd_write = 0x01,
492 nvme_cmd_read = 0x02,
493 nvme_cmd_write_uncor = 0x04,
494 nvme_cmd_compare = 0x05,
495 nvme_cmd_write_zeroes = 0x08,
496 nvme_cmd_dsm = 0x09,
497 nvme_cmd_resv_register = 0x0d,
498 nvme_cmd_resv_report = 0x0e,
499 nvme_cmd_resv_acquire = 0x11,
500 nvme_cmd_resv_release = 0x15,
501 };
502
503 /*
504 * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
505 *
506 * @NVME_SGL_FMT_ADDRESS: absolute address of the data block
507 * @NVME_SGL_FMT_OFFSET: relative offset of the in-capsule data block
508 * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
509 * @NVME_SGL_FMT_INVALIDATE: RDMA transport specific remote invalidation
510 * request subtype
511 */
512 enum {
513 NVME_SGL_FMT_ADDRESS = 0x00,
514 NVME_SGL_FMT_OFFSET = 0x01,
515 NVME_SGL_FMT_TRANSPORT_A = 0x0A,
516 NVME_SGL_FMT_INVALIDATE = 0x0f,
517 };
518
519 /*
520 * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
521 *
522 * For struct nvme_sgl_desc:
523 * @NVME_SGL_FMT_DATA_DESC: data block descriptor
524 * @NVME_SGL_FMT_SEG_DESC: sgl segment descriptor
525 * @NVME_SGL_FMT_LAST_SEG_DESC: last sgl segment descriptor
526 *
527 * For struct nvme_keyed_sgl_desc:
528 * @NVME_KEY_SGL_FMT_DATA_DESC: keyed data block descriptor
529 *
530 * Transport-specific SGL types:
531 * @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
532 */
533 enum {
534 NVME_SGL_FMT_DATA_DESC = 0x00,
535 NVME_SGL_FMT_SEG_DESC = 0x02,
536 NVME_SGL_FMT_LAST_SEG_DESC = 0x03,
537 NVME_KEY_SGL_FMT_DATA_DESC = 0x04,
538 NVME_TRANSPORT_SGL_DATA_DESC = 0x05,
539 };
540
541 struct nvme_sgl_desc {
542 __le64 addr;
543 __le32 length;
544 __u8 rsvd[3];
545 __u8 type;
546 };
547
548 struct nvme_keyed_sgl_desc {
549 __le64 addr;
550 __u8 length[3];
551 __u8 key[4];
552 __u8 type;
553 };
554
555 union nvme_data_ptr {
556 struct {
557 __le64 prp1;
558 __le64 prp2;
559 };
560 struct nvme_sgl_desc sgl;
561 struct nvme_keyed_sgl_desc ksgl;
562 };
563
564 /*
565 * Lowest two bits of our flags field (FUSE field in the spec):
566 *
567 * @NVME_CMD_FUSE_FIRST: Fused Operation, first command
568 * @NVME_CMD_FUSE_SECOND: Fused Operation, second command
569 *
570 * Highest two bits in our flags field (PSDT field in the spec):
571 *
572 * @NVME_CMD_PSDT_SGL_METABUF: Use SGLS for this transfer,
573 * If used, MPTR contains addr of single physical buffer (byte aligned).
574 * @NVME_CMD_PSDT_SGL_METASEG: Use SGLS for this transfer,
575 * If used, MPTR contains an address of an SGL segment containing
576 * exactly 1 SGL descriptor (qword aligned).
577 */
578 enum {
579 NVME_CMD_FUSE_FIRST = (1 << 0),
580 NVME_CMD_FUSE_SECOND = (1 << 1),
581
582 NVME_CMD_SGL_METABUF = (1 << 6),
583 NVME_CMD_SGL_METASEG = (1 << 7),
584 NVME_CMD_SGL_ALL = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
585 };
586
587 struct nvme_common_command {
588 __u8 opcode;
589 __u8 flags;
590 __u16 command_id;
591 __le32 nsid;
592 __le32 cdw2[2];
593 __le64 metadata;
594 union nvme_data_ptr dptr;
595 __le32 cdw10[6];
596 };
597
598 struct nvme_rw_command {
599 __u8 opcode;
600 __u8 flags;
601 __u16 command_id;
602 __le32 nsid;
603 __u64 rsvd2;
604 __le64 metadata;
605 union nvme_data_ptr dptr;
606 __le64 slba;
607 __le16 length;
608 __le16 control;
609 __le32 dsmgmt;
610 __le32 reftag;
611 __le16 apptag;
612 __le16 appmask;
613 };
614
615 enum {
616 NVME_RW_LR = 1 << 15,
617 NVME_RW_FUA = 1 << 14,
618 NVME_RW_DSM_FREQ_UNSPEC = 0,
619 NVME_RW_DSM_FREQ_TYPICAL = 1,
620 NVME_RW_DSM_FREQ_RARE = 2,
621 NVME_RW_DSM_FREQ_READS = 3,
622 NVME_RW_DSM_FREQ_WRITES = 4,
623 NVME_RW_DSM_FREQ_RW = 5,
624 NVME_RW_DSM_FREQ_ONCE = 6,
625 NVME_RW_DSM_FREQ_PREFETCH = 7,
626 NVME_RW_DSM_FREQ_TEMP = 8,
627 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
628 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
629 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
630 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
631 NVME_RW_DSM_SEQ_REQ = 1 << 6,
632 NVME_RW_DSM_COMPRESSED = 1 << 7,
633 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
634 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
635 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
636 NVME_RW_PRINFO_PRACT = 1 << 13,
637 NVME_RW_DTYPE_STREAMS = 1 << 4,
638 };
639
640 struct nvme_dsm_cmd {
641 __u8 opcode;
642 __u8 flags;
643 __u16 command_id;
644 __le32 nsid;
645 __u64 rsvd2[2];
646 union nvme_data_ptr dptr;
647 __le32 nr;
648 __le32 attributes;
649 __u32 rsvd12[4];
650 };
651
652 enum {
653 NVME_DSMGMT_IDR = 1 << 0,
654 NVME_DSMGMT_IDW = 1 << 1,
655 NVME_DSMGMT_AD = 1 << 2,
656 };
657
658 #define NVME_DSM_MAX_RANGES 256
659
660 struct nvme_dsm_range {
661 __le32 cattr;
662 __le32 nlb;
663 __le64 slba;
664 };
665
666 struct nvme_write_zeroes_cmd {
667 __u8 opcode;
668 __u8 flags;
669 __u16 command_id;
670 __le32 nsid;
671 __u64 rsvd2;
672 __le64 metadata;
673 union nvme_data_ptr dptr;
674 __le64 slba;
675 __le16 length;
676 __le16 control;
677 __le32 dsmgmt;
678 __le32 reftag;
679 __le16 apptag;
680 __le16 appmask;
681 };
682
683 /* Features */
684
685 struct nvme_feat_auto_pst {
686 __le64 entries[32];
687 };
688
689 enum {
690 NVME_HOST_MEM_ENABLE = (1 << 0),
691 NVME_HOST_MEM_RETURN = (1 << 1),
692 };
693
694 /* Admin commands */
695
696 enum nvme_admin_opcode {
697 nvme_admin_delete_sq = 0x00,
698 nvme_admin_create_sq = 0x01,
699 nvme_admin_get_log_page = 0x02,
700 nvme_admin_delete_cq = 0x04,
701 nvme_admin_create_cq = 0x05,
702 nvme_admin_identify = 0x06,
703 nvme_admin_abort_cmd = 0x08,
704 nvme_admin_set_features = 0x09,
705 nvme_admin_get_features = 0x0a,
706 nvme_admin_async_event = 0x0c,
707 nvme_admin_ns_mgmt = 0x0d,
708 nvme_admin_activate_fw = 0x10,
709 nvme_admin_download_fw = 0x11,
710 nvme_admin_ns_attach = 0x15,
711 nvme_admin_keep_alive = 0x18,
712 nvme_admin_directive_send = 0x19,
713 nvme_admin_directive_recv = 0x1a,
714 nvme_admin_dbbuf = 0x7C,
715 nvme_admin_format_nvm = 0x80,
716 nvme_admin_security_send = 0x81,
717 nvme_admin_security_recv = 0x82,
718 nvme_admin_sanitize_nvm = 0x84,
719 };
720
721 enum {
722 NVME_QUEUE_PHYS_CONTIG = (1 << 0),
723 NVME_CQ_IRQ_ENABLED = (1 << 1),
724 NVME_SQ_PRIO_URGENT = (0 << 1),
725 NVME_SQ_PRIO_HIGH = (1 << 1),
726 NVME_SQ_PRIO_MEDIUM = (2 << 1),
727 NVME_SQ_PRIO_LOW = (3 << 1),
728 NVME_FEAT_ARBITRATION = 0x01,
729 NVME_FEAT_POWER_MGMT = 0x02,
730 NVME_FEAT_LBA_RANGE = 0x03,
731 NVME_FEAT_TEMP_THRESH = 0x04,
732 NVME_FEAT_ERR_RECOVERY = 0x05,
733 NVME_FEAT_VOLATILE_WC = 0x06,
734 NVME_FEAT_NUM_QUEUES = 0x07,
735 NVME_FEAT_IRQ_COALESCE = 0x08,
736 NVME_FEAT_IRQ_CONFIG = 0x09,
737 NVME_FEAT_WRITE_ATOMIC = 0x0a,
738 NVME_FEAT_ASYNC_EVENT = 0x0b,
739 NVME_FEAT_AUTO_PST = 0x0c,
740 NVME_FEAT_HOST_MEM_BUF = 0x0d,
741 NVME_FEAT_TIMESTAMP = 0x0e,
742 NVME_FEAT_KATO = 0x0f,
743 NVME_FEAT_SW_PROGRESS = 0x80,
744 NVME_FEAT_HOST_ID = 0x81,
745 NVME_FEAT_RESV_MASK = 0x82,
746 NVME_FEAT_RESV_PERSIST = 0x83,
747 NVME_LOG_ERROR = 0x01,
748 NVME_LOG_SMART = 0x02,
749 NVME_LOG_FW_SLOT = 0x03,
750 NVME_LOG_CMD_EFFECTS = 0x05,
751 NVME_LOG_DISC = 0x70,
752 NVME_LOG_RESERVATION = 0x80,
753 NVME_FWACT_REPL = (0 << 3),
754 NVME_FWACT_REPL_ACTV = (1 << 3),
755 NVME_FWACT_ACTV = (2 << 3),
756 };
757
758 struct nvme_identify {
759 __u8 opcode;
760 __u8 flags;
761 __u16 command_id;
762 __le32 nsid;
763 __u64 rsvd2[2];
764 union nvme_data_ptr dptr;
765 __u8 cns;
766 __u8 rsvd3;
767 __le16 ctrlid;
768 __u32 rsvd11[5];
769 };
770
771 #define NVME_IDENTIFY_DATA_SIZE 4096
772
773 struct nvme_features {
774 __u8 opcode;
775 __u8 flags;
776 __u16 command_id;
777 __le32 nsid;
778 __u64 rsvd2[2];
779 union nvme_data_ptr dptr;
780 __le32 fid;
781 __le32 dword11;
782 __le32 dword12;
783 __le32 dword13;
784 __le32 dword14;
785 __le32 dword15;
786 };
787
788 struct nvme_host_mem_buf_desc {
789 __le64 addr;
790 __le32 size;
791 __u32 rsvd;
792 };
793
794 struct nvme_create_cq {
795 __u8 opcode;
796 __u8 flags;
797 __u16 command_id;
798 __u32 rsvd1[5];
799 __le64 prp1;
800 __u64 rsvd8;
801 __le16 cqid;
802 __le16 qsize;
803 __le16 cq_flags;
804 __le16 irq_vector;
805 __u32 rsvd12[4];
806 };
807
808 struct nvme_create_sq {
809 __u8 opcode;
810 __u8 flags;
811 __u16 command_id;
812 __u32 rsvd1[5];
813 __le64 prp1;
814 __u64 rsvd8;
815 __le16 sqid;
816 __le16 qsize;
817 __le16 sq_flags;
818 __le16 cqid;
819 __u32 rsvd12[4];
820 };
821
822 struct nvme_delete_queue {
823 __u8 opcode;
824 __u8 flags;
825 __u16 command_id;
826 __u32 rsvd1[9];
827 __le16 qid;
828 __u16 rsvd10;
829 __u32 rsvd11[5];
830 };
831
832 struct nvme_abort_cmd {
833 __u8 opcode;
834 __u8 flags;
835 __u16 command_id;
836 __u32 rsvd1[9];
837 __le16 sqid;
838 __u16 cid;
839 __u32 rsvd11[5];
840 };
841
842 struct nvme_download_firmware {
843 __u8 opcode;
844 __u8 flags;
845 __u16 command_id;
846 __u32 rsvd1[5];
847 union nvme_data_ptr dptr;
848 __le32 numd;
849 __le32 offset;
850 __u32 rsvd12[4];
851 };
852
853 struct nvme_format_cmd {
854 __u8 opcode;
855 __u8 flags;
856 __u16 command_id;
857 __le32 nsid;
858 __u64 rsvd2[4];
859 __le32 cdw10;
860 __u32 rsvd11[5];
861 };
862
863 struct nvme_get_log_page_command {
864 __u8 opcode;
865 __u8 flags;
866 __u16 command_id;
867 __le32 nsid;
868 __u64 rsvd2[2];
869 union nvme_data_ptr dptr;
870 __u8 lid;
871 __u8 rsvd10;
872 __le16 numdl;
873 __le16 numdu;
874 __u16 rsvd11;
875 __le32 lpol;
876 __le32 lpou;
877 __u32 rsvd14[2];
878 };
879
880 struct nvme_directive_cmd {
881 __u8 opcode;
882 __u8 flags;
883 __u16 command_id;
884 __le32 nsid;
885 __u64 rsvd2[2];
886 union nvme_data_ptr dptr;
887 __le32 numd;
888 __u8 doper;
889 __u8 dtype;
890 __le16 dspec;
891 __u8 endir;
892 __u8 tdtype;
893 __u16 rsvd15;
894
895 __u32 rsvd16[3];
896 };
897
898 /*
899 * Fabrics subcommands.
900 */
901 enum nvmf_fabrics_opcode {
902 nvme_fabrics_command = 0x7f,
903 };
904
905 enum nvmf_capsule_command {
906 nvme_fabrics_type_property_set = 0x00,
907 nvme_fabrics_type_connect = 0x01,
908 nvme_fabrics_type_property_get = 0x04,
909 };
910
911 struct nvmf_common_command {
912 __u8 opcode;
913 __u8 resv1;
914 __u16 command_id;
915 __u8 fctype;
916 __u8 resv2[35];
917 __u8 ts[24];
918 };
919
920 /*
921 * The legal cntlid range a NVMe Target will provide.
922 * Note that cntlid of value 0 is considered illegal in the fabrics world.
923 * Devices based on earlier specs did not have the subsystem concept;
924 * therefore, those devices had their cntlid value set to 0 as a result.
925 */
926 #define NVME_CNTLID_MIN 1
927 #define NVME_CNTLID_MAX 0xffef
928 #define NVME_CNTLID_DYNAMIC 0xffff
929
930 #define MAX_DISC_LOGS 255
931
932 /* Discovery log page entry */
933 struct nvmf_disc_rsp_page_entry {
934 __u8 trtype;
935 __u8 adrfam;
936 __u8 subtype;
937 __u8 treq;
938 __le16 portid;
939 __le16 cntlid;
940 __le16 asqsz;
941 __u8 resv8[22];
942 char trsvcid[NVMF_TRSVCID_SIZE];
943 __u8 resv64[192];
944 char subnqn[NVMF_NQN_FIELD_LEN];
945 char traddr[NVMF_TRADDR_SIZE];
946 union tsas {
947 char common[NVMF_TSAS_SIZE];
948 struct rdma {
949 __u8 qptype;
950 __u8 prtype;
951 __u8 cms;
952 __u8 resv3[5];
953 __u16 pkey;
954 __u8 resv10[246];
955 } rdma;
956 } tsas;
957 };
958
959 /* Discovery log page header */
960 struct nvmf_disc_rsp_page_hdr {
961 __le64 genctr;
962 __le64 numrec;
963 __le16 recfmt;
964 __u8 resv14[1006];
965 struct nvmf_disc_rsp_page_entry entries[0];
966 };
967
968 struct nvmf_connect_command {
969 __u8 opcode;
970 __u8 resv1;
971 __u16 command_id;
972 __u8 fctype;
973 __u8 resv2[19];
974 union nvme_data_ptr dptr;
975 __le16 recfmt;
976 __le16 qid;
977 __le16 sqsize;
978 __u8 cattr;
979 __u8 resv3;
980 __le32 kato;
981 __u8 resv4[12];
982 };
983
984 struct nvmf_connect_data {
985 uuid_t hostid;
986 __le16 cntlid;
987 char resv4[238];
988 char subsysnqn[NVMF_NQN_FIELD_LEN];
989 char hostnqn[NVMF_NQN_FIELD_LEN];
990 char resv5[256];
991 };
992
993 struct nvmf_property_set_command {
994 __u8 opcode;
995 __u8 resv1;
996 __u16 command_id;
997 __u8 fctype;
998 __u8 resv2[35];
999 __u8 attrib;
1000 __u8 resv3[3];
1001 __le32 offset;
1002 __le64 value;
1003 __u8 resv4[8];
1004 };
1005
1006 struct nvmf_property_get_command {
1007 __u8 opcode;
1008 __u8 resv1;
1009 __u16 command_id;
1010 __u8 fctype;
1011 __u8 resv2[35];
1012 __u8 attrib;
1013 __u8 resv3[3];
1014 __le32 offset;
1015 __u8 resv4[16];
1016 };
1017
1018 struct nvme_dbbuf {
1019 __u8 opcode;
1020 __u8 flags;
1021 __u16 command_id;
1022 __u32 rsvd1[5];
1023 __le64 prp1;
1024 __le64 prp2;
1025 __u32 rsvd12[6];
1026 };
1027
1028 struct streams_directive_params {
1029 __le16 msl;
1030 __le16 nssa;
1031 __le16 nsso;
1032 __u8 rsvd[10];
1033 __le32 sws;
1034 __le16 sgs;
1035 __le16 nsa;
1036 __le16 nso;
1037 __u8 rsvd2[6];
1038 };
1039
1040 struct nvme_command {
1041 union {
1042 struct nvme_common_command common;
1043 struct nvme_rw_command rw;
1044 struct nvme_identify identify;
1045 struct nvme_features features;
1046 struct nvme_create_cq create_cq;
1047 struct nvme_create_sq create_sq;
1048 struct nvme_delete_queue delete_queue;
1049 struct nvme_download_firmware dlfw;
1050 struct nvme_format_cmd format;
1051 struct nvme_dsm_cmd dsm;
1052 struct nvme_write_zeroes_cmd write_zeroes;
1053 struct nvme_abort_cmd abort;
1054 struct nvme_get_log_page_command get_log_page;
1055 struct nvmf_common_command fabrics;
1056 struct nvmf_connect_command connect;
1057 struct nvmf_property_set_command prop_set;
1058 struct nvmf_property_get_command prop_get;
1059 struct nvme_dbbuf dbbuf;
1060 struct nvme_directive_cmd directive;
1061 };
1062 };
1063
1064 static inline bool nvme_is_write(struct nvme_command *cmd)
1065 {
1066 /*
1067 * What a mess...
1068 *
1069 * Why can't we simply have a Fabrics In and Fabrics out command?
1070 */
1071 if (unlikely(cmd->common.opcode == nvme_fabrics_command))
1072 return cmd->fabrics.fctype & 1;
1073 return cmd->common.opcode & 1;
1074 }
1075
1076 enum {
1077 /*
1078 * Generic Command Status:
1079 */
1080 NVME_SC_SUCCESS = 0x0,
1081 NVME_SC_INVALID_OPCODE = 0x1,
1082 NVME_SC_INVALID_FIELD = 0x2,
1083 NVME_SC_CMDID_CONFLICT = 0x3,
1084 NVME_SC_DATA_XFER_ERROR = 0x4,
1085 NVME_SC_POWER_LOSS = 0x5,
1086 NVME_SC_INTERNAL = 0x6,
1087 NVME_SC_ABORT_REQ = 0x7,
1088 NVME_SC_ABORT_QUEUE = 0x8,
1089 NVME_SC_FUSED_FAIL = 0x9,
1090 NVME_SC_FUSED_MISSING = 0xa,
1091 NVME_SC_INVALID_NS = 0xb,
1092 NVME_SC_CMD_SEQ_ERROR = 0xc,
1093 NVME_SC_SGL_INVALID_LAST = 0xd,
1094 NVME_SC_SGL_INVALID_COUNT = 0xe,
1095 NVME_SC_SGL_INVALID_DATA = 0xf,
1096 NVME_SC_SGL_INVALID_METADATA = 0x10,
1097 NVME_SC_SGL_INVALID_TYPE = 0x11,
1098
1099 NVME_SC_SGL_INVALID_OFFSET = 0x16,
1100 NVME_SC_SGL_INVALID_SUBTYPE = 0x17,
1101
1102 NVME_SC_LBA_RANGE = 0x80,
1103 NVME_SC_CAP_EXCEEDED = 0x81,
1104 NVME_SC_NS_NOT_READY = 0x82,
1105 NVME_SC_RESERVATION_CONFLICT = 0x83,
1106
1107 /*
1108 * Command Specific Status:
1109 */
1110 NVME_SC_CQ_INVALID = 0x100,
1111 NVME_SC_QID_INVALID = 0x101,
1112 NVME_SC_QUEUE_SIZE = 0x102,
1113 NVME_SC_ABORT_LIMIT = 0x103,
1114 NVME_SC_ABORT_MISSING = 0x104,
1115 NVME_SC_ASYNC_LIMIT = 0x105,
1116 NVME_SC_FIRMWARE_SLOT = 0x106,
1117 NVME_SC_FIRMWARE_IMAGE = 0x107,
1118 NVME_SC_INVALID_VECTOR = 0x108,
1119 NVME_SC_INVALID_LOG_PAGE = 0x109,
1120 NVME_SC_INVALID_FORMAT = 0x10a,
1121 NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1122 NVME_SC_INVALID_QUEUE = 0x10c,
1123 NVME_SC_FEATURE_NOT_SAVEABLE = 0x10d,
1124 NVME_SC_FEATURE_NOT_CHANGEABLE = 0x10e,
1125 NVME_SC_FEATURE_NOT_PER_NS = 0x10f,
1126 NVME_SC_FW_NEEDS_SUBSYS_RESET = 0x110,
1127 NVME_SC_FW_NEEDS_RESET = 0x111,
1128 NVME_SC_FW_NEEDS_MAX_TIME = 0x112,
1129 NVME_SC_FW_ACIVATE_PROHIBITED = 0x113,
1130 NVME_SC_OVERLAPPING_RANGE = 0x114,
1131 NVME_SC_NS_INSUFFICENT_CAP = 0x115,
1132 NVME_SC_NS_ID_UNAVAILABLE = 0x116,
1133 NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1134 NVME_SC_NS_IS_PRIVATE = 0x119,
1135 NVME_SC_NS_NOT_ATTACHED = 0x11a,
1136 NVME_SC_THIN_PROV_NOT_SUPP = 0x11b,
1137 NVME_SC_CTRL_LIST_INVALID = 0x11c,
1138
1139 /*
1140 * I/O Command Set Specific - NVM commands:
1141 */
1142 NVME_SC_BAD_ATTRIBUTES = 0x180,
1143 NVME_SC_INVALID_PI = 0x181,
1144 NVME_SC_READ_ONLY = 0x182,
1145 NVME_SC_ONCS_NOT_SUPPORTED = 0x183,
1146
1147 /*
1148 * I/O Command Set Specific - Fabrics commands:
1149 */
1150 NVME_SC_CONNECT_FORMAT = 0x180,
1151 NVME_SC_CONNECT_CTRL_BUSY = 0x181,
1152 NVME_SC_CONNECT_INVALID_PARAM = 0x182,
1153 NVME_SC_CONNECT_RESTART_DISC = 0x183,
1154 NVME_SC_CONNECT_INVALID_HOST = 0x184,
1155
1156 NVME_SC_DISCOVERY_RESTART = 0x190,
1157 NVME_SC_AUTH_REQUIRED = 0x191,
1158
1159 /*
1160 * Media and Data Integrity Errors:
1161 */
1162 NVME_SC_WRITE_FAULT = 0x280,
1163 NVME_SC_READ_ERROR = 0x281,
1164 NVME_SC_GUARD_CHECK = 0x282,
1165 NVME_SC_APPTAG_CHECK = 0x283,
1166 NVME_SC_REFTAG_CHECK = 0x284,
1167 NVME_SC_COMPARE_FAILED = 0x285,
1168 NVME_SC_ACCESS_DENIED = 0x286,
1169 NVME_SC_UNWRITTEN_BLOCK = 0x287,
1170
1171 NVME_SC_DNR = 0x4000,
1172 };
1173
1174 struct nvme_completion {
1175 /*
1176 * Used by Admin and Fabrics commands to return data:
1177 */
1178 union nvme_result {
1179 __le16 u16;
1180 __le32 u32;
1181 __le64 u64;
1182 } result;
1183 __le16 sq_head; /* how much of this queue may be reclaimed */
1184 __le16 sq_id; /* submission queue that generated this entry */
1185 __u16 command_id; /* of the command which completed */
1186 __le16 status; /* did the command fail, and if so, why? */
1187 };
1188
1189 #define NVME_VS(major, minor, tertiary) \
1190 (((major) << 16) | ((minor) << 8) | (tertiary))
1191
1192 #define NVME_MAJOR(ver) ((ver) >> 16)
1193 #define NVME_MINOR(ver) (((ver) >> 8) & 0xff)
1194 #define NVME_TERTIARY(ver) ((ver) & 0xff)
1195
1196 #endif /* _LINUX_NVME_H */
CRIS linux kernel tree