include/linux/qed/fcoe_common.h

   1 /* QLogic qed NIC Driver
   2  * Copyright (c) 2015 QLogic Corporation
   3  *
   4  * This software is available under the terms of the GNU General Public License
   5  * (GPL) Version 2, available from the file COPYING in the main directory of
   6  * this source tree.
   7  */
   8
   9 #ifndef __FCOE_COMMON__
  10 #define __FCOE_COMMON__
  11
  12 /*********************/
  13 /* FCOE FW CONSTANTS */
  14 /*********************/
  15
  16 #define FC_ABTS_REPLY_MAX_PAYLOAD_LEN   12
  17
  18 /* The fcoe storm task context protection-information of Ystorm */
  19 struct protection_info_ctx {
  20         __le16 flags;
  21 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK         0x3
  22 #define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT        0
  23 #define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK            0x1
  24 #define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT           2
  25 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK   0x1
  26 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT  3
  27 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK      0xF
  28 #define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT     4
  29 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK   0x1
  30 #define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT  8
  31 #define PROTECTION_INFO_CTX_RESERVED0_MASK              0x7F
  32 #define PROTECTION_INFO_CTX_RESERVED0_SHIFT             9
  33         u8 dix_block_size;
  34         u8 dst_size;
  35 };
  36
  37 /* The fcoe storm task context protection-information of Ystorm */
  38 union protection_info_union_ctx {
  39         struct protection_info_ctx info;
  40         __le32 value;
  41 };
  42
  43 /* FCP CMD payload */
  44 struct fcoe_fcp_cmd_payload {
  45         __le32 opaque[8];
  46 };
  47
  48 /* FCP RSP payload */
  49 struct fcoe_fcp_rsp_payload {
  50         __le32 opaque[6];
  51 };
  52
  53 /* FCP RSP payload */
  54 struct fcp_rsp_payload_padded {
  55         struct fcoe_fcp_rsp_payload rsp_payload;
  56         __le32 reserved[2];
  57 };
  58
  59 /* FCP RSP payload */
  60 struct fcoe_fcp_xfer_payload {
  61         __le32 opaque[3];
  62 };
  63
  64 /* FCP RSP payload */
  65 struct fcp_xfer_payload_padded {
  66         struct fcoe_fcp_xfer_payload xfer_payload;
  67         __le32 reserved[5];
  68 };
  69
  70 /* Task params */
  71 struct fcoe_tx_data_params {
  72         __le32 data_offset;
  73         __le32 offset_in_io;
  74         u8 flags;
  75 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK     0x1
  76 #define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT    0
  77 #define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK              0x1
  78 #define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT             1
  79 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK          0x1
  80 #define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT         2
  81 #define FCOE_TX_DATA_PARAMS_RESERVED0_MASK              0x1F
  82 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT             3
  83         u8 dif_residual;
  84         __le16 seq_cnt;
  85         __le16 single_sge_saved_offset;
  86         __le16 next_dif_offset;
  87         __le16 seq_id;
  88         __le16 reserved3;
  89 };
  90
  91 /* Middle path parameters: FC header fields provided by the driver */
  92 struct fcoe_tx_mid_path_params {
  93         __le32 parameter;
  94         u8 r_ctl;
  95         u8 type;
  96         u8 cs_ctl;
  97         u8 df_ctl;
  98         __le16 rx_id;
  99         __le16 ox_id;
 100 };
 101
 102 /* Task params */
 103 struct fcoe_tx_params {
 104         struct fcoe_tx_data_params data;
 105         struct fcoe_tx_mid_path_params mid_path;
 106 };
 107
 108 /* Union of FCP CMD payload \ TX params \ ABTS \ Cleanup */
 109 union fcoe_tx_info_union_ctx {
 110         struct fcoe_fcp_cmd_payload fcp_cmd_payload;
 111         struct fcp_rsp_payload_padded fcp_rsp_payload;
 112         struct fcp_xfer_payload_padded fcp_xfer_payload;
 113         struct fcoe_tx_params tx_params;
 114 };
 115
 116 /* Data sgl */
 117 struct fcoe_slow_sgl_ctx {
 118         struct regpair base_sgl_addr;
 119         __le16 curr_sge_off;
 120         __le16 remainder_num_sges;
 121         __le16 curr_sgl_index;
 122         __le16 reserved;
 123 };
 124
 125 /* Union of DIX SGL \ cached DIX sges */
 126 union fcoe_dix_desc_ctx {
 127         struct fcoe_slow_sgl_ctx dix_sgl;
 128         struct scsi_sge cached_dix_sge;
 129 };
 130
 131 /* The fcoe storm task context of Ystorm */
 132 struct ystorm_fcoe_task_st_ctx {
 133         u8 task_type;
 134         u8 sgl_mode;
 135 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK        0x1
 136 #define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT       0
 137 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK               0x7F
 138 #define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT              1
 139         u8 cached_dix_sge;
 140         u8 expect_first_xfer;
 141         __le32 num_pbf_zero_write;
 142         union protection_info_union_ctx protection_info_union;
 143         __le32 data_2_trns_rem;
 144         struct scsi_sgl_params sgl_params;
 145         u8 reserved1[12];
 146         union fcoe_tx_info_union_ctx tx_info_union;
 147         union fcoe_dix_desc_ctx dix_desc;
 148         struct scsi_cached_sges data_desc;
 149         __le16 ox_id;
 150         __le16 rx_id;
 151         __le32 task_rety_identifier;
 152         u8 reserved2[8];
 153 };
 154
 155 struct e4_ystorm_fcoe_task_ag_ctx {
 156         u8 byte0;
 157         u8 byte1;
 158         __le16 word0;
 159         u8 flags0;
 160 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK         0xF
 161 #define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT        0
 162 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK            0x1
 163 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT           4
 164 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK            0x1
 165 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT           5
 166 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK            0x1
 167 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT           6
 168 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK            0x1
 169 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT           7
 170         u8 flags1;
 171 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK             0x3
 172 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT            0
 173 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK             0x3
 174 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT            2
 175 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK      0x3
 176 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT     4
 177 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK           0x1
 178 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT          6
 179 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK           0x1
 180 #define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT          7
 181         u8 flags2;
 182 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK            0x1
 183 #define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT           0
 184 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK         0x1
 185 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT        1
 186 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK         0x1
 187 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT        2
 188 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK         0x1
 189 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT        3
 190 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK         0x1
 191 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT        4
 192 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK         0x1
 193 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT        5
 194 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK         0x1
 195 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT        6
 196 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK         0x1
 197 #define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT        7
 198         u8 byte2;
 199         __le32 reg0;
 200         u8 byte3;
 201         u8 byte4;
 202         __le16 rx_id;
 203         __le16 word2;
 204         __le16 word3;
 205         __le16 word4;
 206         __le16 word5;
 207         __le32 reg1;
 208         __le32 reg2;
 209 };
 210
 211 struct e4_tstorm_fcoe_task_ag_ctx {
 212         u8 reserved;
 213         u8 byte1;
 214         __le16 icid;
 215         u8 flags0;
 216 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
 217 #define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
 218 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
 219 #define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
 220 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK                    0x1
 221 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT                   5
 222 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK         0x1
 223 #define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT        6
 224 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK                   0x1
 225 #define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT                  7
 226         u8 flags1;
 227 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK    0x1
 228 #define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT   0
 229 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK            0x1
 230 #define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT           1
 231 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK   0x3
 232 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT  2
 233 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK       0x3
 234 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT      4
 235 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK             0x3
 236 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT            6
 237         u8 flags2;
 238 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK          0x3
 239 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT         0
 240 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK           0x3
 241 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT          2
 242 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK             0x3
 243 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT            4
 244 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK         0x3
 245 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT        6
 246         u8 flags3;
 247 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK           0x3
 248 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT          0
 249 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK        0x1
 250 #define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT       2
 251 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK            0x1
 252 #define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT           3
 253 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK                   0x1
 254 #define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT                  4
 255 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK       0x1
 256 #define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT      5
 257 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK        0x1
 258 #define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT       6
 259 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK          0x1
 260 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT         7
 261         u8 flags4;
 262 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK      0x1
 263 #define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT     0
 264 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK        0x1
 265 #define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT       1
 266 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK                 0x1
 267 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT                2
 268 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK                 0x1
 269 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT                3
 270 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK                 0x1
 271 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT                4
 272 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK                 0x1
 273 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT                5
 274 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK                 0x1
 275 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT                6
 276 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK                 0x1
 277 #define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT                7
 278         u8 cleanup_state;
 279         __le16 last_sent_tid;
 280         __le32 rec_rr_tov_exp_timeout;
 281         u8 byte3;
 282         u8 byte4;
 283         __le16 word2;
 284         __le16 word3;
 285         __le16 word4;
 286         __le32 data_offset_end_of_seq;
 287         __le32 data_offset_next;
 288 };
 289
 290 /* Cached data sges */
 291 struct fcoe_exp_ro {
 292         __le32 data_offset;
 293         __le32 reserved;
 294 };
 295
 296 /* Union of Cleanup address \ expected relative offsets */
 297 union fcoe_cleanup_addr_exp_ro_union {
 298         struct regpair abts_rsp_fc_payload_hi;
 299         struct fcoe_exp_ro exp_ro;
 300 };
 301
 302 /* Fields coppied from ABTSrsp pckt */
 303 struct fcoe_abts_pkt {
 304         __le32 abts_rsp_fc_payload_lo;
 305         __le16 abts_rsp_rx_id;
 306         u8 abts_rsp_rctl;
 307         u8 reserved2;
 308 };
 309
 310 /* FW read- write (modifyable) part The fcoe task storm context of Tstorm */
 311 struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
 312         union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
 313         __le16 flags;
 314 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK        0x1
 315 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT       0
 316 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK    0x1
 317 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT   1
 318 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK         0x1
 319 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT        2
 320 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK        0x1
 321 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT       3
 322 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK   0x1
 323 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT  4
 324 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK    0x1
 325 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT   5
 326 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK         0x3
 327 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT        6
 328 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK              0xFF
 329 #define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT             8
 330         __le16 seq_cnt;
 331         u8 seq_id;
 332         u8 ooo_rx_seq_id;
 333         __le16 rx_id;
 334         struct fcoe_abts_pkt abts_data;
 335         __le32 e_d_tov_exp_timeout_val;
 336         __le16 ooo_rx_seq_cnt;
 337         __le16 reserved1;
 338 };
 339
 340 /* FW read only part The fcoe task storm context of Tstorm */
 341 struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
 342         u8 task_type;
 343         u8 dev_type;
 344         u8 conf_supported;
 345         u8 glbl_q_num;
 346         __le32 cid;
 347         __le32 fcp_cmd_trns_size;
 348         __le32 rsrv;
 349 };
 350
 351 /** The fcoe task storm context of Tstorm */
 352 struct tstorm_fcoe_task_st_ctx {
 353         struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
 354         struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
 355 };
 356
 357 struct e4_mstorm_fcoe_task_ag_ctx {
 358         u8 byte0;
 359         u8 byte1;
 360         __le16 icid;
 361         u8 flags0;
 362 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
 363 #define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
 364 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
 365 #define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
 366 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK              0x1
 367 #define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT             5
 368 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK                    0x1
 369 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT                   6
 370 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK                    0x1
 371 #define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT                   7
 372         u8 flags1;
 373 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK           0x3
 374 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT          0
 375 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK                     0x3
 376 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT                    2
 377 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK                     0x3
 378 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT                    4
 379 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK        0x1
 380 #define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT       6
 381 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK                   0x1
 382 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT                  7
 383         u8 flags2;
 384 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK                   0x1
 385 #define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT                  0
 386 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK                 0x1
 387 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT                1
 388 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK                 0x1
 389 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT                2
 390 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK                 0x1
 391 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT                3
 392 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK                 0x1
 393 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT                4
 394 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK                 0x1
 395 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT                5
 396 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK       0x1
 397 #define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT      6
 398 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK                 0x1
 399 #define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT                7
 400         u8 cleanup_state;
 401         __le32 received_bytes;
 402         u8 byte3;
 403         u8 glbl_q_num;
 404         __le16 word1;
 405         __le16 tid_to_xfer;
 406         __le16 word3;
 407         __le16 word4;
 408         __le16 word5;
 409         __le32 expected_bytes;
 410         __le32 reg2;
 411 };
 412
 413 /* The fcoe task storm context of Mstorm */
 414 struct mstorm_fcoe_task_st_ctx {
 415         struct regpair rsp_buf_addr;
 416         __le32 rsrv[2];
 417         struct scsi_sgl_params sgl_params;
 418         __le32 data_2_trns_rem;
 419         __le32 data_buffer_offset;
 420         __le16 parent_id;
 421         __le16 flags;
 422 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK          0xF
 423 #define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT         0
 424 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK             0x3
 425 #define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT            4
 426 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK                0x1
 427 #define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT               6
 428 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK       0x1
 429 #define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT      7
 430 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK             0x3
 431 #define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT            8
 432 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK       0x1
 433 #define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT      10
 434 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK         0x1
 435 #define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT        11
 436 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK              0x1
 437 #define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT             12
 438 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK                0x1
 439 #define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT               13
 440 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK                   0x3
 441 #define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT                  14
 442         struct scsi_cached_sges data_desc;
 443 };
 444
 445 struct e4_ustorm_fcoe_task_ag_ctx {
 446         u8 reserved;
 447         u8 byte1;
 448         __le16 icid;
 449         u8 flags0;
 450 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK         0xF
 451 #define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT        0
 452 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK            0x1
 453 #define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT           4
 454 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK                    0x1
 455 #define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT                   5
 456 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK                     0x3
 457 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT                    6
 458         u8 flags1;
 459 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK             0x3
 460 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT            0
 461 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK             0x3
 462 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT            2
 463 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK             0x3
 464 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT            4
 465 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK    0x3
 466 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT   6
 467         u8 flags2;
 468 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK                   0x1
 469 #define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT                  0
 470 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK                   0x1
 471 #define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT                  1
 472 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK                   0x1
 473 #define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT                  2
 474 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK                   0x1
 475 #define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT                  3
 476 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK         0x1
 477 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT        4
 478 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK                 0x1
 479 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT                5
 480 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK                 0x1
 481 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT                6
 482 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK                 0x1
 483 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT                7
 484         u8 flags3;
 485 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK         0x1
 486 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT        0
 487 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK         0x1
 488 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT        1
 489 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK         0x1
 490 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT        2
 491 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK         0x1
 492 #define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT        3
 493 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK  0xF
 494 #define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
 495         __le32 dif_err_intervals;
 496         __le32 dif_error_1st_interval;
 497         __le32 global_cq_num;
 498         __le32 reg3;
 499         __le32 reg4;
 500         __le32 reg5;
 501 };
 502
 503 /* FCoE task context */
 504 struct e4_fcoe_task_context {
 505         struct ystorm_fcoe_task_st_ctx ystorm_st_context;
 506         struct regpair ystorm_st_padding[2];
 507         struct tdif_task_context tdif_context;
 508         struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context;
 509         struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context;
 510         struct timers_context timer_context;
 511         struct tstorm_fcoe_task_st_ctx tstorm_st_context;
 512         struct regpair tstorm_st_padding[2];
 513         struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context;
 514         struct mstorm_fcoe_task_st_ctx mstorm_st_context;
 515         struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context;
 516         struct rdif_task_context rdif_context;
 517 };
 518
 519 /* FCoE additional WQE (Sq/XferQ) information */
 520 union fcoe_additional_info_union {
 521         __le32 previous_tid;
 522         __le32 parent_tid;
 523         __le32 burst_length;
 524         __le32 seq_rec_updated_offset;
 525 };
 526
 527 /* FCoE Ramrod Command IDs */
 528 enum fcoe_completion_status {
 529         FCOE_COMPLETION_STATUS_SUCCESS,
 530         FCOE_COMPLETION_STATUS_FCOE_VER_ERR,
 531         FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR,
 532         MAX_FCOE_COMPLETION_STATUS
 533 };
 534
 535 /* FC address (SID/DID) network presentation */
 536 struct fc_addr_nw {
 537         u8 addr_lo;
 538         u8 addr_mid;
 539         u8 addr_hi;
 540 };
 541
 542 /* FCoE connection offload */
 543 struct fcoe_conn_offload_ramrod_data {
 544         struct regpair sq_pbl_addr;
 545         struct regpair sq_curr_page_addr;
 546         struct regpair sq_next_page_addr;
 547         struct regpair xferq_pbl_addr;
 548         struct regpair xferq_curr_page_addr;
 549         struct regpair xferq_next_page_addr;
 550         struct regpair respq_pbl_addr;
 551         struct regpair respq_curr_page_addr;
 552         struct regpair respq_next_page_addr;
 553         __le16 dst_mac_addr_lo;
 554         __le16 dst_mac_addr_mid;
 555         __le16 dst_mac_addr_hi;
 556         __le16 src_mac_addr_lo;
 557         __le16 src_mac_addr_mid;
 558         __le16 src_mac_addr_hi;
 559         __le16 tx_max_fc_pay_len;
 560         __le16 e_d_tov_timer_val;
 561         __le16 rx_max_fc_pay_len;
 562         __le16 vlan_tag;
 563 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK      0xFFF
 564 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT     0
 565 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK          0x1
 566 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT         12
 567 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK     0x7
 568 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT    13
 569         __le16 physical_q0;
 570         __le16 rec_rr_tov_timer_val;
 571         struct fc_addr_nw s_id;
 572         u8 max_conc_seqs_c3;
 573         struct fc_addr_nw d_id;
 574         u8 flags;
 575 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK  0x1
 576 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
 577 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK           0x1
 578 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT          1
 579 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK          0x1
 580 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT         2
 581 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK          0x1
 582 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT         3
 583 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_MASK        0x1
 584 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_SHIFT       4
 585 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK                 0x3
 586 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT                5
 587 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK            0x1
 588 #define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT           7
 589         __le16 conn_id;
 590         u8 def_q_idx;
 591         u8 reserved[5];
 592 };
 593
 594 /* FCoE terminate connection request */
 595 struct fcoe_conn_terminate_ramrod_data {
 596         struct regpair terminate_params_addr;
 597 };
 598
 599 /* FCoE device type */
 600 enum fcoe_device_type {
 601         FCOE_TASK_DEV_TYPE_DISK,
 602         FCOE_TASK_DEV_TYPE_TAPE,
 603         MAX_FCOE_DEVICE_TYPE
 604 };
 605
 606 /* Data sgl */
 607 struct fcoe_fast_sgl_ctx {
 608         struct regpair sgl_start_addr;
 609         __le32 sgl_byte_offset;
 610         __le16 task_reuse_cnt;
 611         __le16 init_offset_in_first_sge;
 612 };
 613
 614 /* FCoE firmware function init */
 615 struct fcoe_init_func_ramrod_data {
 616         struct scsi_init_func_params func_params;
 617         struct scsi_init_func_queues q_params;
 618         __le16 mtu;
 619         __le16 sq_num_pages_in_pbl;
 620         __le32 reserved[3];
 621 };
 622
 623 /* FCoE: Mode of the connection: Target or Initiator or both */
 624 enum fcoe_mode_type {
 625         FCOE_INITIATOR_MODE = 0x0,
 626         FCOE_TARGET_MODE = 0x1,
 627         FCOE_BOTH_OR_NOT_CHOSEN = 0x3,
 628         MAX_FCOE_MODE_TYPE
 629 };
 630
 631 /* Per PF FCoE receive path statistics - tStorm RAM structure */
 632 struct fcoe_rx_stat {
 633         struct regpair fcoe_rx_byte_cnt;
 634         struct regpair fcoe_rx_data_pkt_cnt;
 635         struct regpair fcoe_rx_xfer_pkt_cnt;
 636         struct regpair fcoe_rx_other_pkt_cnt;
 637         __le32 fcoe_silent_drop_pkt_cmdq_full_cnt;
 638         __le32 fcoe_silent_drop_pkt_rq_full_cnt;
 639         __le32 fcoe_silent_drop_pkt_crc_error_cnt;
 640         __le32 fcoe_silent_drop_pkt_task_invalid_cnt;
 641         __le32 fcoe_silent_drop_total_pkt_cnt;
 642         __le32 rsrv;
 643 };
 644
 645 /* FCoE SQE request type */
 646 enum fcoe_sqe_request_type {
 647         SEND_FCOE_CMD,
 648         SEND_FCOE_MIDPATH,
 649         SEND_FCOE_ABTS_REQUEST,
 650         FCOE_EXCHANGE_CLEANUP,
 651         FCOE_SEQUENCE_RECOVERY,
 652         SEND_FCOE_XFER_RDY,
 653         SEND_FCOE_RSP,
 654         SEND_FCOE_RSP_WITH_SENSE_DATA,
 655         SEND_FCOE_TARGET_DATA,
 656         SEND_FCOE_INITIATOR_DATA,
 657         SEND_FCOE_XFER_CONTINUATION_RDY,
 658         SEND_FCOE_TARGET_ABTS_RSP,
 659         MAX_FCOE_SQE_REQUEST_TYPE
 660 };
 661
 662 /* FCoe statistics request */
 663 struct fcoe_stat_ramrod_data {
 664         struct regpair stat_params_addr;
 665 };
 666
 667 /* FCoE task type */
 668 enum fcoe_task_type {
 669         FCOE_TASK_TYPE_WRITE_INITIATOR,
 670         FCOE_TASK_TYPE_READ_INITIATOR,
 671         FCOE_TASK_TYPE_MIDPATH,
 672         FCOE_TASK_TYPE_UNSOLICITED,
 673         FCOE_TASK_TYPE_ABTS,
 674         FCOE_TASK_TYPE_EXCHANGE_CLEANUP,
 675         FCOE_TASK_TYPE_SEQUENCE_CLEANUP,
 676         FCOE_TASK_TYPE_WRITE_TARGET,
 677         FCOE_TASK_TYPE_READ_TARGET,
 678         FCOE_TASK_TYPE_RSP,
 679         FCOE_TASK_TYPE_RSP_SENSE_DATA,
 680         FCOE_TASK_TYPE_ABTS_TARGET,
 681         FCOE_TASK_TYPE_ENUM_SIZE,
 682         MAX_FCOE_TASK_TYPE
 683 };
 684
 685 /* Per PF FCoE transmit path statistics - pStorm RAM structure */
 686 struct fcoe_tx_stat {
 687         struct regpair fcoe_tx_byte_cnt;
 688         struct regpair fcoe_tx_data_pkt_cnt;
 689         struct regpair fcoe_tx_xfer_pkt_cnt;
 690         struct regpair fcoe_tx_other_pkt_cnt;
 691 };
 692
 693 /* FCoE SQ/XferQ element */
 694 struct fcoe_wqe {
 695         __le16 task_id;
 696         __le16 flags;
 697 #define FCOE_WQE_REQ_TYPE_MASK          0xF
 698 #define FCOE_WQE_REQ_TYPE_SHIFT         0
 699 #define FCOE_WQE_SGL_MODE_MASK          0x1
 700 #define FCOE_WQE_SGL_MODE_SHIFT         4
 701 #define FCOE_WQE_CONTINUATION_MASK      0x1
 702 #define FCOE_WQE_CONTINUATION_SHIFT     5
 703 #define FCOE_WQE_SEND_AUTO_RSP_MASK     0x1
 704 #define FCOE_WQE_SEND_AUTO_RSP_SHIFT    6
 705 #define FCOE_WQE_RESERVED_MASK          0x1
 706 #define FCOE_WQE_RESERVED_SHIFT         7
 707 #define FCOE_WQE_NUM_SGES_MASK          0xF
 708 #define FCOE_WQE_NUM_SGES_SHIFT         8
 709 #define FCOE_WQE_RESERVED1_MASK         0xF
 710 #define FCOE_WQE_RESERVED1_SHIFT        12
 711         union fcoe_additional_info_union additional_info_union;
 712 };
 713
 714 /* FCoE XFRQ element */
 715 struct xfrqe_prot_flags {
 716         u8 flags;
 717 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK    0xF
 718 #define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT   0
 719 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK               0x1
 720 #define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT              4
 721 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK            0x3
 722 #define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT           5
 723 #define XFRQE_PROT_FLAGS_RESERVED_MASK                  0x1
 724 #define XFRQE_PROT_FLAGS_RESERVED_SHIFT                 7
 725 };
 726
 727 /* FCoE doorbell data */
 728 struct fcoe_db_data {
 729         u8 params;
 730 #define FCOE_DB_DATA_DEST_MASK          0x3
 731 #define FCOE_DB_DATA_DEST_SHIFT         0
 732 #define FCOE_DB_DATA_AGG_CMD_MASK       0x3
 733 #define FCOE_DB_DATA_AGG_CMD_SHIFT      2
 734 #define FCOE_DB_DATA_BYPASS_EN_MASK     0x1
 735 #define FCOE_DB_DATA_BYPASS_EN_SHIFT    4
 736 #define FCOE_DB_DATA_RESERVED_MASK      0x1
 737 #define FCOE_DB_DATA_RESERVED_SHIFT     5
 738 #define FCOE_DB_DATA_AGG_VAL_SEL_MASK   0x3
 739 #define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT  6
 740         u8 agg_flags;
 741         __le16 sq_prod;
 742 };
 743
 744 #endif /* __FCOE_COMMON__ */