include/linux/stmmac.h

   1 /*******************************************************************************
   2
   3   Header file for stmmac platform data
   4
   5   Copyright (C) 2009  STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24 *******************************************************************************/
  25
  26 #ifndef __STMMAC_PLATFORM_DATA
  27 #define __STMMAC_PLATFORM_DATA
  28
  29 #include <linux/platform_device.h>
  30
  31 #define MTL_MAX_RX_QUEUES       8
  32 #define MTL_MAX_TX_QUEUES       8
  33
  34 #define STMMAC_RX_COE_NONE      0
  35 #define STMMAC_RX_COE_TYPE1     1
  36 #define STMMAC_RX_COE_TYPE2     2
  37
  38 /* Define the macros for CSR clock range parameters to be passed by
  39  * platform code.
  40  * This could also be configured at run time using CPU freq framework. */
  41
  42 /* MDC Clock Selection define*/
  43 #define STMMAC_CSR_60_100M      0x0     /* MDC = clk_scr_i/42 */
  44 #define STMMAC_CSR_100_150M     0x1     /* MDC = clk_scr_i/62 */
  45 #define STMMAC_CSR_20_35M       0x2     /* MDC = clk_scr_i/16 */
  46 #define STMMAC_CSR_35_60M       0x3     /* MDC = clk_scr_i/26 */
  47 #define STMMAC_CSR_150_250M     0x4     /* MDC = clk_scr_i/102 */
  48 #define STMMAC_CSR_250_300M     0x5     /* MDC = clk_scr_i/122 */
  49
  50 /* MTL algorithms identifiers */
  51 #define MTL_TX_ALGORITHM_WRR    0x0
  52 #define MTL_TX_ALGORITHM_WFQ    0x1
  53 #define MTL_TX_ALGORITHM_DWRR   0x2
  54 #define MTL_TX_ALGORITHM_SP     0x3
  55 #define MTL_RX_ALGORITHM_SP     0x4
  56 #define MTL_RX_ALGORITHM_WSP    0x5
  57
  58 /* RX/TX Queue Mode */
  59 #define MTL_QUEUE_AVB           0x0
  60 #define MTL_QUEUE_DCB           0x1
  61
  62 /* The MDC clock could be set higher than the IEEE 802.3
  63  * specified frequency limit 0f 2.5 MHz, by programming a clock divider
  64  * of value different than the above defined values. The resultant MDIO
  65  * clock frequency of 12.5 MHz is applicable for the interfacing chips
  66  * supporting higher MDC clocks.
  67  * The MDC clock selection macros need to be defined for MDC clock rate
  68  * of 12.5 MHz, corresponding to the following selection.
  69  */
  70 #define STMMAC_CSR_I_4          0x8     /* clk_csr_i/4 */
  71 #define STMMAC_CSR_I_6          0x9     /* clk_csr_i/6 */
  72 #define STMMAC_CSR_I_8          0xA     /* clk_csr_i/8 */
  73 #define STMMAC_CSR_I_10         0xB     /* clk_csr_i/10 */
  74 #define STMMAC_CSR_I_12         0xC     /* clk_csr_i/12 */
  75 #define STMMAC_CSR_I_14         0xD     /* clk_csr_i/14 */
  76 #define STMMAC_CSR_I_16         0xE     /* clk_csr_i/16 */
  77 #define STMMAC_CSR_I_18         0xF     /* clk_csr_i/18 */
  78
  79 /* AXI DMA Burst length supported */
  80 #define DMA_AXI_BLEN_4          (1 << 1)
  81 #define DMA_AXI_BLEN_8          (1 << 2)
  82 #define DMA_AXI_BLEN_16         (1 << 3)
  83 #define DMA_AXI_BLEN_32         (1 << 4)
  84 #define DMA_AXI_BLEN_64         (1 << 5)
  85 #define DMA_AXI_BLEN_128        (1 << 6)
  86 #define DMA_AXI_BLEN_256        (1 << 7)
  87 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
  88                         | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
  89                         | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
  90
  91 /* Platfrom data for platform device structure's platform_data field */
  92
  93 struct stmmac_mdio_bus_data {
  94         int (*phy_reset)(void *priv);
  95         unsigned int phy_mask;
  96         int *irqs;
  97         int probed_phy_irq;
  98 #ifdef CONFIG_OF
  99         int reset_gpio, active_low;
 100         u32 delays[3];
 101 #endif
 102 };
 103
 104 struct stmmac_dma_cfg {
 105         int pbl;
 106         int txpbl;
 107         int rxpbl;
 108         bool pblx8;
 109         int fixed_burst;
 110         int mixed_burst;
 111         bool aal;
 112 };
 113
 114 #define AXI_BLEN        7
 115 struct stmmac_axi {
 116         bool axi_lpi_en;
 117         bool axi_xit_frm;
 118         u32 axi_wr_osr_lmt;
 119         u32 axi_rd_osr_lmt;
 120         bool axi_kbbe;
 121         u32 axi_blen[AXI_BLEN];
 122         bool axi_fb;
 123         bool axi_mb;
 124         bool axi_rb;
 125 };
 126
 127 struct stmmac_rxq_cfg {
 128         u8 mode_to_use;
 129         u32 chan;
 130         u8 pkt_route;
 131         bool use_prio;
 132         u32 prio;
 133 };
 134
 135 struct stmmac_txq_cfg {
 136         u32 weight;
 137         u8 mode_to_use;
 138         /* Credit Base Shaper parameters */
 139         u32 send_slope;
 140         u32 idle_slope;
 141         u32 high_credit;
 142         u32 low_credit;
 143         bool use_prio;
 144         u32 prio;
 145 };
 146
 147 struct plat_stmmacenet_data {
 148         int bus_id;
 149         int phy_addr;
 150         int interface;
 151         struct stmmac_mdio_bus_data *mdio_bus_data;
 152         struct device_node *phy_node;
 153         struct device_node *mdio_node;
 154         struct stmmac_dma_cfg *dma_cfg;
 155         int clk_csr;
 156         int has_gmac;
 157         int enh_desc;
 158         int tx_coe;
 159         int rx_coe;
 160         int bugged_jumbo;
 161         int pmt;
 162         int force_sf_dma_mode;
 163         int force_thresh_dma_mode;
 164         int riwt_off;
 165         int max_speed;
 166         int maxmtu;
 167         int multicast_filter_bins;
 168         int unicast_filter_entries;
 169         int tx_fifo_size;
 170         int rx_fifo_size;
 171         u32 rx_queues_to_use;
 172         u32 tx_queues_to_use;
 173         u8 rx_sched_algorithm;
 174         u8 tx_sched_algorithm;
 175         struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
 176         struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
 177         void (*fix_mac_speed)(void *priv, unsigned int speed);
 178         int (*init)(struct platform_device *pdev, void *priv);
 179         void (*exit)(struct platform_device *pdev, void *priv);
 180         struct mac_device_info *(*setup)(void *priv);
 181         void *bsp_priv;
 182         struct clk *stmmac_clk;
 183         struct clk *pclk;
 184         struct clk *clk_ptp_ref;
 185         unsigned int clk_ptp_rate;
 186         struct reset_control *stmmac_rst;
 187         struct stmmac_axi *axi;
 188         int has_gmac4;
 189         bool has_sun8i;
 190         bool tso_en;
 191         int mac_port_sel_speed;
 192         bool en_tx_lpi_clockgating;
 193 };
 194 #endif