| blob | 6e61ae20d01a064f5a2085de83fdcd9e4a361c18 |
1 [
2 {
3 "EventCode": "0x63",
4 "Counter": "0,1",
5 "UMask": "0x2",
6 "EventName": "CACHE_LOCK_CYCLES.L1D",
7 "SampleAfterValue": "2000000",
8 "BriefDescription": "Cycles L1D locked"
9 },
10 {
11 "EventCode": "0x63",
12 "Counter": "0,1",
13 "UMask": "0x1",
14 "EventName": "CACHE_LOCK_CYCLES.L1D_L2",
15 "SampleAfterValue": "2000000",
16 "BriefDescription": "Cycles L1D and L2 locked"
17 },
18 {
19 "EventCode": "0x51",
20 "Counter": "0,1",
21 "UMask": "0x4",
22 "EventName": "L1D.M_EVICT",
23 "SampleAfterValue": "2000000",
24 "BriefDescription": "L1D cache lines replaced in M state"
25 },
26 {
27 "EventCode": "0x51",
28 "Counter": "0,1",
29 "UMask": "0x2",
30 "EventName": "L1D.M_REPL",
31 "SampleAfterValue": "2000000",
32 "BriefDescription": "L1D cache lines allocated in the M state"
33 },
34 {
35 "EventCode": "0x51",
36 "Counter": "0,1",
37 "UMask": "0x8",
38 "EventName": "L1D.M_SNOOP_EVICT",
39 "SampleAfterValue": "2000000",
40 "BriefDescription": "L1D snoop eviction of cache lines in M state"
41 },
42 {
43 "EventCode": "0x51",
44 "Counter": "0,1",
45 "UMask": "0x1",
46 "EventName": "L1D.REPL",
47 "SampleAfterValue": "2000000",
48 "BriefDescription": "L1 data cache lines allocated"
49 },
50 {
51 "EventCode": "0x52",
52 "Counter": "0,1",
53 "UMask": "0x1",
54 "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT",
55 "SampleAfterValue": "2000000",
56 "BriefDescription": "L1D prefetch load lock accepted in fill buffer"
57 },
58 {
59 "EventCode": "0x4E",
60 "Counter": "0,1",
61 "UMask": "0x2",
62 "EventName": "L1D_PREFETCH.MISS",
63 "SampleAfterValue": "200000",
64 "BriefDescription": "L1D hardware prefetch misses"
65 },
66 {
67 "EventCode": "0x4E",
68 "Counter": "0,1",
69 "UMask": "0x1",
70 "EventName": "L1D_PREFETCH.REQUESTS",
71 "SampleAfterValue": "200000",
72 "BriefDescription": "L1D hardware prefetch requests"
73 },
74 {
75 "EventCode": "0x4E",
76 "Counter": "0,1",
77 "UMask": "0x4",
78 "EventName": "L1D_PREFETCH.TRIGGERS",
79 "SampleAfterValue": "200000",
80 "BriefDescription": "L1D hardware prefetch requests triggered"
81 },
82 {
83 "EventCode": "0x28",
84 "Counter": "0,1,2,3",
85 "UMask": "0x4",
86 "EventName": "L1D_WB_L2.E_STATE",
87 "SampleAfterValue": "100000",
88 "BriefDescription": "L1 writebacks to L2 in E state"
89 },
90 {
91 "EventCode": "0x28",
92 "Counter": "0,1,2,3",
93 "UMask": "0x1",
94 "EventName": "L1D_WB_L2.I_STATE",
95 "SampleAfterValue": "100000",
96 "BriefDescription": "L1 writebacks to L2 in I state (misses)"
97 },
98 {
99 "EventCode": "0x28",
100 "Counter": "0,1,2,3",
101 "UMask": "0x8",
102 "EventName": "L1D_WB_L2.M_STATE",
103 "SampleAfterValue": "100000",
104 "BriefDescription": "L1 writebacks to L2 in M state"
105 },
106 {
107 "EventCode": "0x28",
108 "Counter": "0,1,2,3",
109 "UMask": "0xf",
110 "EventName": "L1D_WB_L2.MESI",
111 "SampleAfterValue": "100000",
112 "BriefDescription": "All L1 writebacks to L2"
113 },
114 {
115 "EventCode": "0x28",
116 "Counter": "0,1,2,3",
117 "UMask": "0x2",
118 "EventName": "L1D_WB_L2.S_STATE",
119 "SampleAfterValue": "100000",
120 "BriefDescription": "L1 writebacks to L2 in S state"
121 },
122 {
123 "EventCode": "0x26",
124 "Counter": "0,1,2,3",
125 "UMask": "0xff",
126 "EventName": "L2_DATA_RQSTS.ANY",
127 "SampleAfterValue": "200000",
128 "BriefDescription": "All L2 data requests"
129 },
130 {
131 "EventCode": "0x26",
132 "Counter": "0,1,2,3",
133 "UMask": "0x4",
134 "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE",
135 "SampleAfterValue": "200000",
136 "BriefDescription": "L2 data demand loads in E state"
137 },
138 {
139 "EventCode": "0x26",
140 "Counter": "0,1,2,3",
141 "UMask": "0x1",
142 "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE",
143 "SampleAfterValue": "200000",
144 "BriefDescription": "L2 data demand loads in I state (misses)"
145 },
146 {
147 "EventCode": "0x26",
148 "Counter": "0,1,2,3",
149 "UMask": "0x8",
150 "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE",
151 "SampleAfterValue": "200000",
152 "BriefDescription": "L2 data demand loads in M state"
153 },
154 {
155 "EventCode": "0x26",
156 "Counter": "0,1,2,3",
157 "UMask": "0xf",
158 "EventName": "L2_DATA_RQSTS.DEMAND.MESI",
159 "SampleAfterValue": "200000",
160 "BriefDescription": "L2 data demand requests"
161 },
162 {
163 "EventCode": "0x26",
164 "Counter": "0,1,2,3",
165 "UMask": "0x2",
166 "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE",
167 "SampleAfterValue": "200000",
168 "BriefDescription": "L2 data demand loads in S state"
169 },
170 {
171 "EventCode": "0x26",
172 "Counter": "0,1,2,3",
173 "UMask": "0x40",
174 "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE",
175 "SampleAfterValue": "200000",
176 "BriefDescription": "L2 data prefetches in E state"
177 },
178 {
179 "EventCode": "0x26",
180 "Counter": "0,1,2,3",
181 "UMask": "0x10",
182 "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE",
183 "SampleAfterValue": "200000",
184 "BriefDescription": "L2 data prefetches in the I state (misses)"
185 },
186 {
187 "EventCode": "0x26",
188 "Counter": "0,1,2,3",
189 "UMask": "0x80",
190 "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE",
191 "SampleAfterValue": "200000",
192 "BriefDescription": "L2 data prefetches in M state"
193 },
194 {
195 "EventCode": "0x26",
196 "Counter": "0,1,2,3",
197 "UMask": "0xf0",
198 "EventName": "L2_DATA_RQSTS.PREFETCH.MESI",
199 "SampleAfterValue": "200000",
200 "BriefDescription": "All L2 data prefetches"
201 },
202 {
203 "EventCode": "0x26",
204 "Counter": "0,1,2,3",
205 "UMask": "0x20",
206 "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE",
207 "SampleAfterValue": "200000",
208 "BriefDescription": "L2 data prefetches in the S state"
209 },
210 {
211 "EventCode": "0xF1",
212 "Counter": "0,1,2,3",
213 "UMask": "0x7",
214 "EventName": "L2_LINES_IN.ANY",
215 "SampleAfterValue": "100000",
216 "BriefDescription": "L2 lines alloacated"
217 },
218 {
219 "EventCode": "0xF1",
220 "Counter": "0,1,2,3",
221 "UMask": "0x4",
222 "EventName": "L2_LINES_IN.E_STATE",
223 "SampleAfterValue": "100000",
224 "BriefDescription": "L2 lines allocated in the E state"
225 },
226 {
227 "EventCode": "0xF1",
228 "Counter": "0,1,2,3",
229 "UMask": "0x2",
230 "EventName": "L2_LINES_IN.S_STATE",
231 "SampleAfterValue": "100000",
232 "BriefDescription": "L2 lines allocated in the S state"
233 },
234 {
235 "EventCode": "0xF2",
236 "Counter": "0,1,2,3",
237 "UMask": "0xf",
238 "EventName": "L2_LINES_OUT.ANY",
239 "SampleAfterValue": "100000",
240 "BriefDescription": "L2 lines evicted"
241 },
242 {
243 "EventCode": "0xF2",
244 "Counter": "0,1,2,3",
245 "UMask": "0x1",
246 "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
247 "SampleAfterValue": "100000",
248 "BriefDescription": "L2 lines evicted by a demand request"
249 },
250 {
251 "EventCode": "0xF2",
252 "Counter": "0,1,2,3",
253 "UMask": "0x2",
254 "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
255 "SampleAfterValue": "100000",
256 "BriefDescription": "L2 modified lines evicted by a demand request"
257 },
258 {
259 "EventCode": "0xF2",
260 "Counter": "0,1,2,3",
261 "UMask": "0x4",
262 "EventName": "L2_LINES_OUT.PREFETCH_CLEAN",
263 "SampleAfterValue": "100000",
264 "BriefDescription": "L2 lines evicted by a prefetch request"
265 },
266 {
267 "EventCode": "0xF2",
268 "Counter": "0,1,2,3",
269 "UMask": "0x8",
270 "EventName": "L2_LINES_OUT.PREFETCH_DIRTY",
271 "SampleAfterValue": "100000",
272 "BriefDescription": "L2 modified lines evicted by a prefetch request"
273 },
274 {
275 "EventCode": "0x24",
276 "Counter": "0,1,2,3",
277 "UMask": "0x10",
278 "EventName": "L2_RQSTS.IFETCH_HIT",
279 "SampleAfterValue": "200000",
280 "BriefDescription": "L2 instruction fetch hits"
281 },
282 {
283 "EventCode": "0x24",
284 "Counter": "0,1,2,3",
285 "UMask": "0x20",
286 "EventName": "L2_RQSTS.IFETCH_MISS",
287 "SampleAfterValue": "200000",
288 "BriefDescription": "L2 instruction fetch misses"
289 },
290 {
291 "EventCode": "0x24",
292 "Counter": "0,1,2,3",
293 "UMask": "0x30",
294 "EventName": "L2_RQSTS.IFETCHES",
295 "SampleAfterValue": "200000",
296 "BriefDescription": "L2 instruction fetches"
297 },
298 {
299 "EventCode": "0x24",
300 "Counter": "0,1,2,3",
301 "UMask": "0x1",
302 "EventName": "L2_RQSTS.LD_HIT",
303 "SampleAfterValue": "200000",
304 "BriefDescription": "L2 load hits"
305 },
306 {
307 "EventCode": "0x24",
308 "Counter": "0,1,2,3",
309 "UMask": "0x2",
310 "EventName": "L2_RQSTS.LD_MISS",
311 "SampleAfterValue": "200000",
312 "BriefDescription": "L2 load misses"
313 },
314 {
315 "EventCode": "0x24",
316 "Counter": "0,1,2,3",
317 "UMask": "0x3",
318 "EventName": "L2_RQSTS.LOADS",
319 "SampleAfterValue": "200000",
320 "BriefDescription": "L2 requests"
321 },
322 {
323 "EventCode": "0x24",
324 "Counter": "0,1,2,3",
325 "UMask": "0xaa",
326 "EventName": "L2_RQSTS.MISS",
327 "SampleAfterValue": "200000",
328 "BriefDescription": "All L2 misses"
329 },
330 {
331 "EventCode": "0x24",
332 "Counter": "0,1,2,3",
333 "UMask": "0x40",
334 "EventName": "L2_RQSTS.PREFETCH_HIT",
335 "SampleAfterValue": "200000",
336 "BriefDescription": "L2 prefetch hits"
337 },
338 {
339 "EventCode": "0x24",
340 "Counter": "0,1,2,3",
341 "UMask": "0x80",
342 "EventName": "L2_RQSTS.PREFETCH_MISS",
343 "SampleAfterValue": "200000",
344 "BriefDescription": "L2 prefetch misses"
345 },
346 {
347 "EventCode": "0x24",
348 "Counter": "0,1,2,3",
349 "UMask": "0xc0",
350 "EventName": "L2_RQSTS.PREFETCHES",
351 "SampleAfterValue": "200000",
352 "BriefDescription": "All L2 prefetches"
353 },
354 {
355 "EventCode": "0x24",
356 "Counter": "0,1,2,3",
357 "UMask": "0xff",
358 "EventName": "L2_RQSTS.REFERENCES",
359 "SampleAfterValue": "200000",
360 "BriefDescription": "All L2 requests"
361 },
362 {
363 "EventCode": "0x24",
364 "Counter": "0,1,2,3",
365 "UMask": "0x4",
366 "EventName": "L2_RQSTS.RFO_HIT",
367 "SampleAfterValue": "200000",
368 "BriefDescription": "L2 RFO hits"
369 },
370 {
371 "EventCode": "0x24",
372 "Counter": "0,1,2,3",
373 "UMask": "0x8",
374 "EventName": "L2_RQSTS.RFO_MISS",
375 "SampleAfterValue": "200000",
376 "BriefDescription": "L2 RFO misses"
377 },
378 {
379 "EventCode": "0x24",
380 "Counter": "0,1,2,3",
381 "UMask": "0xc",
382 "EventName": "L2_RQSTS.RFOS",
383 "SampleAfterValue": "200000",
384 "BriefDescription": "L2 RFO requests"
385 },
386 {
387 "EventCode": "0xF0",
388 "Counter": "0,1,2,3",
389 "UMask": "0x80",
390 "EventName": "L2_TRANSACTIONS.ANY",
391 "SampleAfterValue": "200000",
392 "BriefDescription": "All L2 transactions"
393 },
394 {
395 "EventCode": "0xF0",
396 "Counter": "0,1,2,3",
397 "UMask": "0x20",
398 "EventName": "L2_TRANSACTIONS.FILL",
399 "SampleAfterValue": "200000",
400 "BriefDescription": "L2 fill transactions"
401 },
402 {
403 "EventCode": "0xF0",
404 "Counter": "0,1,2,3",
405 "UMask": "0x4",
406 "EventName": "L2_TRANSACTIONS.IFETCH",
407 "SampleAfterValue": "200000",
408 "BriefDescription": "L2 instruction fetch transactions"
409 },
410 {
411 "EventCode": "0xF0",
412 "Counter": "0,1,2,3",
413 "UMask": "0x10",
414 "EventName": "L2_TRANSACTIONS.L1D_WB",
415 "SampleAfterValue": "200000",
416 "BriefDescription": "L1D writeback to L2 transactions"
417 },
418 {
419 "EventCode": "0xF0",
420 "Counter": "0,1,2,3",
421 "UMask": "0x1",
422 "EventName": "L2_TRANSACTIONS.LOAD",
423 "SampleAfterValue": "200000",
424 "BriefDescription": "L2 Load transactions"
425 },
426 {
427 "EventCode": "0xF0",
428 "Counter": "0,1,2,3",
429 "UMask": "0x8",
430 "EventName": "L2_TRANSACTIONS.PREFETCH",
431 "SampleAfterValue": "200000",
432 "BriefDescription": "L2 prefetch transactions"
433 },
434 {
435 "EventCode": "0xF0",
436 "Counter": "0,1,2,3",
437 "UMask": "0x2",
438 "EventName": "L2_TRANSACTIONS.RFO",
439 "SampleAfterValue": "200000",
440 "BriefDescription": "L2 RFO transactions"
441 },
442 {
443 "EventCode": "0xF0",
444 "Counter": "0,1,2,3",
445 "UMask": "0x40",
446 "EventName": "L2_TRANSACTIONS.WB",
447 "SampleAfterValue": "200000",
448 "BriefDescription": "L2 writeback to LLC transactions"
449 },
450 {
451 "EventCode": "0x27",
452 "Counter": "0,1,2,3",
453 "UMask": "0x40",
454 "EventName": "L2_WRITE.LOCK.E_STATE",
455 "SampleAfterValue": "100000",
456 "BriefDescription": "L2 demand lock RFOs in E state"
457 },
458 {
459 "EventCode": "0x27",
460 "Counter": "0,1,2,3",
461 "UMask": "0xe0",
462 "EventName": "L2_WRITE.LOCK.HIT",
463 "SampleAfterValue": "100000",
464 "BriefDescription": "All demand L2 lock RFOs that hit the cache"
465 },
466 {
467 "EventCode": "0x27",
468 "Counter": "0,1,2,3",
469 "UMask": "0x10",
470 "EventName": "L2_WRITE.LOCK.I_STATE",
471 "SampleAfterValue": "100000",
472 "BriefDescription": "L2 demand lock RFOs in I state (misses)"
473 },
474 {
475 "EventCode": "0x27",
476 "Counter": "0,1,2,3",
477 "UMask": "0x80",
478 "EventName": "L2_WRITE.LOCK.M_STATE",
479 "SampleAfterValue": "100000",
480 "BriefDescription": "L2 demand lock RFOs in M state"
481 },
482 {
483 "EventCode": "0x27",
484 "Counter": "0,1,2,3",
485 "UMask": "0xf0",
486 "EventName": "L2_WRITE.LOCK.MESI",
487 "SampleAfterValue": "100000",
488 "BriefDescription": "All demand L2 lock RFOs"
489 },
490 {
491 "EventCode": "0x27",
492 "Counter": "0,1,2,3",
493 "UMask": "0x20",
494 "EventName": "L2_WRITE.LOCK.S_STATE",
495 "SampleAfterValue": "100000",
496 "BriefDescription": "L2 demand lock RFOs in S state"
497 },
498 {
499 "EventCode": "0x27",
500 "Counter": "0,1,2,3",
501 "UMask": "0xe",
502 "EventName": "L2_WRITE.RFO.HIT",
503 "SampleAfterValue": "100000",
504 "BriefDescription": "All L2 demand store RFOs that hit the cache"
505 },
506 {
507 "EventCode": "0x27",
508 "Counter": "0,1,2,3",
509 "UMask": "0x1",
510 "EventName": "L2_WRITE.RFO.I_STATE",
511 "SampleAfterValue": "100000",
512 "BriefDescription": "L2 demand store RFOs in I state (misses)"
513 },
514 {
515 "EventCode": "0x27",
516 "Counter": "0,1,2,3",
517 "UMask": "0x8",
518 "EventName": "L2_WRITE.RFO.M_STATE",
519 "SampleAfterValue": "100000",
520 "BriefDescription": "L2 demand store RFOs in M state"
521 },
522 {
523 "EventCode": "0x27",
524 "Counter": "0,1,2,3",
525 "UMask": "0xf",
526 "EventName": "L2_WRITE.RFO.MESI",
527 "SampleAfterValue": "100000",
528 "BriefDescription": "All L2 demand store RFOs"
529 },
530 {
531 "EventCode": "0x27",
532 "Counter": "0,1,2,3",
533 "UMask": "0x2",
534 "EventName": "L2_WRITE.RFO.S_STATE",
535 "SampleAfterValue": "100000",
536 "BriefDescription": "L2 demand store RFOs in S state"
537 },
538 {
539 "EventCode": "0x2E",
540 "Counter": "0,1,2,3",
541 "UMask": "0x41",
542 "EventName": "LONGEST_LAT_CACHE.MISS",
543 "SampleAfterValue": "100000",
544 "BriefDescription": "Longest latency cache miss"
545 },
546 {
547 "EventCode": "0x2E",
548 "Counter": "0,1,2,3",
549 "UMask": "0x4f",
550 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
551 "SampleAfterValue": "200000",
552 "BriefDescription": "Longest latency cache reference"
553 },
554 {
555 "PEBS": "1",
556 "EventCode": "0xB",
557 "Counter": "0,1,2,3",
558 "UMask": "0x1",
559 "EventName": "MEM_INST_RETIRED.LOADS",
560 "SampleAfterValue": "2000000",
561 "BriefDescription": "Instructions retired which contains a load (Precise Event)"
562 },
563 {
564 "PEBS": "1",
565 "EventCode": "0xB",
566 "Counter": "0,1,2,3",
567 "UMask": "0x2",
568 "EventName": "MEM_INST_RETIRED.STORES",
569 "SampleAfterValue": "2000000",
570 "BriefDescription": "Instructions retired which contains a store (Precise Event)"
571 },
572 {
573 "PEBS": "1",
574 "EventCode": "0xCB",
575 "Counter": "0,1,2,3",
576 "UMask": "0x40",
577 "EventName": "MEM_LOAD_RETIRED.HIT_LFB",
578 "SampleAfterValue": "200000",
579 "BriefDescription": "Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)"
580 },
581 {
582 "PEBS": "1",
583 "EventCode": "0xCB",
584 "Counter": "0,1,2,3",
585 "UMask": "0x1",
586 "EventName": "MEM_LOAD_RETIRED.L1D_HIT",
587 "SampleAfterValue": "2000000",
588 "BriefDescription": "Retired loads that hit the L1 data cache (Precise Event)"
589 },
590 {
591 "PEBS": "1",
592 "EventCode": "0xCB",
593 "Counter": "0,1,2,3",
594 "UMask": "0x2",
595 "EventName": "MEM_LOAD_RETIRED.L2_HIT",
596 "SampleAfterValue": "200000",
597 "BriefDescription": "Retired loads that hit the L2 cache (Precise Event)"
598 },
599 {
600 "PEBS": "1",
601 "EventCode": "0xCB",
602 "Counter": "0,1,2,3",
603 "UMask": "0x10",
604 "EventName": "MEM_LOAD_RETIRED.LLC_MISS",
605 "SampleAfterValue": "10000",
606 "BriefDescription": "Retired loads that miss the LLC cache (Precise Event)"
607 },
608 {
609 "PEBS": "1",
610 "EventCode": "0xCB",
611 "Counter": "0,1,2,3",
612 "UMask": "0x4",
613 "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT",
614 "SampleAfterValue": "40000",
615 "BriefDescription": "Retired loads that hit valid versions in the LLC cache (Precise Event)"
616 },
617 {
618 "PEBS": "1",
619 "EventCode": "0xCB",
620 "Counter": "0,1,2,3",
621 "UMask": "0x8",
622 "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM",
623 "SampleAfterValue": "40000",
624 "BriefDescription": "Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)"
625 },
626 {
627 "EventCode": "0xB0",
628 "Counter": "0,1,2,3",
629 "UMask": "0x80",
630 "EventName": "OFFCORE_REQUESTS.ANY",
631 "SampleAfterValue": "100000",
632 "BriefDescription": "All offcore requests"
633 },
634 {
635 "EventCode": "0xB0",
636 "Counter": "0,1,2,3",
637 "UMask": "0x8",
638 "EventName": "OFFCORE_REQUESTS.ANY.READ",
639 "SampleAfterValue": "100000",
640 "BriefDescription": "Offcore read requests"
641 },
642 {
643 "EventCode": "0xB0",
644 "Counter": "0,1,2,3",
645 "UMask": "0x10",
646 "EventName": "OFFCORE_REQUESTS.ANY.RFO",
647 "SampleAfterValue": "100000",
648 "BriefDescription": "Offcore RFO requests"
649 },
650 {
651 "EventCode": "0xB0",
652 "Counter": "0,1,2,3",
653 "UMask": "0x2",
654 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE",
655 "SampleAfterValue": "100000",
656 "BriefDescription": "Offcore demand code read requests"
657 },
658 {
659 "EventCode": "0xB0",
660 "Counter": "0,1,2,3",
661 "UMask": "0x1",
662 "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA",
663 "SampleAfterValue": "100000",
664 "BriefDescription": "Offcore demand data read requests"
665 },
666 {
667 "EventCode": "0xB0",
668 "Counter": "0,1,2,3",
669 "UMask": "0x4",
670 "EventName": "OFFCORE_REQUESTS.DEMAND.RFO",
671 "SampleAfterValue": "100000",
672 "BriefDescription": "Offcore demand RFO requests"
673 },
674 {
675 "EventCode": "0xB0",
676 "Counter": "0,1,2,3",
677 "UMask": "0x40",
678 "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK",
679 "SampleAfterValue": "100000",
680 "BriefDescription": "Offcore L1 data cache writebacks"
681 },
682 {
683 "EventCode": "0x60",
684 "UMask": "0x8",
685 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ",
686 "SampleAfterValue": "2000000",
687 "BriefDescription": "Outstanding offcore reads"
688 },
689 {
690 "EventCode": "0x60",
691 "UMask": "0x8",
692 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY",
693 "SampleAfterValue": "2000000",
694 "BriefDescription": "Cycles offcore reads busy",
695 "CounterMask": "1"
696 },
697 {
698 "EventCode": "0x60",
699 "UMask": "0x2",
700 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE",
701 "SampleAfterValue": "2000000",
702 "BriefDescription": "Outstanding offcore demand code reads"
703 },
704 {
705 "EventCode": "0x60",
706 "UMask": "0x2",
707 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY",
708 "SampleAfterValue": "2000000",
709 "BriefDescription": "Cycles offcore demand code read busy",
710 "CounterMask": "1"
711 },
712 {
713 "EventCode": "0x60",
714 "UMask": "0x1",
715 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA",
716 "SampleAfterValue": "2000000",
717 "BriefDescription": "Outstanding offcore demand data reads"
718 },
719 {
720 "EventCode": "0x60",
721 "UMask": "0x1",
722 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY",
723 "SampleAfterValue": "2000000",
724 "BriefDescription": "Cycles offcore demand data read busy",
725 "CounterMask": "1"
726 },
727 {
728 "EventCode": "0x60",
729 "UMask": "0x4",
730 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO",
731 "SampleAfterValue": "2000000",
732 "BriefDescription": "Outstanding offcore demand RFOs"
733 },
734 {
735 "EventCode": "0x60",
736 "UMask": "0x4",
737 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY",
738 "SampleAfterValue": "2000000",
739 "BriefDescription": "Cycles offcore demand RFOs busy",
740 "CounterMask": "1"
741 },
742 {
743 "EventCode": "0xB2",
744 "Counter": "0,1,2,3",
745 "UMask": "0x1",
746 "EventName": "OFFCORE_REQUESTS_SQ_FULL",
747 "SampleAfterValue": "100000",
748 "BriefDescription": "Offcore requests blocked due to Super Queue full"
749 },
750 {
751 "EventCode": "0xF4",
752 "Counter": "0,1,2,3",
753 "UMask": "0x4",
754 "EventName": "SQ_MISC.LRU_HINTS",
755 "SampleAfterValue": "2000000",
756 "BriefDescription": "Super Queue LRU hints sent to LLC"
757 },
758 {
759 "EventCode": "0xF4",
760 "Counter": "0,1,2,3",
761 "UMask": "0x10",
762 "EventName": "SQ_MISC.SPLIT_LOCK",
763 "SampleAfterValue": "2000000",
764 "BriefDescription": "Super Queue lock splits across a cache line"
765 },
766 {
767 "EventCode": "0x6",
768 "Counter": "0,1,2,3",
769 "UMask": "0x4",
770 "EventName": "STORE_BLOCKS.AT_RET",
771 "SampleAfterValue": "200000",
772 "BriefDescription": "Loads delayed with at-Retirement block code"
773 },
774 {
775 "EventCode": "0x6",
776 "Counter": "0,1,2,3",
777 "UMask": "0x8",
778 "EventName": "STORE_BLOCKS.L1D_BLOCK",
779 "SampleAfterValue": "200000",
780 "BriefDescription": "Cacheable loads delayed with L1D block code"
781 },
782 {
783 "PEBS": "2",
784 "EventCode": "0xB",
785 "MSRValue": "0x0",
786 "Counter": "3",
787 "UMask": "0x10",
788 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0",
789 "MSRIndex": "0x3F6",
790 "SampleAfterValue": "2000000",
791 "BriefDescription": "Memory instructions retired above 0 clocks (Precise Event)"
792 },
793 {
794 "PEBS": "2",
795 "EventCode": "0xB",
796 "MSRValue": "0x400",
797 "Counter": "3",
798 "UMask": "0x10",
799 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024",
800 "MSRIndex": "0x3F6",
801 "SampleAfterValue": "100",
802 "BriefDescription": "Memory instructions retired above 1024 clocks (Precise Event)"
803 },
804 {
805 "PEBS": "2",
806 "EventCode": "0xB",
807 "MSRValue": "0x80",
808 "Counter": "3",
809 "UMask": "0x10",
810 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128",
811 "MSRIndex": "0x3F6",
812 "SampleAfterValue": "1000",
813 "BriefDescription": "Memory instructions retired above 128 clocks (Precise Event)"
814 },
815 {
816 "PEBS": "2",
817 "EventCode": "0xB",
818 "MSRValue": "0x10",
819 "Counter": "3",
820 "UMask": "0x10",
821 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16",
822 "MSRIndex": "0x3F6",
823 "SampleAfterValue": "10000",
824 "BriefDescription": "Memory instructions retired above 16 clocks (Precise Event)"
825 },
826 {
827 "PEBS": "2",
828 "EventCode": "0xB",
829 "MSRValue": "0x4000",
830 "Counter": "3",
831 "UMask": "0x10",
832 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384",
833 "MSRIndex": "0x3F6",
834 "SampleAfterValue": "5",
835 "BriefDescription": "Memory instructions retired above 16384 clocks (Precise Event)"
836 },
837 {
838 "PEBS": "2",
839 "EventCode": "0xB",
840 "MSRValue": "0x800",
841 "Counter": "3",
842 "UMask": "0x10",
843 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048",
844 "MSRIndex": "0x3F6",
845 "SampleAfterValue": "50",
846 "BriefDescription": "Memory instructions retired above 2048 clocks (Precise Event)"
847 },
848 {
849 "PEBS": "2",
850 "EventCode": "0xB",
851 "MSRValue": "0x100",
852 "Counter": "3",
853 "UMask": "0x10",
854 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256",
855 "MSRIndex": "0x3F6",
856 "SampleAfterValue": "500",
857 "BriefDescription": "Memory instructions retired above 256 clocks (Precise Event)"
858 },
859 {
860 "PEBS": "2",
861 "EventCode": "0xB",
862 "MSRValue": "0x20",
863 "Counter": "3",
864 "UMask": "0x10",
865 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32",
866 "MSRIndex": "0x3F6",
867 "SampleAfterValue": "5000",
868 "BriefDescription": "Memory instructions retired above 32 clocks (Precise Event)"
869 },
870 {
871 "PEBS": "2",
872 "EventCode": "0xB",
873 "MSRValue": "0x8000",
874 "Counter": "3",
875 "UMask": "0x10",
876 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768",
877 "MSRIndex": "0x3F6",
878 "SampleAfterValue": "3",
879 "BriefDescription": "Memory instructions retired above 32768 clocks (Precise Event)"
880 },
881 {
882 "PEBS": "2",
883 "EventCode": "0xB",
884 "MSRValue": "0x4",
885 "Counter": "3",
886 "UMask": "0x10",
887 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4",
888 "MSRIndex": "0x3F6",
889 "SampleAfterValue": "50000",
890 "BriefDescription": "Memory instructions retired above 4 clocks (Precise Event)"
891 },
892 {
893 "PEBS": "2",
894 "EventCode": "0xB",
895 "MSRValue": "0x1000",
896 "Counter": "3",
897 "UMask": "0x10",
898 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096",
899 "MSRIndex": "0x3F6",
900 "SampleAfterValue": "20",
901 "BriefDescription": "Memory instructions retired above 4096 clocks (Precise Event)"
902 },
903 {
904 "PEBS": "2",
905 "EventCode": "0xB",
906 "MSRValue": "0x200",
907 "Counter": "3",
908 "UMask": "0x10",
909 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512",
910 "MSRIndex": "0x3F6",
911 "SampleAfterValue": "200",
912 "BriefDescription": "Memory instructions retired above 512 clocks (Precise Event)"
913 },
914 {
915 "PEBS": "2",
916 "EventCode": "0xB",
917 "MSRValue": "0x40",
918 "Counter": "3",
919 "UMask": "0x10",
920 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64",
921 "MSRIndex": "0x3F6",
922 "SampleAfterValue": "2000",
923 "BriefDescription": "Memory instructions retired above 64 clocks (Precise Event)"
924 },
925 {
926 "PEBS": "2",
927 "EventCode": "0xB",
928 "MSRValue": "0x8",
929 "Counter": "3",
930 "UMask": "0x10",
931 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8",
932 "MSRIndex": "0x3F6",
933 "SampleAfterValue": "20000",
934 "BriefDescription": "Memory instructions retired above 8 clocks (Precise Event)"
935 },
936 {
937 "PEBS": "2",
938 "EventCode": "0xB",
939 "MSRValue": "0x2000",
940 "Counter": "3",
941 "UMask": "0x10",
942 "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192",
943 "MSRIndex": "0x3F6",
944 "SampleAfterValue": "10",
945 "BriefDescription": "Memory instructions retired above 8192 clocks (Precise Event)"
946 },
947 {
948 "EventCode": "0xB7, 0xBB",
949 "MSRValue": "0x5011",
950 "Counter": "0,1,2,3",
951 "UMask": "0x1",
952 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
953 "MSRIndex": "0x1a6,0x1a7",
954 "SampleAfterValue": "100000",
955 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
956 "Offcore": "1"
957 },
958 {
959 "EventCode": "0xB7, 0xBB",
960 "MSRValue": "0x7f11",
961 "Counter": "0,1,2,3",
962 "UMask": "0x1",
963 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM",
964 "MSRIndex": "0x1a6,0x1a7",
965 "SampleAfterValue": "100000",
966 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM",
967 "Offcore": "1"
968 },
969 {
970 "EventCode": "0xB7, 0xBB",
971 "MSRValue": "0xff11",
972 "Counter": "0,1,2,3",
973 "UMask": "0x1",
974 "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION",
975 "MSRIndex": "0x1a6,0x1a7",
976 "SampleAfterValue": "100000",
977 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = ANY_LOCATION",
978 "Offcore": "1"
979 },
980 {
981 "EventCode": "0xB7, 0xBB",
982 "MSRValue": "0x8011",
983 "Counter": "0,1,2,3",
984 "UMask": "0x1",
985 "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO",
986 "MSRIndex": "0x1a6,0x1a7",
987 "SampleAfterValue": "100000",
988 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = IO_CSR_MMIO",
989 "Offcore": "1"
990 },
991 {
992 "EventCode": "0xB7, 0xBB",
993 "MSRValue": "0x111",
994 "Counter": "0,1,2,3",
995 "UMask": "0x1",
996 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE",
997 "MSRIndex": "0x1a6,0x1a7",
998 "SampleAfterValue": "100000",
999 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1000 "Offcore": "1"
1001 },
1002 {
1003 "EventCode": "0xB7, 0xBB",
1004 "MSRValue": "0x211",
1005 "Counter": "0,1,2,3",
1006 "UMask": "0x1",
1007 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT",
1008 "MSRIndex": "0x1a6,0x1a7",
1009 "SampleAfterValue": "100000",
1010 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1011 "Offcore": "1"
1012 },
1013 {
1014 "EventCode": "0xB7, 0xBB",
1015 "MSRValue": "0x411",
1016 "Counter": "0,1,2,3",
1017 "UMask": "0x1",
1018 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM",
1019 "MSRIndex": "0x1a6,0x1a7",
1020 "SampleAfterValue": "100000",
1021 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1022 "Offcore": "1"
1023 },
1024 {
1025 "EventCode": "0xB7, 0xBB",
1026 "MSRValue": "0x711",
1027 "Counter": "0,1,2,3",
1028 "UMask": "0x1",
1029 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE",
1030 "MSRIndex": "0x1a6,0x1a7",
1031 "SampleAfterValue": "100000",
1032 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_CACHE",
1033 "Offcore": "1"
1034 },
1035 {
1036 "EventCode": "0xB7, 0xBB",
1037 "MSRValue": "0x1011",
1038 "Counter": "0,1,2,3",
1039 "UMask": "0x1",
1040 "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1041 "MSRIndex": "0x1a6,0x1a7",
1042 "SampleAfterValue": "100000",
1043 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1044 "Offcore": "1"
1045 },
1046 {
1047 "EventCode": "0xB7, 0xBB",
1048 "MSRValue": "0x811",
1049 "Counter": "0,1,2,3",
1050 "UMask": "0x1",
1051 "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM",
1052 "MSRIndex": "0x1a6,0x1a7",
1053 "SampleAfterValue": "100000",
1054 "BriefDescription": "REQUEST = ANY_DATA read and RESPONSE = REMOTE_CACHE_HITM",
1055 "Offcore": "1"
1056 },
1057 {
1058 "EventCode": "0xB7, 0xBB",
1059 "MSRValue": "0x5044",
1060 "Counter": "0,1,2,3",
1061 "UMask": "0x1",
1062 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1063 "MSRIndex": "0x1a6,0x1a7",
1064 "SampleAfterValue": "100000",
1065 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1066 "Offcore": "1"
1067 },
1068 {
1069 "EventCode": "0xB7, 0xBB",
1070 "MSRValue": "0x7f44",
1071 "Counter": "0,1,2,3",
1072 "UMask": "0x1",
1073 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM",
1074 "MSRIndex": "0x1a6,0x1a7",
1075 "SampleAfterValue": "100000",
1076 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_CACHE_DRAM",
1077 "Offcore": "1"
1078 },
1079 {
1080 "EventCode": "0xB7, 0xBB",
1081 "MSRValue": "0xff44",
1082 "Counter": "0,1,2,3",
1083 "UMask": "0x1",
1084 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION",
1085 "MSRIndex": "0x1a6,0x1a7",
1086 "SampleAfterValue": "100000",
1087 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = ANY_LOCATION",
1088 "Offcore": "1"
1089 },
1090 {
1091 "EventCode": "0xB7, 0xBB",
1092 "MSRValue": "0x8044",
1093 "Counter": "0,1,2,3",
1094 "UMask": "0x1",
1095 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO",
1096 "MSRIndex": "0x1a6,0x1a7",
1097 "SampleAfterValue": "100000",
1098 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = IO_CSR_MMIO",
1099 "Offcore": "1"
1100 },
1101 {
1102 "EventCode": "0xB7, 0xBB",
1103 "MSRValue": "0x144",
1104 "Counter": "0,1,2,3",
1105 "UMask": "0x1",
1106 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE",
1107 "MSRIndex": "0x1a6,0x1a7",
1108 "SampleAfterValue": "100000",
1109 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1110 "Offcore": "1"
1111 },
1112 {
1113 "EventCode": "0xB7, 0xBB",
1114 "MSRValue": "0x244",
1115 "Counter": "0,1,2,3",
1116 "UMask": "0x1",
1117 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1118 "MSRIndex": "0x1a6,0x1a7",
1119 "SampleAfterValue": "100000",
1120 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1121 "Offcore": "1"
1122 },
1123 {
1124 "EventCode": "0xB7, 0xBB",
1125 "MSRValue": "0x444",
1126 "Counter": "0,1,2,3",
1127 "UMask": "0x1",
1128 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1129 "MSRIndex": "0x1a6,0x1a7",
1130 "SampleAfterValue": "100000",
1131 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1132 "Offcore": "1"
1133 },
1134 {
1135 "EventCode": "0xB7, 0xBB",
1136 "MSRValue": "0x744",
1137 "Counter": "0,1,2,3",
1138 "UMask": "0x1",
1139 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE",
1140 "MSRIndex": "0x1a6,0x1a7",
1141 "SampleAfterValue": "100000",
1142 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_CACHE",
1143 "Offcore": "1"
1144 },
1145 {
1146 "EventCode": "0xB7, 0xBB",
1147 "MSRValue": "0x1044",
1148 "Counter": "0,1,2,3",
1149 "UMask": "0x1",
1150 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1151 "MSRIndex": "0x1a6,0x1a7",
1152 "SampleAfterValue": "100000",
1153 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1154 "Offcore": "1"
1155 },
1156 {
1157 "EventCode": "0xB7, 0xBB",
1158 "MSRValue": "0x844",
1159 "Counter": "0,1,2,3",
1160 "UMask": "0x1",
1161 "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM",
1162 "MSRIndex": "0x1a6,0x1a7",
1163 "SampleAfterValue": "100000",
1164 "BriefDescription": "REQUEST = ANY IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1165 "Offcore": "1"
1166 },
1167 {
1168 "EventCode": "0xB7, 0xBB",
1169 "MSRValue": "0x50ff",
1170 "Counter": "0,1,2,3",
1171 "UMask": "0x1",
1172 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1173 "MSRIndex": "0x1a6,0x1a7",
1174 "SampleAfterValue": "100000",
1175 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1176 "Offcore": "1"
1177 },
1178 {
1179 "EventCode": "0xB7, 0xBB",
1180 "MSRValue": "0x7fff",
1181 "Counter": "0,1,2,3",
1182 "UMask": "0x1",
1183 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM",
1184 "MSRIndex": "0x1a6,0x1a7",
1185 "SampleAfterValue": "100000",
1186 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_CACHE_DRAM",
1187 "Offcore": "1"
1188 },
1189 {
1190 "EventCode": "0xB7, 0xBB",
1191 "MSRValue": "0xffff",
1192 "Counter": "0,1,2,3",
1193 "UMask": "0x1",
1194 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION",
1195 "MSRIndex": "0x1a6,0x1a7",
1196 "SampleAfterValue": "100000",
1197 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = ANY_LOCATION",
1198 "Offcore": "1"
1199 },
1200 {
1201 "EventCode": "0xB7, 0xBB",
1202 "MSRValue": "0x80ff",
1203 "Counter": "0,1,2,3",
1204 "UMask": "0x1",
1205 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO",
1206 "MSRIndex": "0x1a6,0x1a7",
1207 "SampleAfterValue": "100000",
1208 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = IO_CSR_MMIO",
1209 "Offcore": "1"
1210 },
1211 {
1212 "EventCode": "0xB7, 0xBB",
1213 "MSRValue": "0x1ff",
1214 "Counter": "0,1,2,3",
1215 "UMask": "0x1",
1216 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE",
1217 "MSRIndex": "0x1a6,0x1a7",
1218 "SampleAfterValue": "100000",
1219 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1220 "Offcore": "1"
1221 },
1222 {
1223 "EventCode": "0xB7, 0xBB",
1224 "MSRValue": "0x2ff",
1225 "Counter": "0,1,2,3",
1226 "UMask": "0x1",
1227 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT",
1228 "MSRIndex": "0x1a6,0x1a7",
1229 "SampleAfterValue": "100000",
1230 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1231 "Offcore": "1"
1232 },
1233 {
1234 "EventCode": "0xB7, 0xBB",
1235 "MSRValue": "0x4ff",
1236 "Counter": "0,1,2,3",
1237 "UMask": "0x1",
1238 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM",
1239 "MSRIndex": "0x1a6,0x1a7",
1240 "SampleAfterValue": "100000",
1241 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1242 "Offcore": "1"
1243 },
1244 {
1245 "EventCode": "0xB7, 0xBB",
1246 "MSRValue": "0x7ff",
1247 "Counter": "0,1,2,3",
1248 "UMask": "0x1",
1249 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE",
1250 "MSRIndex": "0x1a6,0x1a7",
1251 "SampleAfterValue": "100000",
1252 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_CACHE",
1253 "Offcore": "1"
1254 },
1255 {
1256 "EventCode": "0xB7, 0xBB",
1257 "MSRValue": "0x10ff",
1258 "Counter": "0,1,2,3",
1259 "UMask": "0x1",
1260 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1261 "MSRIndex": "0x1a6,0x1a7",
1262 "SampleAfterValue": "100000",
1263 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1264 "Offcore": "1"
1265 },
1266 {
1267 "EventCode": "0xB7, 0xBB",
1268 "MSRValue": "0x8ff",
1269 "Counter": "0,1,2,3",
1270 "UMask": "0x1",
1271 "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM",
1272 "MSRIndex": "0x1a6,0x1a7",
1273 "SampleAfterValue": "100000",
1274 "BriefDescription": "REQUEST = ANY_REQUEST and RESPONSE = REMOTE_CACHE_HITM",
1275 "Offcore": "1"
1276 },
1277 {
1278 "EventCode": "0xB7, 0xBB",
1279 "MSRValue": "0x5022",
1280 "Counter": "0,1,2,3",
1281 "UMask": "0x1",
1282 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1283 "MSRIndex": "0x1a6,0x1a7",
1284 "SampleAfterValue": "100000",
1285 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1286 "Offcore": "1"
1287 },
1288 {
1289 "EventCode": "0xB7, 0xBB",
1290 "MSRValue": "0x7f22",
1291 "Counter": "0,1,2,3",
1292 "UMask": "0x1",
1293 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM",
1294 "MSRIndex": "0x1a6,0x1a7",
1295 "SampleAfterValue": "100000",
1296 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_CACHE_DRAM",
1297 "Offcore": "1"
1298 },
1299 {
1300 "EventCode": "0xB7, 0xBB",
1301 "MSRValue": "0xff22",
1302 "Counter": "0,1,2,3",
1303 "UMask": "0x1",
1304 "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION",
1305 "MSRIndex": "0x1a6,0x1a7",
1306 "SampleAfterValue": "100000",
1307 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = ANY_LOCATION",
1308 "Offcore": "1"
1309 },
1310 {
1311 "EventCode": "0xB7, 0xBB",
1312 "MSRValue": "0x8022",
1313 "Counter": "0,1,2,3",
1314 "UMask": "0x1",
1315 "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO",
1316 "MSRIndex": "0x1a6,0x1a7",
1317 "SampleAfterValue": "100000",
1318 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = IO_CSR_MMIO",
1319 "Offcore": "1"
1320 },
1321 {
1322 "EventCode": "0xB7, 0xBB",
1323 "MSRValue": "0x122",
1324 "Counter": "0,1,2,3",
1325 "UMask": "0x1",
1326 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE",
1327 "MSRIndex": "0x1a6,0x1a7",
1328 "SampleAfterValue": "100000",
1329 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1330 "Offcore": "1"
1331 },
1332 {
1333 "EventCode": "0xB7, 0xBB",
1334 "MSRValue": "0x222",
1335 "Counter": "0,1,2,3",
1336 "UMask": "0x1",
1337 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT",
1338 "MSRIndex": "0x1a6,0x1a7",
1339 "SampleAfterValue": "100000",
1340 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1341 "Offcore": "1"
1342 },
1343 {
1344 "EventCode": "0xB7, 0xBB",
1345 "MSRValue": "0x422",
1346 "Counter": "0,1,2,3",
1347 "UMask": "0x1",
1348 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM",
1349 "MSRIndex": "0x1a6,0x1a7",
1350 "SampleAfterValue": "100000",
1351 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1352 "Offcore": "1"
1353 },
1354 {
1355 "EventCode": "0xB7, 0xBB",
1356 "MSRValue": "0x722",
1357 "Counter": "0,1,2,3",
1358 "UMask": "0x1",
1359 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE",
1360 "MSRIndex": "0x1a6,0x1a7",
1361 "SampleAfterValue": "100000",
1362 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_CACHE",
1363 "Offcore": "1"
1364 },
1365 {
1366 "EventCode": "0xB7, 0xBB",
1367 "MSRValue": "0x1022",
1368 "Counter": "0,1,2,3",
1369 "UMask": "0x1",
1370 "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1371 "MSRIndex": "0x1a6,0x1a7",
1372 "SampleAfterValue": "100000",
1373 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1374 "Offcore": "1"
1375 },
1376 {
1377 "EventCode": "0xB7, 0xBB",
1378 "MSRValue": "0x822",
1379 "Counter": "0,1,2,3",
1380 "UMask": "0x1",
1381 "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM",
1382 "MSRIndex": "0x1a6,0x1a7",
1383 "SampleAfterValue": "100000",
1384 "BriefDescription": "REQUEST = ANY RFO and RESPONSE = REMOTE_CACHE_HITM",
1385 "Offcore": "1"
1386 },
1387 {
1388 "EventCode": "0xB7, 0xBB",
1389 "MSRValue": "0x5008",
1390 "Counter": "0,1,2,3",
1391 "UMask": "0x1",
1392 "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1393 "MSRIndex": "0x1a6,0x1a7",
1394 "SampleAfterValue": "100000",
1395 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1396 "Offcore": "1"
1397 },
1398 {
1399 "EventCode": "0xB7, 0xBB",
1400 "MSRValue": "0x7f08",
1401 "Counter": "0,1,2,3",
1402 "UMask": "0x1",
1403 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM",
1404 "MSRIndex": "0x1a6,0x1a7",
1405 "SampleAfterValue": "100000",
1406 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_CACHE_DRAM",
1407 "Offcore": "1"
1408 },
1409 {
1410 "EventCode": "0xB7, 0xBB",
1411 "MSRValue": "0xff08",
1412 "Counter": "0,1,2,3",
1413 "UMask": "0x1",
1414 "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION",
1415 "MSRIndex": "0x1a6,0x1a7",
1416 "SampleAfterValue": "100000",
1417 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = ANY_LOCATION",
1418 "Offcore": "1"
1419 },
1420 {
1421 "EventCode": "0xB7, 0xBB",
1422 "MSRValue": "0x8008",
1423 "Counter": "0,1,2,3",
1424 "UMask": "0x1",
1425 "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO",
1426 "MSRIndex": "0x1a6,0x1a7",
1427 "SampleAfterValue": "100000",
1428 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = IO_CSR_MMIO",
1429 "Offcore": "1"
1430 },
1431 {
1432 "EventCode": "0xB7, 0xBB",
1433 "MSRValue": "0x108",
1434 "Counter": "0,1,2,3",
1435 "UMask": "0x1",
1436 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE",
1437 "MSRIndex": "0x1a6,0x1a7",
1438 "SampleAfterValue": "100000",
1439 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1440 "Offcore": "1"
1441 },
1442 {
1443 "EventCode": "0xB7, 0xBB",
1444 "MSRValue": "0x208",
1445 "Counter": "0,1,2,3",
1446 "UMask": "0x1",
1447 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT",
1448 "MSRIndex": "0x1a6,0x1a7",
1449 "SampleAfterValue": "100000",
1450 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1451 "Offcore": "1"
1452 },
1453 {
1454 "EventCode": "0xB7, 0xBB",
1455 "MSRValue": "0x408",
1456 "Counter": "0,1,2,3",
1457 "UMask": "0x1",
1458 "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM",
1459 "MSRIndex": "0x1a6,0x1a7",
1460 "SampleAfterValue": "100000",
1461 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1462 "Offcore": "1"
1463 },
1464 {
1465 "EventCode": "0xB7, 0xBB",
1466 "MSRValue": "0x708",
1467 "Counter": "0,1,2,3",
1468 "UMask": "0x1",
1469 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE",
1470 "MSRIndex": "0x1a6,0x1a7",
1471 "SampleAfterValue": "100000",
1472 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_CACHE",
1473 "Offcore": "1"
1474 },
1475 {
1476 "EventCode": "0xB7, 0xBB",
1477 "MSRValue": "0x1008",
1478 "Counter": "0,1,2,3",
1479 "UMask": "0x1",
1480 "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1481 "MSRIndex": "0x1a6,0x1a7",
1482 "SampleAfterValue": "100000",
1483 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1484 "Offcore": "1"
1485 },
1486 {
1487 "EventCode": "0xB7, 0xBB",
1488 "MSRValue": "0x808",
1489 "Counter": "0,1,2,3",
1490 "UMask": "0x1",
1491 "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM",
1492 "MSRIndex": "0x1a6,0x1a7",
1493 "SampleAfterValue": "100000",
1494 "BriefDescription": "REQUEST = CORE_WB and RESPONSE = REMOTE_CACHE_HITM",
1495 "Offcore": "1"
1496 },
1497 {
1498 "EventCode": "0xB7, 0xBB",
1499 "MSRValue": "0x5077",
1500 "Counter": "0,1,2,3",
1501 "UMask": "0x1",
1502 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1503 "MSRIndex": "0x1a6,0x1a7",
1504 "SampleAfterValue": "100000",
1505 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1506 "Offcore": "1"
1507 },
1508 {
1509 "EventCode": "0xB7, 0xBB",
1510 "MSRValue": "0x7f77",
1511 "Counter": "0,1,2,3",
1512 "UMask": "0x1",
1513 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM",
1514 "MSRIndex": "0x1a6,0x1a7",
1515 "SampleAfterValue": "100000",
1516 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1517 "Offcore": "1"
1518 },
1519 {
1520 "EventCode": "0xB7, 0xBB",
1521 "MSRValue": "0xff77",
1522 "Counter": "0,1,2,3",
1523 "UMask": "0x1",
1524 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION",
1525 "MSRIndex": "0x1a6,0x1a7",
1526 "SampleAfterValue": "100000",
1527 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = ANY_LOCATION",
1528 "Offcore": "1"
1529 },
1530 {
1531 "EventCode": "0xB7, 0xBB",
1532 "MSRValue": "0x8077",
1533 "Counter": "0,1,2,3",
1534 "UMask": "0x1",
1535 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO",
1536 "MSRIndex": "0x1a6,0x1a7",
1537 "SampleAfterValue": "100000",
1538 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = IO_CSR_MMIO",
1539 "Offcore": "1"
1540 },
1541 {
1542 "EventCode": "0xB7, 0xBB",
1543 "MSRValue": "0x177",
1544 "Counter": "0,1,2,3",
1545 "UMask": "0x1",
1546 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE",
1547 "MSRIndex": "0x1a6,0x1a7",
1548 "SampleAfterValue": "100000",
1549 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1550 "Offcore": "1"
1551 },
1552 {
1553 "EventCode": "0xB7, 0xBB",
1554 "MSRValue": "0x277",
1555 "Counter": "0,1,2,3",
1556 "UMask": "0x1",
1557 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1558 "MSRIndex": "0x1a6,0x1a7",
1559 "SampleAfterValue": "100000",
1560 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1561 "Offcore": "1"
1562 },
1563 {
1564 "EventCode": "0xB7, 0xBB",
1565 "MSRValue": "0x477",
1566 "Counter": "0,1,2,3",
1567 "UMask": "0x1",
1568 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM",
1569 "MSRIndex": "0x1a6,0x1a7",
1570 "SampleAfterValue": "100000",
1571 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1572 "Offcore": "1"
1573 },
1574 {
1575 "EventCode": "0xB7, 0xBB",
1576 "MSRValue": "0x777",
1577 "Counter": "0,1,2,3",
1578 "UMask": "0x1",
1579 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE",
1580 "MSRIndex": "0x1a6,0x1a7",
1581 "SampleAfterValue": "100000",
1582 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_CACHE",
1583 "Offcore": "1"
1584 },
1585 {
1586 "EventCode": "0xB7, 0xBB",
1587 "MSRValue": "0x1077",
1588 "Counter": "0,1,2,3",
1589 "UMask": "0x1",
1590 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1591 "MSRIndex": "0x1a6,0x1a7",
1592 "SampleAfterValue": "100000",
1593 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1594 "Offcore": "1"
1595 },
1596 {
1597 "EventCode": "0xB7, 0xBB",
1598 "MSRValue": "0x877",
1599 "Counter": "0,1,2,3",
1600 "UMask": "0x1",
1601 "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM",
1602 "MSRIndex": "0x1a6,0x1a7",
1603 "SampleAfterValue": "100000",
1604 "BriefDescription": "REQUEST = DATA_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
1605 "Offcore": "1"
1606 },
1607 {
1608 "EventCode": "0xB7, 0xBB",
1609 "MSRValue": "0x5033",
1610 "Counter": "0,1,2,3",
1611 "UMask": "0x1",
1612 "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1613 "MSRIndex": "0x1a6,0x1a7",
1614 "SampleAfterValue": "100000",
1615 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1616 "Offcore": "1"
1617 },
1618 {
1619 "EventCode": "0xB7, 0xBB",
1620 "MSRValue": "0x7f33",
1621 "Counter": "0,1,2,3",
1622 "UMask": "0x1",
1623 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM",
1624 "MSRIndex": "0x1a6,0x1a7",
1625 "SampleAfterValue": "100000",
1626 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_CACHE_DRAM",
1627 "Offcore": "1"
1628 },
1629 {
1630 "EventCode": "0xB7, 0xBB",
1631 "MSRValue": "0xff33",
1632 "Counter": "0,1,2,3",
1633 "UMask": "0x1",
1634 "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION",
1635 "MSRIndex": "0x1a6,0x1a7",
1636 "SampleAfterValue": "100000",
1637 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = ANY_LOCATION",
1638 "Offcore": "1"
1639 },
1640 {
1641 "EventCode": "0xB7, 0xBB",
1642 "MSRValue": "0x8033",
1643 "Counter": "0,1,2,3",
1644 "UMask": "0x1",
1645 "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO",
1646 "MSRIndex": "0x1a6,0x1a7",
1647 "SampleAfterValue": "100000",
1648 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = IO_CSR_MMIO",
1649 "Offcore": "1"
1650 },
1651 {
1652 "EventCode": "0xB7, 0xBB",
1653 "MSRValue": "0x133",
1654 "Counter": "0,1,2,3",
1655 "UMask": "0x1",
1656 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE",
1657 "MSRIndex": "0x1a6,0x1a7",
1658 "SampleAfterValue": "100000",
1659 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1660 "Offcore": "1"
1661 },
1662 {
1663 "EventCode": "0xB7, 0xBB",
1664 "MSRValue": "0x233",
1665 "Counter": "0,1,2,3",
1666 "UMask": "0x1",
1667 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT",
1668 "MSRIndex": "0x1a6,0x1a7",
1669 "SampleAfterValue": "100000",
1670 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1671 "Offcore": "1"
1672 },
1673 {
1674 "EventCode": "0xB7, 0xBB",
1675 "MSRValue": "0x433",
1676 "Counter": "0,1,2,3",
1677 "UMask": "0x1",
1678 "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM",
1679 "MSRIndex": "0x1a6,0x1a7",
1680 "SampleAfterValue": "100000",
1681 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1682 "Offcore": "1"
1683 },
1684 {
1685 "EventCode": "0xB7, 0xBB",
1686 "MSRValue": "0x733",
1687 "Counter": "0,1,2,3",
1688 "UMask": "0x1",
1689 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE",
1690 "MSRIndex": "0x1a6,0x1a7",
1691 "SampleAfterValue": "100000",
1692 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_CACHE",
1693 "Offcore": "1"
1694 },
1695 {
1696 "EventCode": "0xB7, 0xBB",
1697 "MSRValue": "0x1033",
1698 "Counter": "0,1,2,3",
1699 "UMask": "0x1",
1700 "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1701 "MSRIndex": "0x1a6,0x1a7",
1702 "SampleAfterValue": "100000",
1703 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1704 "Offcore": "1"
1705 },
1706 {
1707 "EventCode": "0xB7, 0xBB",
1708 "MSRValue": "0x833",
1709 "Counter": "0,1,2,3",
1710 "UMask": "0x1",
1711 "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM",
1712 "MSRIndex": "0x1a6,0x1a7",
1713 "SampleAfterValue": "100000",
1714 "BriefDescription": "REQUEST = DATA_IN and RESPONSE = REMOTE_CACHE_HITM",
1715 "Offcore": "1"
1716 },
1717 {
1718 "EventCode": "0xB7, 0xBB",
1719 "MSRValue": "0x5003",
1720 "Counter": "0,1,2,3",
1721 "UMask": "0x1",
1722 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1723 "MSRIndex": "0x1a6,0x1a7",
1724 "SampleAfterValue": "100000",
1725 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1726 "Offcore": "1"
1727 },
1728 {
1729 "EventCode": "0xB7, 0xBB",
1730 "MSRValue": "0x7f03",
1731 "Counter": "0,1,2,3",
1732 "UMask": "0x1",
1733 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM",
1734 "MSRIndex": "0x1a6,0x1a7",
1735 "SampleAfterValue": "100000",
1736 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_CACHE_DRAM",
1737 "Offcore": "1"
1738 },
1739 {
1740 "EventCode": "0xB7, 0xBB",
1741 "MSRValue": "0xff03",
1742 "Counter": "0,1,2,3",
1743 "UMask": "0x1",
1744 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION",
1745 "MSRIndex": "0x1a6,0x1a7",
1746 "SampleAfterValue": "100000",
1747 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = ANY_LOCATION",
1748 "Offcore": "1"
1749 },
1750 {
1751 "EventCode": "0xB7, 0xBB",
1752 "MSRValue": "0x8003",
1753 "Counter": "0,1,2,3",
1754 "UMask": "0x1",
1755 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO",
1756 "MSRIndex": "0x1a6,0x1a7",
1757 "SampleAfterValue": "100000",
1758 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = IO_CSR_MMIO",
1759 "Offcore": "1"
1760 },
1761 {
1762 "EventCode": "0xB7, 0xBB",
1763 "MSRValue": "0x103",
1764 "Counter": "0,1,2,3",
1765 "UMask": "0x1",
1766 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE",
1767 "MSRIndex": "0x1a6,0x1a7",
1768 "SampleAfterValue": "100000",
1769 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1770 "Offcore": "1"
1771 },
1772 {
1773 "EventCode": "0xB7, 0xBB",
1774 "MSRValue": "0x203",
1775 "Counter": "0,1,2,3",
1776 "UMask": "0x1",
1777 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT",
1778 "MSRIndex": "0x1a6,0x1a7",
1779 "SampleAfterValue": "100000",
1780 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1781 "Offcore": "1"
1782 },
1783 {
1784 "EventCode": "0xB7, 0xBB",
1785 "MSRValue": "0x403",
1786 "Counter": "0,1,2,3",
1787 "UMask": "0x1",
1788 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM",
1789 "MSRIndex": "0x1a6,0x1a7",
1790 "SampleAfterValue": "100000",
1791 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1792 "Offcore": "1"
1793 },
1794 {
1795 "EventCode": "0xB7, 0xBB",
1796 "MSRValue": "0x703",
1797 "Counter": "0,1,2,3",
1798 "UMask": "0x1",
1799 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE",
1800 "MSRIndex": "0x1a6,0x1a7",
1801 "SampleAfterValue": "100000",
1802 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_CACHE",
1803 "Offcore": "1"
1804 },
1805 {
1806 "EventCode": "0xB7, 0xBB",
1807 "MSRValue": "0x1003",
1808 "Counter": "0,1,2,3",
1809 "UMask": "0x1",
1810 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1811 "MSRIndex": "0x1a6,0x1a7",
1812 "SampleAfterValue": "100000",
1813 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1814 "Offcore": "1"
1815 },
1816 {
1817 "EventCode": "0xB7, 0xBB",
1818 "MSRValue": "0x803",
1819 "Counter": "0,1,2,3",
1820 "UMask": "0x1",
1821 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM",
1822 "MSRIndex": "0x1a6,0x1a7",
1823 "SampleAfterValue": "100000",
1824 "BriefDescription": "REQUEST = DEMAND_DATA and RESPONSE = REMOTE_CACHE_HITM",
1825 "Offcore": "1"
1826 },
1827 {
1828 "EventCode": "0xB7, 0xBB",
1829 "MSRValue": "0x5001",
1830 "Counter": "0,1,2,3",
1831 "UMask": "0x1",
1832 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1833 "MSRIndex": "0x1a6,0x1a7",
1834 "SampleAfterValue": "100000",
1835 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1836 "Offcore": "1"
1837 },
1838 {
1839 "EventCode": "0xB7, 0xBB",
1840 "MSRValue": "0x7f01",
1841 "Counter": "0,1,2,3",
1842 "UMask": "0x1",
1843 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM",
1844 "MSRIndex": "0x1a6,0x1a7",
1845 "SampleAfterValue": "100000",
1846 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
1847 "Offcore": "1"
1848 },
1849 {
1850 "EventCode": "0xB7, 0xBB",
1851 "MSRValue": "0xff01",
1852 "Counter": "0,1,2,3",
1853 "UMask": "0x1",
1854 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION",
1855 "MSRIndex": "0x1a6,0x1a7",
1856 "SampleAfterValue": "100000",
1857 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = ANY_LOCATION",
1858 "Offcore": "1"
1859 },
1860 {
1861 "EventCode": "0xB7, 0xBB",
1862 "MSRValue": "0x8001",
1863 "Counter": "0,1,2,3",
1864 "UMask": "0x1",
1865 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO",
1866 "MSRIndex": "0x1a6,0x1a7",
1867 "SampleAfterValue": "100000",
1868 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = IO_CSR_MMIO",
1869 "Offcore": "1"
1870 },
1871 {
1872 "EventCode": "0xB7, 0xBB",
1873 "MSRValue": "0x101",
1874 "Counter": "0,1,2,3",
1875 "UMask": "0x1",
1876 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_CORE",
1877 "MSRIndex": "0x1a6,0x1a7",
1878 "SampleAfterValue": "100000",
1879 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1880 "Offcore": "1"
1881 },
1882 {
1883 "EventCode": "0xB7, 0xBB",
1884 "MSRValue": "0x201",
1885 "Counter": "0,1,2,3",
1886 "UMask": "0x1",
1887 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
1888 "MSRIndex": "0x1a6,0x1a7",
1889 "SampleAfterValue": "100000",
1890 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
1891 "Offcore": "1"
1892 },
1893 {
1894 "EventCode": "0xB7, 0xBB",
1895 "MSRValue": "0x401",
1896 "Counter": "0,1,2,3",
1897 "UMask": "0x1",
1898 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
1899 "MSRIndex": "0x1a6,0x1a7",
1900 "SampleAfterValue": "100000",
1901 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
1902 "Offcore": "1"
1903 },
1904 {
1905 "EventCode": "0xB7, 0xBB",
1906 "MSRValue": "0x701",
1907 "Counter": "0,1,2,3",
1908 "UMask": "0x1",
1909 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE",
1910 "MSRIndex": "0x1a6,0x1a7",
1911 "SampleAfterValue": "100000",
1912 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_CACHE",
1913 "Offcore": "1"
1914 },
1915 {
1916 "EventCode": "0xB7, 0xBB",
1917 "MSRValue": "0x1001",
1918 "Counter": "0,1,2,3",
1919 "UMask": "0x1",
1920 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1921 "MSRIndex": "0x1a6,0x1a7",
1922 "SampleAfterValue": "100000",
1923 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
1924 "Offcore": "1"
1925 },
1926 {
1927 "EventCode": "0xB7, 0xBB",
1928 "MSRValue": "0x801",
1929 "Counter": "0,1,2,3",
1930 "UMask": "0x1",
1931 "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM",
1932 "MSRIndex": "0x1a6,0x1a7",
1933 "SampleAfterValue": "100000",
1934 "BriefDescription": "REQUEST = DEMAND_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
1935 "Offcore": "1"
1936 },
1937 {
1938 "EventCode": "0xB7, 0xBB",
1939 "MSRValue": "0x5004",
1940 "Counter": "0,1,2,3",
1941 "UMask": "0x1",
1942 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
1943 "MSRIndex": "0x1a6,0x1a7",
1944 "SampleAfterValue": "100000",
1945 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
1946 "Offcore": "1"
1947 },
1948 {
1949 "EventCode": "0xB7, 0xBB",
1950 "MSRValue": "0x7f04",
1951 "Counter": "0,1,2,3",
1952 "UMask": "0x1",
1953 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM",
1954 "MSRIndex": "0x1a6,0x1a7",
1955 "SampleAfterValue": "100000",
1956 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_CACHE_DRAM",
1957 "Offcore": "1"
1958 },
1959 {
1960 "EventCode": "0xB7, 0xBB",
1961 "MSRValue": "0xff04",
1962 "Counter": "0,1,2,3",
1963 "UMask": "0x1",
1964 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION",
1965 "MSRIndex": "0x1a6,0x1a7",
1966 "SampleAfterValue": "100000",
1967 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = ANY_LOCATION",
1968 "Offcore": "1"
1969 },
1970 {
1971 "EventCode": "0xB7, 0xBB",
1972 "MSRValue": "0x8004",
1973 "Counter": "0,1,2,3",
1974 "UMask": "0x1",
1975 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO",
1976 "MSRIndex": "0x1a6,0x1a7",
1977 "SampleAfterValue": "100000",
1978 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = IO_CSR_MMIO",
1979 "Offcore": "1"
1980 },
1981 {
1982 "EventCode": "0xB7, 0xBB",
1983 "MSRValue": "0x104",
1984 "Counter": "0,1,2,3",
1985 "UMask": "0x1",
1986 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE",
1987 "MSRIndex": "0x1a6,0x1a7",
1988 "SampleAfterValue": "100000",
1989 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
1990 "Offcore": "1"
1991 },
1992 {
1993 "EventCode": "0xB7, 0xBB",
1994 "MSRValue": "0x204",
1995 "Counter": "0,1,2,3",
1996 "UMask": "0x1",
1997 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HIT",
1998 "MSRIndex": "0x1a6,0x1a7",
1999 "SampleAfterValue": "100000",
2000 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2001 "Offcore": "1"
2002 },
2003 {
2004 "EventCode": "0xB7, 0xBB",
2005 "MSRValue": "0x404",
2006 "Counter": "0,1,2,3",
2007 "UMask": "0x1",
2008 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2009 "MSRIndex": "0x1a6,0x1a7",
2010 "SampleAfterValue": "100000",
2011 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2012 "Offcore": "1"
2013 },
2014 {
2015 "EventCode": "0xB7, 0xBB",
2016 "MSRValue": "0x704",
2017 "Counter": "0,1,2,3",
2018 "UMask": "0x1",
2019 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE",
2020 "MSRIndex": "0x1a6,0x1a7",
2021 "SampleAfterValue": "100000",
2022 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_CACHE",
2023 "Offcore": "1"
2024 },
2025 {
2026 "EventCode": "0xB7, 0xBB",
2027 "MSRValue": "0x1004",
2028 "Counter": "0,1,2,3",
2029 "UMask": "0x1",
2030 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2031 "MSRIndex": "0x1a6,0x1a7",
2032 "SampleAfterValue": "100000",
2033 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2034 "Offcore": "1"
2035 },
2036 {
2037 "EventCode": "0xB7, 0xBB",
2038 "MSRValue": "0x804",
2039 "Counter": "0,1,2,3",
2040 "UMask": "0x1",
2041 "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM",
2042 "MSRIndex": "0x1a6,0x1a7",
2043 "SampleAfterValue": "100000",
2044 "BriefDescription": "REQUEST = DEMAND_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
2045 "Offcore": "1"
2046 },
2047 {
2048 "EventCode": "0xB7, 0xBB",
2049 "MSRValue": "0x5002",
2050 "Counter": "0,1,2,3",
2051 "UMask": "0x1",
2052 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2053 "MSRIndex": "0x1a6,0x1a7",
2054 "SampleAfterValue": "100000",
2055 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2056 "Offcore": "1"
2057 },
2058 {
2059 "EventCode": "0xB7, 0xBB",
2060 "MSRValue": "0x7f02",
2061 "Counter": "0,1,2,3",
2062 "UMask": "0x1",
2063 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM",
2064 "MSRIndex": "0x1a6,0x1a7",
2065 "SampleAfterValue": "100000",
2066 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_CACHE_DRAM",
2067 "Offcore": "1"
2068 },
2069 {
2070 "EventCode": "0xB7, 0xBB",
2071 "MSRValue": "0xff02",
2072 "Counter": "0,1,2,3",
2073 "UMask": "0x1",
2074 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION",
2075 "MSRIndex": "0x1a6,0x1a7",
2076 "SampleAfterValue": "100000",
2077 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = ANY_LOCATION",
2078 "Offcore": "1"
2079 },
2080 {
2081 "EventCode": "0xB7, 0xBB",
2082 "MSRValue": "0x8002",
2083 "Counter": "0,1,2,3",
2084 "UMask": "0x1",
2085 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO",
2086 "MSRIndex": "0x1a6,0x1a7",
2087 "SampleAfterValue": "100000",
2088 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = IO_CSR_MMIO",
2089 "Offcore": "1"
2090 },
2091 {
2092 "EventCode": "0xB7, 0xBB",
2093 "MSRValue": "0x102",
2094 "Counter": "0,1,2,3",
2095 "UMask": "0x1",
2096 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE",
2097 "MSRIndex": "0x1a6,0x1a7",
2098 "SampleAfterValue": "100000",
2099 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2100 "Offcore": "1"
2101 },
2102 {
2103 "EventCode": "0xB7, 0xBB",
2104 "MSRValue": "0x202",
2105 "Counter": "0,1,2,3",
2106 "UMask": "0x1",
2107 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT",
2108 "MSRIndex": "0x1a6,0x1a7",
2109 "SampleAfterValue": "100000",
2110 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2111 "Offcore": "1"
2112 },
2113 {
2114 "EventCode": "0xB7, 0xBB",
2115 "MSRValue": "0x402",
2116 "Counter": "0,1,2,3",
2117 "UMask": "0x1",
2118 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM",
2119 "MSRIndex": "0x1a6,0x1a7",
2120 "SampleAfterValue": "100000",
2121 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2122 "Offcore": "1"
2123 },
2124 {
2125 "EventCode": "0xB7, 0xBB",
2126 "MSRValue": "0x702",
2127 "Counter": "0,1,2,3",
2128 "UMask": "0x1",
2129 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE",
2130 "MSRIndex": "0x1a6,0x1a7",
2131 "SampleAfterValue": "100000",
2132 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_CACHE",
2133 "Offcore": "1"
2134 },
2135 {
2136 "EventCode": "0xB7, 0xBB",
2137 "MSRValue": "0x1002",
2138 "Counter": "0,1,2,3",
2139 "UMask": "0x1",
2140 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2141 "MSRIndex": "0x1a6,0x1a7",
2142 "SampleAfterValue": "100000",
2143 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2144 "Offcore": "1"
2145 },
2146 {
2147 "EventCode": "0xB7, 0xBB",
2148 "MSRValue": "0x802",
2149 "Counter": "0,1,2,3",
2150 "UMask": "0x1",
2151 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM",
2152 "MSRIndex": "0x1a6,0x1a7",
2153 "SampleAfterValue": "100000",
2154 "BriefDescription": "REQUEST = DEMAND_RFO and RESPONSE = REMOTE_CACHE_HITM",
2155 "Offcore": "1"
2156 },
2157 {
2158 "EventCode": "0xB7, 0xBB",
2159 "MSRValue": "0x5080",
2160 "Counter": "0,1,2,3",
2161 "UMask": "0x1",
2162 "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2163 "MSRIndex": "0x1a6,0x1a7",
2164 "SampleAfterValue": "100000",
2165 "BriefDescription": "REQUEST = OTHER and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2166 "Offcore": "1"
2167 },
2168 {
2169 "EventCode": "0xB7, 0xBB",
2170 "MSRValue": "0x7f80",
2171 "Counter": "0,1,2,3",
2172 "UMask": "0x1",
2173 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM",
2174 "MSRIndex": "0x1a6,0x1a7",
2175 "SampleAfterValue": "100000",
2176 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_CACHE_DRAM",
2177 "Offcore": "1"
2178 },
2179 {
2180 "EventCode": "0xB7, 0xBB",
2181 "MSRValue": "0xff80",
2182 "Counter": "0,1,2,3",
2183 "UMask": "0x1",
2184 "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION",
2185 "MSRIndex": "0x1a6,0x1a7",
2186 "SampleAfterValue": "100000",
2187 "BriefDescription": "REQUEST = OTHER and RESPONSE = ANY_LOCATION",
2188 "Offcore": "1"
2189 },
2190 {
2191 "EventCode": "0xB7, 0xBB",
2192 "MSRValue": "0x8080",
2193 "Counter": "0,1,2,3",
2194 "UMask": "0x1",
2195 "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO",
2196 "MSRIndex": "0x1a6,0x1a7",
2197 "SampleAfterValue": "100000",
2198 "BriefDescription": "REQUEST = OTHER and RESPONSE = IO_CSR_MMIO",
2199 "Offcore": "1"
2200 },
2201 {
2202 "EventCode": "0xB7, 0xBB",
2203 "MSRValue": "0x180",
2204 "Counter": "0,1,2,3",
2205 "UMask": "0x1",
2206 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE",
2207 "MSRIndex": "0x1a6,0x1a7",
2208 "SampleAfterValue": "100000",
2209 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2210 "Offcore": "1"
2211 },
2212 {
2213 "EventCode": "0xB7, 0xBB",
2214 "MSRValue": "0x280",
2215 "Counter": "0,1,2,3",
2216 "UMask": "0x1",
2217 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT",
2218 "MSRIndex": "0x1a6,0x1a7",
2219 "SampleAfterValue": "100000",
2220 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2221 "Offcore": "1"
2222 },
2223 {
2224 "EventCode": "0xB7, 0xBB",
2225 "MSRValue": "0x480",
2226 "Counter": "0,1,2,3",
2227 "UMask": "0x1",
2228 "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM",
2229 "MSRIndex": "0x1a6,0x1a7",
2230 "SampleAfterValue": "100000",
2231 "BriefDescription": "REQUEST = OTHER and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2232 "Offcore": "1"
2233 },
2234 {
2235 "EventCode": "0xB7, 0xBB",
2236 "MSRValue": "0x780",
2237 "Counter": "0,1,2,3",
2238 "UMask": "0x1",
2239 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE",
2240 "MSRIndex": "0x1a6,0x1a7",
2241 "SampleAfterValue": "100000",
2242 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_CACHE",
2243 "Offcore": "1"
2244 },
2245 {
2246 "EventCode": "0xB7, 0xBB",
2247 "MSRValue": "0x1080",
2248 "Counter": "0,1,2,3",
2249 "UMask": "0x1",
2250 "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2251 "MSRIndex": "0x1a6,0x1a7",
2252 "SampleAfterValue": "100000",
2253 "BriefDescription": "REQUEST = OTHER and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2254 "Offcore": "1"
2255 },
2256 {
2257 "EventCode": "0xB7, 0xBB",
2258 "MSRValue": "0x880",
2259 "Counter": "0,1,2,3",
2260 "UMask": "0x1",
2261 "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM",
2262 "MSRIndex": "0x1a6,0x1a7",
2263 "SampleAfterValue": "100000",
2264 "BriefDescription": "REQUEST = OTHER and RESPONSE = REMOTE_CACHE_HITM",
2265 "Offcore": "1"
2266 },
2267 {
2268 "EventCode": "0xB7, 0xBB",
2269 "MSRValue": "0x5050",
2270 "Counter": "0,1,2,3",
2271 "UMask": "0x1",
2272 "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2273 "MSRIndex": "0x1a6,0x1a7",
2274 "SampleAfterValue": "100000",
2275 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2276 "Offcore": "1"
2277 },
2278 {
2279 "EventCode": "0xB7, 0xBB",
2280 "MSRValue": "0x7f50",
2281 "Counter": "0,1,2,3",
2282 "UMask": "0x1",
2283 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM",
2284 "MSRIndex": "0x1a6,0x1a7",
2285 "SampleAfterValue": "100000",
2286 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_CACHE_DRAM",
2287 "Offcore": "1"
2288 },
2289 {
2290 "EventCode": "0xB7, 0xBB",
2291 "MSRValue": "0xff50",
2292 "Counter": "0,1,2,3",
2293 "UMask": "0x1",
2294 "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION",
2295 "MSRIndex": "0x1a6,0x1a7",
2296 "SampleAfterValue": "100000",
2297 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = ANY_LOCATION",
2298 "Offcore": "1"
2299 },
2300 {
2301 "EventCode": "0xB7, 0xBB",
2302 "MSRValue": "0x8050",
2303 "Counter": "0,1,2,3",
2304 "UMask": "0x1",
2305 "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO",
2306 "MSRIndex": "0x1a6,0x1a7",
2307 "SampleAfterValue": "100000",
2308 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = IO_CSR_MMIO",
2309 "Offcore": "1"
2310 },
2311 {
2312 "EventCode": "0xB7, 0xBB",
2313 "MSRValue": "0x150",
2314 "Counter": "0,1,2,3",
2315 "UMask": "0x1",
2316 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE",
2317 "MSRIndex": "0x1a6,0x1a7",
2318 "SampleAfterValue": "100000",
2319 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2320 "Offcore": "1"
2321 },
2322 {
2323 "EventCode": "0xB7, 0xBB",
2324 "MSRValue": "0x250",
2325 "Counter": "0,1,2,3",
2326 "UMask": "0x1",
2327 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT",
2328 "MSRIndex": "0x1a6,0x1a7",
2329 "SampleAfterValue": "100000",
2330 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2331 "Offcore": "1"
2332 },
2333 {
2334 "EventCode": "0xB7, 0xBB",
2335 "MSRValue": "0x450",
2336 "Counter": "0,1,2,3",
2337 "UMask": "0x1",
2338 "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM",
2339 "MSRIndex": "0x1a6,0x1a7",
2340 "SampleAfterValue": "100000",
2341 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2342 "Offcore": "1"
2343 },
2344 {
2345 "EventCode": "0xB7, 0xBB",
2346 "MSRValue": "0x750",
2347 "Counter": "0,1,2,3",
2348 "UMask": "0x1",
2349 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE",
2350 "MSRIndex": "0x1a6,0x1a7",
2351 "SampleAfterValue": "100000",
2352 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_CACHE",
2353 "Offcore": "1"
2354 },
2355 {
2356 "EventCode": "0xB7, 0xBB",
2357 "MSRValue": "0x1050",
2358 "Counter": "0,1,2,3",
2359 "UMask": "0x1",
2360 "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2361 "MSRIndex": "0x1a6,0x1a7",
2362 "SampleAfterValue": "100000",
2363 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2364 "Offcore": "1"
2365 },
2366 {
2367 "EventCode": "0xB7, 0xBB",
2368 "MSRValue": "0x850",
2369 "Counter": "0,1,2,3",
2370 "UMask": "0x1",
2371 "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM",
2372 "MSRIndex": "0x1a6,0x1a7",
2373 "SampleAfterValue": "100000",
2374 "BriefDescription": "REQUEST = PF_DATA and RESPONSE = REMOTE_CACHE_HITM",
2375 "Offcore": "1"
2376 },
2377 {
2378 "EventCode": "0xB7, 0xBB",
2379 "MSRValue": "0x5010",
2380 "Counter": "0,1,2,3",
2381 "UMask": "0x1",
2382 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2383 "MSRIndex": "0x1a6,0x1a7",
2384 "SampleAfterValue": "100000",
2385 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2386 "Offcore": "1"
2387 },
2388 {
2389 "EventCode": "0xB7, 0xBB",
2390 "MSRValue": "0x7f10",
2391 "Counter": "0,1,2,3",
2392 "UMask": "0x1",
2393 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM",
2394 "MSRIndex": "0x1a6,0x1a7",
2395 "SampleAfterValue": "100000",
2396 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_CACHE_DRAM",
2397 "Offcore": "1"
2398 },
2399 {
2400 "EventCode": "0xB7, 0xBB",
2401 "MSRValue": "0xff10",
2402 "Counter": "0,1,2,3",
2403 "UMask": "0x1",
2404 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION",
2405 "MSRIndex": "0x1a6,0x1a7",
2406 "SampleAfterValue": "100000",
2407 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = ANY_LOCATION",
2408 "Offcore": "1"
2409 },
2410 {
2411 "EventCode": "0xB7, 0xBB",
2412 "MSRValue": "0x8010",
2413 "Counter": "0,1,2,3",
2414 "UMask": "0x1",
2415 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO",
2416 "MSRIndex": "0x1a6,0x1a7",
2417 "SampleAfterValue": "100000",
2418 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = IO_CSR_MMIO",
2419 "Offcore": "1"
2420 },
2421 {
2422 "EventCode": "0xB7, 0xBB",
2423 "MSRValue": "0x110",
2424 "Counter": "0,1,2,3",
2425 "UMask": "0x1",
2426 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE",
2427 "MSRIndex": "0x1a6,0x1a7",
2428 "SampleAfterValue": "100000",
2429 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2430 "Offcore": "1"
2431 },
2432 {
2433 "EventCode": "0xB7, 0xBB",
2434 "MSRValue": "0x210",
2435 "Counter": "0,1,2,3",
2436 "UMask": "0x1",
2437 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT",
2438 "MSRIndex": "0x1a6,0x1a7",
2439 "SampleAfterValue": "100000",
2440 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2441 "Offcore": "1"
2442 },
2443 {
2444 "EventCode": "0xB7, 0xBB",
2445 "MSRValue": "0x410",
2446 "Counter": "0,1,2,3",
2447 "UMask": "0x1",
2448 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM",
2449 "MSRIndex": "0x1a6,0x1a7",
2450 "SampleAfterValue": "100000",
2451 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2452 "Offcore": "1"
2453 },
2454 {
2455 "EventCode": "0xB7, 0xBB",
2456 "MSRValue": "0x710",
2457 "Counter": "0,1,2,3",
2458 "UMask": "0x1",
2459 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE",
2460 "MSRIndex": "0x1a6,0x1a7",
2461 "SampleAfterValue": "100000",
2462 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_CACHE",
2463 "Offcore": "1"
2464 },
2465 {
2466 "EventCode": "0xB7, 0xBB",
2467 "MSRValue": "0x1010",
2468 "Counter": "0,1,2,3",
2469 "UMask": "0x1",
2470 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2471 "MSRIndex": "0x1a6,0x1a7",
2472 "SampleAfterValue": "100000",
2473 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2474 "Offcore": "1"
2475 },
2476 {
2477 "EventCode": "0xB7, 0xBB",
2478 "MSRValue": "0x810",
2479 "Counter": "0,1,2,3",
2480 "UMask": "0x1",
2481 "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM",
2482 "MSRIndex": "0x1a6,0x1a7",
2483 "SampleAfterValue": "100000",
2484 "BriefDescription": "REQUEST = PF_DATA_RD and RESPONSE = REMOTE_CACHE_HITM",
2485 "Offcore": "1"
2486 },
2487 {
2488 "EventCode": "0xB7, 0xBB",
2489 "MSRValue": "0x5040",
2490 "Counter": "0,1,2,3",
2491 "UMask": "0x1",
2492 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2493 "MSRIndex": "0x1a6,0x1a7",
2494 "SampleAfterValue": "100000",
2495 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2496 "Offcore": "1"
2497 },
2498 {
2499 "EventCode": "0xB7, 0xBB",
2500 "MSRValue": "0x7f40",
2501 "Counter": "0,1,2,3",
2502 "UMask": "0x1",
2503 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM",
2504 "MSRIndex": "0x1a6,0x1a7",
2505 "SampleAfterValue": "100000",
2506 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_CACHE_DRAM",
2507 "Offcore": "1"
2508 },
2509 {
2510 "EventCode": "0xB7, 0xBB",
2511 "MSRValue": "0xff40",
2512 "Counter": "0,1,2,3",
2513 "UMask": "0x1",
2514 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION",
2515 "MSRIndex": "0x1a6,0x1a7",
2516 "SampleAfterValue": "100000",
2517 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = ANY_LOCATION",
2518 "Offcore": "1"
2519 },
2520 {
2521 "EventCode": "0xB7, 0xBB",
2522 "MSRValue": "0x8040",
2523 "Counter": "0,1,2,3",
2524 "UMask": "0x1",
2525 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO",
2526 "MSRIndex": "0x1a6,0x1a7",
2527 "SampleAfterValue": "100000",
2528 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = IO_CSR_MMIO",
2529 "Offcore": "1"
2530 },
2531 {
2532 "EventCode": "0xB7, 0xBB",
2533 "MSRValue": "0x140",
2534 "Counter": "0,1,2,3",
2535 "UMask": "0x1",
2536 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE",
2537 "MSRIndex": "0x1a6,0x1a7",
2538 "SampleAfterValue": "100000",
2539 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2540 "Offcore": "1"
2541 },
2542 {
2543 "EventCode": "0xB7, 0xBB",
2544 "MSRValue": "0x240",
2545 "Counter": "0,1,2,3",
2546 "UMask": "0x1",
2547 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT",
2548 "MSRIndex": "0x1a6,0x1a7",
2549 "SampleAfterValue": "100000",
2550 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2551 "Offcore": "1"
2552 },
2553 {
2554 "EventCode": "0xB7, 0xBB",
2555 "MSRValue": "0x440",
2556 "Counter": "0,1,2,3",
2557 "UMask": "0x1",
2558 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM",
2559 "MSRIndex": "0x1a6,0x1a7",
2560 "SampleAfterValue": "100000",
2561 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2562 "Offcore": "1"
2563 },
2564 {
2565 "EventCode": "0xB7, 0xBB",
2566 "MSRValue": "0x740",
2567 "Counter": "0,1,2,3",
2568 "UMask": "0x1",
2569 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE",
2570 "MSRIndex": "0x1a6,0x1a7",
2571 "SampleAfterValue": "100000",
2572 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_CACHE",
2573 "Offcore": "1"
2574 },
2575 {
2576 "EventCode": "0xB7, 0xBB",
2577 "MSRValue": "0x1040",
2578 "Counter": "0,1,2,3",
2579 "UMask": "0x1",
2580 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2581 "MSRIndex": "0x1a6,0x1a7",
2582 "SampleAfterValue": "100000",
2583 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2584 "Offcore": "1"
2585 },
2586 {
2587 "EventCode": "0xB7, 0xBB",
2588 "MSRValue": "0x840",
2589 "Counter": "0,1,2,3",
2590 "UMask": "0x1",
2591 "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM",
2592 "MSRIndex": "0x1a6,0x1a7",
2593 "SampleAfterValue": "100000",
2594 "BriefDescription": "REQUEST = PF_RFO and RESPONSE = REMOTE_CACHE_HITM",
2595 "Offcore": "1"
2596 },
2597 {
2598 "EventCode": "0xB7, 0xBB",
2599 "MSRValue": "0x5020",
2600 "Counter": "0,1,2,3",
2601 "UMask": "0x1",
2602 "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2603 "MSRIndex": "0x1a6,0x1a7",
2604 "SampleAfterValue": "100000",
2605 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2606 "Offcore": "1"
2607 },
2608 {
2609 "EventCode": "0xB7, 0xBB",
2610 "MSRValue": "0x7f20",
2611 "Counter": "0,1,2,3",
2612 "UMask": "0x1",
2613 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM",
2614 "MSRIndex": "0x1a6,0x1a7",
2615 "SampleAfterValue": "100000",
2616 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_CACHE_DRAM",
2617 "Offcore": "1"
2618 },
2619 {
2620 "EventCode": "0xB7, 0xBB",
2621 "MSRValue": "0xff20",
2622 "Counter": "0,1,2,3",
2623 "UMask": "0x1",
2624 "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION",
2625 "MSRIndex": "0x1a6,0x1a7",
2626 "SampleAfterValue": "100000",
2627 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = ANY_LOCATION",
2628 "Offcore": "1"
2629 },
2630 {
2631 "EventCode": "0xB7, 0xBB",
2632 "MSRValue": "0x8020",
2633 "Counter": "0,1,2,3",
2634 "UMask": "0x1",
2635 "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO",
2636 "MSRIndex": "0x1a6,0x1a7",
2637 "SampleAfterValue": "100000",
2638 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = IO_CSR_MMIO",
2639 "Offcore": "1"
2640 },
2641 {
2642 "EventCode": "0xB7, 0xBB",
2643 "MSRValue": "0x120",
2644 "Counter": "0,1,2,3",
2645 "UMask": "0x1",
2646 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE",
2647 "MSRIndex": "0x1a6,0x1a7",
2648 "SampleAfterValue": "100000",
2649 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2650 "Offcore": "1"
2651 },
2652 {
2653 "EventCode": "0xB7, 0xBB",
2654 "MSRValue": "0x220",
2655 "Counter": "0,1,2,3",
2656 "UMask": "0x1",
2657 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT",
2658 "MSRIndex": "0x1a6,0x1a7",
2659 "SampleAfterValue": "100000",
2660 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2661 "Offcore": "1"
2662 },
2663 {
2664 "EventCode": "0xB7, 0xBB",
2665 "MSRValue": "0x420",
2666 "Counter": "0,1,2,3",
2667 "UMask": "0x1",
2668 "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM",
2669 "MSRIndex": "0x1a6,0x1a7",
2670 "SampleAfterValue": "100000",
2671 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2672 "Offcore": "1"
2673 },
2674 {
2675 "EventCode": "0xB7, 0xBB",
2676 "MSRValue": "0x720",
2677 "Counter": "0,1,2,3",
2678 "UMask": "0x1",
2679 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE",
2680 "MSRIndex": "0x1a6,0x1a7",
2681 "SampleAfterValue": "100000",
2682 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_CACHE",
2683 "Offcore": "1"
2684 },
2685 {
2686 "EventCode": "0xB7, 0xBB",
2687 "MSRValue": "0x1020",
2688 "Counter": "0,1,2,3",
2689 "UMask": "0x1",
2690 "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2691 "MSRIndex": "0x1a6,0x1a7",
2692 "SampleAfterValue": "100000",
2693 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2694 "Offcore": "1"
2695 },
2696 {
2697 "EventCode": "0xB7, 0xBB",
2698 "MSRValue": "0x820",
2699 "Counter": "0,1,2,3",
2700 "UMask": "0x1",
2701 "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM",
2702 "MSRIndex": "0x1a6,0x1a7",
2703 "SampleAfterValue": "100000",
2704 "BriefDescription": "REQUEST = PF_IFETCH and RESPONSE = REMOTE_CACHE_HITM",
2705 "Offcore": "1"
2706 },
2707 {
2708 "EventCode": "0xB7, 0xBB",
2709 "MSRValue": "0x5070",
2710 "Counter": "0,1,2,3",
2711 "UMask": "0x1",
2712 "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2713 "MSRIndex": "0x1a6,0x1a7",
2714 "SampleAfterValue": "100000",
2715 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ALL_LOCAL_DRAM AND REMOTE_CACHE_HIT",
2716 "Offcore": "1"
2717 },
2718 {
2719 "EventCode": "0xB7, 0xBB",
2720 "MSRValue": "0x7f70",
2721 "Counter": "0,1,2,3",
2722 "UMask": "0x1",
2723 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM",
2724 "MSRIndex": "0x1a6,0x1a7",
2725 "SampleAfterValue": "100000",
2726 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_CACHE_DRAM",
2727 "Offcore": "1"
2728 },
2729 {
2730 "EventCode": "0xB7, 0xBB",
2731 "MSRValue": "0xff70",
2732 "Counter": "0,1,2,3",
2733 "UMask": "0x1",
2734 "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION",
2735 "MSRIndex": "0x1a6,0x1a7",
2736 "SampleAfterValue": "100000",
2737 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = ANY_LOCATION",
2738 "Offcore": "1"
2739 },
2740 {
2741 "EventCode": "0xB7, 0xBB",
2742 "MSRValue": "0x8070",
2743 "Counter": "0,1,2,3",
2744 "UMask": "0x1",
2745 "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO",
2746 "MSRIndex": "0x1a6,0x1a7",
2747 "SampleAfterValue": "100000",
2748 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = IO_CSR_MMIO",
2749 "Offcore": "1"
2750 },
2751 {
2752 "EventCode": "0xB7, 0xBB",
2753 "MSRValue": "0x170",
2754 "Counter": "0,1,2,3",
2755 "UMask": "0x1",
2756 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE",
2757 "MSRIndex": "0x1a6,0x1a7",
2758 "SampleAfterValue": "100000",
2759 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_NO_OTHER_CORE",
2760 "Offcore": "1"
2761 },
2762 {
2763 "EventCode": "0xB7, 0xBB",
2764 "MSRValue": "0x270",
2765 "Counter": "0,1,2,3",
2766 "UMask": "0x1",
2767 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT",
2768 "MSRIndex": "0x1a6,0x1a7",
2769 "SampleAfterValue": "100000",
2770 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HIT",
2771 "Offcore": "1"
2772 },
2773 {
2774 "EventCode": "0xB7, 0xBB",
2775 "MSRValue": "0x470",
2776 "Counter": "0,1,2,3",
2777 "UMask": "0x1",
2778 "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM",
2779 "MSRIndex": "0x1a6,0x1a7",
2780 "SampleAfterValue": "100000",
2781 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LLC_HIT_OTHER_CORE_HITM",
2782 "Offcore": "1"
2783 },
2784 {
2785 "EventCode": "0xB7, 0xBB",
2786 "MSRValue": "0x770",
2787 "Counter": "0,1,2,3",
2788 "UMask": "0x1",
2789 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE",
2790 "MSRIndex": "0x1a6,0x1a7",
2791 "SampleAfterValue": "100000",
2792 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_CACHE",
2793 "Offcore": "1"
2794 },
2795 {
2796 "EventCode": "0xB7, 0xBB",
2797 "MSRValue": "0x1070",
2798 "Counter": "0,1,2,3",
2799 "UMask": "0x1",
2800 "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACHE_HIT",
2801 "MSRIndex": "0x1a6,0x1a7",
2802 "SampleAfterValue": "100000",
2803 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = LOCAL_DRAM AND REMOTE_CACHE_HIT",
2804 "Offcore": "1"
2805 },
2806 {
2807 "EventCode": "0xB7, 0xBB",
2808 "MSRValue": "0x870",
2809 "Counter": "0,1,2,3",
2810 "UMask": "0x1",
2811 "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM",
2812 "MSRIndex": "0x1a6,0x1a7",
2813 "SampleAfterValue": "100000",
2814 "BriefDescription": "REQUEST = PREFETCH and RESPONSE = REMOTE_CACHE_HITM",
2815 "Offcore": "1"
2816 }
2817 ]