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ipc/sem: make semctl setting sempid consistent
[cris-mirror.git] / sound / pci / hda / patch_hdmi.c
blob49ee4e55dd16e9a8914258a8d9064a912145ad4e
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10 *
11 * Authors:
12 * Wu Fengguang <wfg@linux.intel.com>
13 *
14 * Maintained by:
15 * Wu Fengguang <wfg@linux.intel.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the Free
19 * Software Foundation; either version 2 of the License, or (at your option)
20 * any later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 * for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software Foundation,
29 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include <sound/hdaudio.h>
41 #include <sound/hda_i915.h>
42 #include <sound/hda_chmap.h>
43 #include "hda_codec.h"
44 #include "hda_local.h"
45 #include "hda_jack.h"
46
47 static bool static_hdmi_pcm;
48 module_param(static_hdmi_pcm, bool, 0644);
49 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
50
51 #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
52 #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
53 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
54 #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
55 #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
56 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
57 || is_skylake(codec) || is_broxton(codec) \
58 || is_kabylake(codec))
59
60 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
61 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
62 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
63
64 struct hdmi_spec_per_cvt {
65 hda_nid_t cvt_nid;
66 int assigned;
67 unsigned int channels_min;
68 unsigned int channels_max;
69 u32 rates;
70 u64 formats;
71 unsigned int maxbps;
72 };
73
74 /* max. connections to a widget */
75 #define HDA_MAX_CONNECTIONS 32
76
77 struct hdmi_spec_per_pin {
78 hda_nid_t pin_nid;
79 /* pin idx, different device entries on the same pin use the same idx */
80 int pin_nid_idx;
81 int num_mux_nids;
82 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
83 int mux_idx;
84 hda_nid_t cvt_nid;
85
86 struct hda_codec *codec;
87 struct hdmi_eld sink_eld;
88 struct mutex lock;
89 struct delayed_work work;
90 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
91 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
92 int repoll_count;
93 bool setup; /* the stream has been set up by prepare callback */
94 int channels; /* current number of channels */
95 bool non_pcm;
96 bool chmap_set; /* channel-map override by ALSA API? */
97 unsigned char chmap[8]; /* ALSA API channel-map */
98 #ifdef CONFIG_SND_PROC_FS
99 struct snd_info_entry *proc_entry;
100 #endif
101 };
102
103 /* operations used by generic code that can be overridden by patches */
104 struct hdmi_ops {
105 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
106 unsigned char *buf, int *eld_size);
107
108 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
109 int ca, int active_channels, int conn_type);
110
111 /* enable/disable HBR (HD passthrough) */
112 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
113
114 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
115 hda_nid_t pin_nid, u32 stream_tag, int format);
116
117 };
118
119 struct hdmi_pcm {
120 struct hda_pcm *pcm;
121 struct snd_jack *jack;
122 struct snd_kcontrol *eld_ctl;
123 };
124
125 struct hdmi_spec {
126 int num_cvts;
127 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
128 hda_nid_t cvt_nids[4]; /* only for haswell fix */
129
130 int num_pins;
131 struct snd_array pins; /* struct hdmi_spec_per_pin */
132 struct hdmi_pcm pcm_rec[16];
133 struct mutex pcm_lock;
134 /* pcm_bitmap means which pcms have been assigned to pins*/
135 unsigned long pcm_bitmap;
136 int pcm_used; /* counter of pcm_rec[] */
137 /* bitmap shows whether the pcm is opened in user space
138 * bit 0 means the first playback PCM (PCM3);
139 * bit 1 means the second playback PCM, and so on.
140 */
141 unsigned long pcm_in_use;
142
143 struct hdmi_eld temp_eld;
144 struct hdmi_ops ops;
145
146 bool dyn_pin_out;
147 bool dyn_pcm_assign;
148 /*
149 * Non-generic VIA/NVIDIA specific
150 */
151 struct hda_multi_out multiout;
152 struct hda_pcm_stream pcm_playback;
153
154 /* i915/powerwell (Haswell+/Valleyview+) specific */
155 struct i915_audio_component_audio_ops i915_audio_ops;
156 bool i915_bound; /* was i915 bound in this driver? */
157
158 struct hdac_chmap chmap;
159 };
160
161 #ifdef CONFIG_SND_HDA_I915
162 #define codec_has_acomp(codec) \
163 ((codec)->bus->core.audio_component != NULL)
164 #else
165 #define codec_has_acomp(codec) false
166 #endif
167
168 struct hdmi_audio_infoframe {
169 u8 type; /* 0x84 */
170 u8 ver; /* 0x01 */
171 u8 len; /* 0x0a */
172
173 u8 checksum;
174
175 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
176 u8 SS01_SF24;
177 u8 CXT04;
178 u8 CA;
179 u8 LFEPBL01_LSV36_DM_INH7;
180 };
181
182 struct dp_audio_infoframe {
183 u8 type; /* 0x84 */
184 u8 len; /* 0x1b */
185 u8 ver; /* 0x11 << 2 */
186
187 u8 CC02_CT47; /* match with HDMI infoframe from this on */
188 u8 SS01_SF24;
189 u8 CXT04;
190 u8 CA;
191 u8 LFEPBL01_LSV36_DM_INH7;
192 };
193
194 union audio_infoframe {
195 struct hdmi_audio_infoframe hdmi;
196 struct dp_audio_infoframe dp;
197 u8 bytes[0];
198 };
199
200 /*
201 * HDMI routines
202 */
203
204 #define get_pin(spec, idx) \
205 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
206 #define get_cvt(spec, idx) \
207 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
208 /* obtain hdmi_pcm object assigned to idx */
209 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
210 /* obtain hda_pcm object assigned to idx */
211 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
212
213 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
214 {
215 struct hdmi_spec *spec = codec->spec;
216 int pin_idx;
217
218 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
219 if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
220 return pin_idx;
221
222 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
223 return -EINVAL;
224 }
225
226 static int hinfo_to_pcm_index(struct hda_codec *codec,
227 struct hda_pcm_stream *hinfo)
228 {
229 struct hdmi_spec *spec = codec->spec;
230 int pcm_idx;
231
232 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
233 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
234 return pcm_idx;
235
236 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
237 return -EINVAL;
238 }
239
240 static int hinfo_to_pin_index(struct hda_codec *codec,
241 struct hda_pcm_stream *hinfo)
242 {
243 struct hdmi_spec *spec = codec->spec;
244 struct hdmi_spec_per_pin *per_pin;
245 int pin_idx;
246
247 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
248 per_pin = get_pin(spec, pin_idx);
249 if (per_pin->pcm &&
250 per_pin->pcm->pcm->stream == hinfo)
251 return pin_idx;
252 }
253
254 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
255 return -EINVAL;
256 }
257
258 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
259 int pcm_idx)
260 {
261 int i;
262 struct hdmi_spec_per_pin *per_pin;
263
264 for (i = 0; i < spec->num_pins; i++) {
265 per_pin = get_pin(spec, i);
266 if (per_pin->pcm_idx == pcm_idx)
267 return per_pin;
268 }
269 return NULL;
270 }
271
272 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
273 {
274 struct hdmi_spec *spec = codec->spec;
275 int cvt_idx;
276
277 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
278 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
279 return cvt_idx;
280
281 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
282 return -EINVAL;
283 }
284
285 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
286 struct snd_ctl_elem_info *uinfo)
287 {
288 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
289 struct hdmi_spec *spec = codec->spec;
290 struct hdmi_spec_per_pin *per_pin;
291 struct hdmi_eld *eld;
292 int pcm_idx;
293
294 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
295
296 pcm_idx = kcontrol->private_value;
297 mutex_lock(&spec->pcm_lock);
298 per_pin = pcm_idx_to_pin(spec, pcm_idx);
299 if (!per_pin) {
300 /* no pin is bound to the pcm */
301 uinfo->count = 0;
302 mutex_unlock(&spec->pcm_lock);
303 return 0;
304 }
305 eld = &per_pin->sink_eld;
306 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
307 mutex_unlock(&spec->pcm_lock);
308
309 return 0;
310 }
311
312 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
313 struct snd_ctl_elem_value *ucontrol)
314 {
315 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
316 struct hdmi_spec *spec = codec->spec;
317 struct hdmi_spec_per_pin *per_pin;
318 struct hdmi_eld *eld;
319 int pcm_idx;
320
321 pcm_idx = kcontrol->private_value;
322 mutex_lock(&spec->pcm_lock);
323 per_pin = pcm_idx_to_pin(spec, pcm_idx);
324 if (!per_pin) {
325 /* no pin is bound to the pcm */
326 memset(ucontrol->value.bytes.data, 0,
327 ARRAY_SIZE(ucontrol->value.bytes.data));
328 mutex_unlock(&spec->pcm_lock);
329 return 0;
330 }
331 eld = &per_pin->sink_eld;
332
333 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
334 eld->eld_size > ELD_MAX_SIZE) {
335 mutex_unlock(&spec->pcm_lock);
336 snd_BUG();
337 return -EINVAL;
338 }
339
340 memset(ucontrol->value.bytes.data, 0,
341 ARRAY_SIZE(ucontrol->value.bytes.data));
342 if (eld->eld_valid)
343 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
344 eld->eld_size);
345 mutex_unlock(&spec->pcm_lock);
346
347 return 0;
348 }
349
350 static struct snd_kcontrol_new eld_bytes_ctl = {
351 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
352 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
353 .name = "ELD",
354 .info = hdmi_eld_ctl_info,
355 .get = hdmi_eld_ctl_get,
356 };
357
358 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
359 int device)
360 {
361 struct snd_kcontrol *kctl;
362 struct hdmi_spec *spec = codec->spec;
363 int err;
364
365 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
366 if (!kctl)
367 return -ENOMEM;
368 kctl->private_value = pcm_idx;
369 kctl->id.device = device;
370
371 /* no pin nid is associated with the kctl now
372 * tbd: associate pin nid to eld ctl later
373 */
374 err = snd_hda_ctl_add(codec, 0, kctl);
375 if (err < 0)
376 return err;
377
378 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
379 return 0;
380 }
381
382 #ifdef BE_PARANOID
383 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
384 int *packet_index, int *byte_index)
385 {
386 int val;
387
388 val = snd_hda_codec_read(codec, pin_nid, 0,
389 AC_VERB_GET_HDMI_DIP_INDEX, 0);
390
391 *packet_index = val >> 5;
392 *byte_index = val & 0x1f;
393 }
394 #endif
395
396 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
397 int packet_index, int byte_index)
398 {
399 int val;
400
401 val = (packet_index << 5) | (byte_index & 0x1f);
402
403 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
404 }
405
406 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
407 unsigned char val)
408 {
409 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
410 }
411
412 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
413 {
414 struct hdmi_spec *spec = codec->spec;
415 int pin_out;
416
417 /* Unmute */
418 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
419 snd_hda_codec_write(codec, pin_nid, 0,
420 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
421
422 if (spec->dyn_pin_out)
423 /* Disable pin out until stream is active */
424 pin_out = 0;
425 else
426 /* Enable pin out: some machines with GM965 gets broken output
427 * when the pin is disabled or changed while using with HDMI
428 */
429 pin_out = PIN_OUT;
430
431 snd_hda_codec_write(codec, pin_nid, 0,
432 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
433 }
434
435 /*
436 * ELD proc files
437 */
438
439 #ifdef CONFIG_SND_PROC_FS
440 static void print_eld_info(struct snd_info_entry *entry,
441 struct snd_info_buffer *buffer)
442 {
443 struct hdmi_spec_per_pin *per_pin = entry->private_data;
444
445 mutex_lock(&per_pin->lock);
446 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
447 mutex_unlock(&per_pin->lock);
448 }
449
450 static void write_eld_info(struct snd_info_entry *entry,
451 struct snd_info_buffer *buffer)
452 {
453 struct hdmi_spec_per_pin *per_pin = entry->private_data;
454
455 mutex_lock(&per_pin->lock);
456 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
457 mutex_unlock(&per_pin->lock);
458 }
459
460 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
461 {
462 char name[32];
463 struct hda_codec *codec = per_pin->codec;
464 struct snd_info_entry *entry;
465 int err;
466
467 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
468 err = snd_card_proc_new(codec->card, name, &entry);
469 if (err < 0)
470 return err;
471
472 snd_info_set_text_ops(entry, per_pin, print_eld_info);
473 entry->c.text.write = write_eld_info;
474 entry->mode |= S_IWUSR;
475 per_pin->proc_entry = entry;
476
477 return 0;
478 }
479
480 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
481 {
482 if (!per_pin->codec->bus->shutdown) {
483 snd_info_free_entry(per_pin->proc_entry);
484 per_pin->proc_entry = NULL;
485 }
486 }
487 #else
488 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
489 int index)
490 {
491 return 0;
492 }
493 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
494 {
495 }
496 #endif
497
498 /*
499 * Audio InfoFrame routines
500 */
501
502 /*
503 * Enable Audio InfoFrame Transmission
504 */
505 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
506 hda_nid_t pin_nid)
507 {
508 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
509 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
510 AC_DIPXMIT_BEST);
511 }
512
513 /*
514 * Disable Audio InfoFrame Transmission
515 */
516 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
517 hda_nid_t pin_nid)
518 {
519 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
520 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
521 AC_DIPXMIT_DISABLE);
522 }
523
524 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
525 {
526 #ifdef CONFIG_SND_DEBUG_VERBOSE
527 int i;
528 int size;
529
530 size = snd_hdmi_get_eld_size(codec, pin_nid);
531 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
532
533 for (i = 0; i < 8; i++) {
534 size = snd_hda_codec_read(codec, pin_nid, 0,
535 AC_VERB_GET_HDMI_DIP_SIZE, i);
536 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
537 }
538 #endif
539 }
540
541 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
542 {
543 #ifdef BE_PARANOID
544 int i, j;
545 int size;
546 int pi, bi;
547 for (i = 0; i < 8; i++) {
548 size = snd_hda_codec_read(codec, pin_nid, 0,
549 AC_VERB_GET_HDMI_DIP_SIZE, i);
550 if (size == 0)
551 continue;
552
553 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
554 for (j = 1; j < 1000; j++) {
555 hdmi_write_dip_byte(codec, pin_nid, 0x0);
556 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
557 if (pi != i)
558 codec_dbg(codec, "dip index %d: %d != %d\n",
559 bi, pi, i);
560 if (bi == 0) /* byte index wrapped around */
561 break;
562 }
563 codec_dbg(codec,
564 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
565 i, size, j);
566 }
567 #endif
568 }
569
570 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
571 {
572 u8 *bytes = (u8 *)hdmi_ai;
573 u8 sum = 0;
574 int i;
575
576 hdmi_ai->checksum = 0;
577
578 for (i = 0; i < sizeof(*hdmi_ai); i++)
579 sum += bytes[i];
580
581 hdmi_ai->checksum = -sum;
582 }
583
584 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
585 hda_nid_t pin_nid,
586 u8 *dip, int size)
587 {
588 int i;
589
590 hdmi_debug_dip_size(codec, pin_nid);
591 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
592
593 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
594 for (i = 0; i < size; i++)
595 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
596 }
597
598 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
599 u8 *dip, int size)
600 {
601 u8 val;
602 int i;
603
604 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
605 != AC_DIPXMIT_BEST)
606 return false;
607
608 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
609 for (i = 0; i < size; i++) {
610 val = snd_hda_codec_read(codec, pin_nid, 0,
611 AC_VERB_GET_HDMI_DIP_DATA, 0);
612 if (val != dip[i])
613 return false;
614 }
615
616 return true;
617 }
618
619 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
620 hda_nid_t pin_nid,
621 int ca, int active_channels,
622 int conn_type)
623 {
624 union audio_infoframe ai;
625
626 memset(&ai, 0, sizeof(ai));
627 if (conn_type == 0) { /* HDMI */
628 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
629
630 hdmi_ai->type = 0x84;
631 hdmi_ai->ver = 0x01;
632 hdmi_ai->len = 0x0a;
633 hdmi_ai->CC02_CT47 = active_channels - 1;
634 hdmi_ai->CA = ca;
635 hdmi_checksum_audio_infoframe(hdmi_ai);
636 } else if (conn_type == 1) { /* DisplayPort */
637 struct dp_audio_infoframe *dp_ai = &ai.dp;
638
639 dp_ai->type = 0x84;
640 dp_ai->len = 0x1b;
641 dp_ai->ver = 0x11 << 2;
642 dp_ai->CC02_CT47 = active_channels - 1;
643 dp_ai->CA = ca;
644 } else {
645 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
646 pin_nid);
647 return;
648 }
649
650 /*
651 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
652 * sizeof(*dp_ai) to avoid partial match/update problems when
653 * the user switches between HDMI/DP monitors.
654 */
655 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
656 sizeof(ai))) {
657 codec_dbg(codec,
658 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
659 pin_nid,
660 active_channels, ca);
661 hdmi_stop_infoframe_trans(codec, pin_nid);
662 hdmi_fill_audio_infoframe(codec, pin_nid,
663 ai.bytes, sizeof(ai));
664 hdmi_start_infoframe_trans(codec, pin_nid);
665 }
666 }
667
668 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
669 struct hdmi_spec_per_pin *per_pin,
670 bool non_pcm)
671 {
672 struct hdmi_spec *spec = codec->spec;
673 struct hdac_chmap *chmap = &spec->chmap;
674 hda_nid_t pin_nid = per_pin->pin_nid;
675 int channels = per_pin->channels;
676 int active_channels;
677 struct hdmi_eld *eld;
678 int ca;
679
680 if (!channels)
681 return;
682
683 if (is_haswell_plus(codec))
684 snd_hda_codec_write(codec, pin_nid, 0,
685 AC_VERB_SET_AMP_GAIN_MUTE,
686 AMP_OUT_UNMUTE);
687
688 eld = &per_pin->sink_eld;
689
690 ca = snd_hdac_channel_allocation(&codec->core,
691 eld->info.spk_alloc, channels,
692 per_pin->chmap_set, non_pcm, per_pin->chmap);
693
694 active_channels = snd_hdac_get_active_channels(ca);
695
696 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
697 active_channels);
698
699 /*
700 * always configure channel mapping, it may have been changed by the
701 * user in the meantime
702 */
703 snd_hdac_setup_channel_mapping(&spec->chmap,
704 pin_nid, non_pcm, ca, channels,
705 per_pin->chmap, per_pin->chmap_set);
706
707 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
708 eld->info.conn_type);
709
710 per_pin->non_pcm = non_pcm;
711 }
712
713 /*
714 * Unsolicited events
715 */
716
717 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
718
719 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
720 {
721 struct hdmi_spec *spec = codec->spec;
722 int pin_idx = pin_nid_to_pin_index(codec, nid);
723
724 if (pin_idx < 0)
725 return;
726 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
727 snd_hda_jack_report_sync(codec);
728 }
729
730 static void jack_callback(struct hda_codec *codec,
731 struct hda_jack_callback *jack)
732 {
733 check_presence_and_report(codec, jack->nid);
734 }
735
736 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
737 {
738 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
739 struct hda_jack_tbl *jack;
740 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
741
742 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
743 if (!jack)
744 return;
745 jack->jack_dirty = 1;
746
747 codec_dbg(codec,
748 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
749 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
750 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
751
752 check_presence_and_report(codec, jack->nid);
753 }
754
755 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
756 {
757 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
758 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
759 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
760 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
761
762 codec_info(codec,
763 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
764 codec->addr,
765 tag,
766 subtag,
767 cp_state,
768 cp_ready);
769
770 /* TODO */
771 if (cp_state)
772 ;
773 if (cp_ready)
774 ;
775 }
776
777
778 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
779 {
780 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
781 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
782
783 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
784 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
785 return;
786 }
787
788 if (subtag == 0)
789 hdmi_intrinsic_event(codec, res);
790 else
791 hdmi_non_intrinsic_event(codec, res);
792 }
793
794 static void haswell_verify_D0(struct hda_codec *codec,
795 hda_nid_t cvt_nid, hda_nid_t nid)
796 {
797 int pwr;
798
799 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
800 * thus pins could only choose converter 0 for use. Make sure the
801 * converters are in correct power state */
802 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
803 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
804
805 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
806 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
807 AC_PWRST_D0);
808 msleep(40);
809 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
810 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
811 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
812 }
813 }
814
815 /*
816 * Callbacks
817 */
818
819 /* HBR should be Non-PCM, 8 channels */
820 #define is_hbr_format(format) \
821 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
822
823 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
824 bool hbr)
825 {
826 int pinctl, new_pinctl;
827
828 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
829 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
830 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
831
832 if (pinctl < 0)
833 return hbr ? -EINVAL : 0;
834
835 new_pinctl = pinctl & ~AC_PINCTL_EPT;
836 if (hbr)
837 new_pinctl |= AC_PINCTL_EPT_HBR;
838 else
839 new_pinctl |= AC_PINCTL_EPT_NATIVE;
840
841 codec_dbg(codec,
842 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
843 pin_nid,
844 pinctl == new_pinctl ? "" : "new-",
845 new_pinctl);
846
847 if (pinctl != new_pinctl)
848 snd_hda_codec_write(codec, pin_nid, 0,
849 AC_VERB_SET_PIN_WIDGET_CONTROL,
850 new_pinctl);
851 } else if (hbr)
852 return -EINVAL;
853
854 return 0;
855 }
856
857 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
858 hda_nid_t pin_nid, u32 stream_tag, int format)
859 {
860 struct hdmi_spec *spec = codec->spec;
861 int err;
862
863 if (is_haswell_plus(codec))
864 haswell_verify_D0(codec, cvt_nid, pin_nid);
865
866 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
867
868 if (err) {
869 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
870 return err;
871 }
872
873 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
874 return 0;
875 }
876
877 /* Try to find an available converter
878 * If pin_idx is less then zero, just try to find an available converter.
879 * Otherwise, try to find an available converter and get the cvt mux index
880 * of the pin.
881 */
882 static int hdmi_choose_cvt(struct hda_codec *codec,
883 int pin_idx, int *cvt_id, int *mux_id)
884 {
885 struct hdmi_spec *spec = codec->spec;
886 struct hdmi_spec_per_pin *per_pin;
887 struct hdmi_spec_per_cvt *per_cvt = NULL;
888 int cvt_idx, mux_idx = 0;
889
890 /* pin_idx < 0 means no pin will be bound to the converter */
891 if (pin_idx < 0)
892 per_pin = NULL;
893 else
894 per_pin = get_pin(spec, pin_idx);
895
896 /* Dynamically assign converter to stream */
897 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
898 per_cvt = get_cvt(spec, cvt_idx);
899
900 /* Must not already be assigned */
901 if (per_cvt->assigned)
902 continue;
903 if (per_pin == NULL)
904 break;
905 /* Must be in pin's mux's list of converters */
906 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
907 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
908 break;
909 /* Not in mux list */
910 if (mux_idx == per_pin->num_mux_nids)
911 continue;
912 break;
913 }
914
915 /* No free converters */
916 if (cvt_idx == spec->num_cvts)
917 return -EBUSY;
918
919 if (per_pin != NULL)
920 per_pin->mux_idx = mux_idx;
921
922 if (cvt_id)
923 *cvt_id = cvt_idx;
924 if (mux_id)
925 *mux_id = mux_idx;
926
927 return 0;
928 }
929
930 /* Assure the pin select the right convetor */
931 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
932 struct hdmi_spec_per_pin *per_pin)
933 {
934 hda_nid_t pin_nid = per_pin->pin_nid;
935 int mux_idx, curr;
936
937 mux_idx = per_pin->mux_idx;
938 curr = snd_hda_codec_read(codec, pin_nid, 0,
939 AC_VERB_GET_CONNECT_SEL, 0);
940 if (curr != mux_idx)
941 snd_hda_codec_write_cache(codec, pin_nid, 0,
942 AC_VERB_SET_CONNECT_SEL,
943 mux_idx);
944 }
945
946 /* get the mux index for the converter of the pins
947 * converter's mux index is the same for all pins on Intel platform
948 */
949 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
950 hda_nid_t cvt_nid)
951 {
952 int i;
953
954 for (i = 0; i < spec->num_cvts; i++)
955 if (spec->cvt_nids[i] == cvt_nid)
956 return i;
957 return -EINVAL;
958 }
959
960 /* Intel HDMI workaround to fix audio routing issue:
961 * For some Intel display codecs, pins share the same connection list.
962 * So a conveter can be selected by multiple pins and playback on any of these
963 * pins will generate sound on the external display, because audio flows from
964 * the same converter to the display pipeline. Also muting one pin may make
965 * other pins have no sound output.
966 * So this function assures that an assigned converter for a pin is not selected
967 * by any other pins.
968 */
969 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
970 hda_nid_t pin_nid, int mux_idx)
971 {
972 struct hdmi_spec *spec = codec->spec;
973 hda_nid_t nid;
974 int cvt_idx, curr;
975 struct hdmi_spec_per_cvt *per_cvt;
976
977 /* configure all pins, including "no physical connection" ones */
978 for_each_hda_codec_node(nid, codec) {
979 unsigned int wid_caps = get_wcaps(codec, nid);
980 unsigned int wid_type = get_wcaps_type(wid_caps);
981
982 if (wid_type != AC_WID_PIN)
983 continue;
984
985 if (nid == pin_nid)
986 continue;
987
988 curr = snd_hda_codec_read(codec, nid, 0,
989 AC_VERB_GET_CONNECT_SEL, 0);
990 if (curr != mux_idx)
991 continue;
992
993 /* choose an unassigned converter. The conveters in the
994 * connection list are in the same order as in the codec.
995 */
996 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
997 per_cvt = get_cvt(spec, cvt_idx);
998 if (!per_cvt->assigned) {
999 codec_dbg(codec,
1000 "choose cvt %d for pin nid %d\n",
1001 cvt_idx, nid);
1002 snd_hda_codec_write_cache(codec, nid, 0,
1003 AC_VERB_SET_CONNECT_SEL,
1004 cvt_idx);
1005 break;
1006 }
1007 }
1008 }
1009 }
1010
1011 /* A wrapper of intel_not_share_asigned_cvt() */
1012 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1013 hda_nid_t pin_nid, hda_nid_t cvt_nid)
1014 {
1015 int mux_idx;
1016 struct hdmi_spec *spec = codec->spec;
1017
1018 if (!is_haswell_plus(codec) && !is_valleyview_plus(codec))
1019 return;
1020
1021 /* On Intel platform, the mapping of converter nid to
1022 * mux index of the pins are always the same.
1023 * The pin nid may be 0, this means all pins will not
1024 * share the converter.
1025 */
1026 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1027 if (mux_idx >= 0)
1028 intel_not_share_assigned_cvt(codec, pin_nid, mux_idx);
1029 }
1030
1031 /* called in hdmi_pcm_open when no pin is assigned to the PCM
1032 * in dyn_pcm_assign mode.
1033 */
1034 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1035 struct hda_codec *codec,
1036 struct snd_pcm_substream *substream)
1037 {
1038 struct hdmi_spec *spec = codec->spec;
1039 struct snd_pcm_runtime *runtime = substream->runtime;
1040 int cvt_idx, pcm_idx;
1041 struct hdmi_spec_per_cvt *per_cvt = NULL;
1042 int err;
1043
1044 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1045 if (pcm_idx < 0)
1046 return -EINVAL;
1047
1048 err = hdmi_choose_cvt(codec, -1, &cvt_idx, NULL);
1049 if (err)
1050 return err;
1051
1052 per_cvt = get_cvt(spec, cvt_idx);
1053 per_cvt->assigned = 1;
1054 hinfo->nid = per_cvt->cvt_nid;
1055
1056 intel_not_share_assigned_cvt_nid(codec, 0, per_cvt->cvt_nid);
1057
1058 set_bit(pcm_idx, &spec->pcm_in_use);
1059 /* todo: setup spdif ctls assign */
1060
1061 /* Initially set the converter's capabilities */
1062 hinfo->channels_min = per_cvt->channels_min;
1063 hinfo->channels_max = per_cvt->channels_max;
1064 hinfo->rates = per_cvt->rates;
1065 hinfo->formats = per_cvt->formats;
1066 hinfo->maxbps = per_cvt->maxbps;
1067
1068 /* Store the updated parameters */
1069 runtime->hw.channels_min = hinfo->channels_min;
1070 runtime->hw.channels_max = hinfo->channels_max;
1071 runtime->hw.formats = hinfo->formats;
1072 runtime->hw.rates = hinfo->rates;
1073
1074 snd_pcm_hw_constraint_step(substream->runtime, 0,
1075 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1076 return 0;
1077 }
1078
1079 /*
1080 * HDA PCM callbacks
1081 */
1082 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1083 struct hda_codec *codec,
1084 struct snd_pcm_substream *substream)
1085 {
1086 struct hdmi_spec *spec = codec->spec;
1087 struct snd_pcm_runtime *runtime = substream->runtime;
1088 int pin_idx, cvt_idx, pcm_idx, mux_idx = 0;
1089 struct hdmi_spec_per_pin *per_pin;
1090 struct hdmi_eld *eld;
1091 struct hdmi_spec_per_cvt *per_cvt = NULL;
1092 int err;
1093
1094 /* Validate hinfo */
1095 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1096 if (pcm_idx < 0)
1097 return -EINVAL;
1098
1099 mutex_lock(&spec->pcm_lock);
1100 pin_idx = hinfo_to_pin_index(codec, hinfo);
1101 if (!spec->dyn_pcm_assign) {
1102 if (snd_BUG_ON(pin_idx < 0)) {
1103 mutex_unlock(&spec->pcm_lock);
1104 return -EINVAL;
1105 }
1106 } else {
1107 /* no pin is assigned to the PCM
1108 * PA need pcm open successfully when probe
1109 */
1110 if (pin_idx < 0) {
1111 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1112 mutex_unlock(&spec->pcm_lock);
1113 return err;
1114 }
1115 }
1116
1117 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1118 if (err < 0) {
1119 mutex_unlock(&spec->pcm_lock);
1120 return err;
1121 }
1122
1123 per_cvt = get_cvt(spec, cvt_idx);
1124 /* Claim converter */
1125 per_cvt->assigned = 1;
1126
1127 set_bit(pcm_idx, &spec->pcm_in_use);
1128 per_pin = get_pin(spec, pin_idx);
1129 per_pin->cvt_nid = per_cvt->cvt_nid;
1130 hinfo->nid = per_cvt->cvt_nid;
1131
1132 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1133 AC_VERB_SET_CONNECT_SEL,
1134 mux_idx);
1135
1136 /* configure unused pins to choose other converters */
1137 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1138 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1139
1140 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1141
1142 /* Initially set the converter's capabilities */
1143 hinfo->channels_min = per_cvt->channels_min;
1144 hinfo->channels_max = per_cvt->channels_max;
1145 hinfo->rates = per_cvt->rates;
1146 hinfo->formats = per_cvt->formats;
1147 hinfo->maxbps = per_cvt->maxbps;
1148
1149 eld = &per_pin->sink_eld;
1150 /* Restrict capabilities by ELD if this isn't disabled */
1151 if (!static_hdmi_pcm && eld->eld_valid) {
1152 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1153 if (hinfo->channels_min > hinfo->channels_max ||
1154 !hinfo->rates || !hinfo->formats) {
1155 per_cvt->assigned = 0;
1156 hinfo->nid = 0;
1157 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1158 mutex_unlock(&spec->pcm_lock);
1159 return -ENODEV;
1160 }
1161 }
1162
1163 mutex_unlock(&spec->pcm_lock);
1164 /* Store the updated parameters */
1165 runtime->hw.channels_min = hinfo->channels_min;
1166 runtime->hw.channels_max = hinfo->channels_max;
1167 runtime->hw.formats = hinfo->formats;
1168 runtime->hw.rates = hinfo->rates;
1169
1170 snd_pcm_hw_constraint_step(substream->runtime, 0,
1171 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1172 return 0;
1173 }
1174
1175 /*
1176 * HDA/HDMI auto parsing
1177 */
1178 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1179 {
1180 struct hdmi_spec *spec = codec->spec;
1181 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1182 hda_nid_t pin_nid = per_pin->pin_nid;
1183
1184 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1185 codec_warn(codec,
1186 "HDMI: pin %d wcaps %#x does not support connection list\n",
1187 pin_nid, get_wcaps(codec, pin_nid));
1188 return -EINVAL;
1189 }
1190
1191 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1192 per_pin->mux_nids,
1193 HDA_MAX_CONNECTIONS);
1194
1195 return 0;
1196 }
1197
1198 static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1199 struct hdmi_spec_per_pin *per_pin)
1200 {
1201 int i;
1202
1203 /* try the prefer PCM */
1204 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1205 return per_pin->pin_nid_idx;
1206
1207 /* have a second try; check the "reserved area" over num_pins */
1208 for (i = spec->num_pins; i < spec->pcm_used; i++) {
1209 if (!test_bit(i, &spec->pcm_bitmap))
1210 return i;
1211 }
1212
1213 /* the last try; check the empty slots in pins */
1214 for (i = 0; i < spec->num_pins; i++) {
1215 if (!test_bit(i, &spec->pcm_bitmap))
1216 return i;
1217 }
1218 return -EBUSY;
1219 }
1220
1221 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1222 struct hdmi_spec_per_pin *per_pin)
1223 {
1224 int idx;
1225
1226 /* pcm already be attached to the pin */
1227 if (per_pin->pcm)
1228 return;
1229 idx = hdmi_find_pcm_slot(spec, per_pin);
1230 if (idx == -EBUSY)
1231 return;
1232 per_pin->pcm_idx = idx;
1233 per_pin->pcm = get_hdmi_pcm(spec, idx);
1234 set_bit(idx, &spec->pcm_bitmap);
1235 }
1236
1237 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1238 struct hdmi_spec_per_pin *per_pin)
1239 {
1240 int idx;
1241
1242 /* pcm already be detached from the pin */
1243 if (!per_pin->pcm)
1244 return;
1245 idx = per_pin->pcm_idx;
1246 per_pin->pcm_idx = -1;
1247 per_pin->pcm = NULL;
1248 if (idx >= 0 && idx < spec->pcm_used)
1249 clear_bit(idx, &spec->pcm_bitmap);
1250 }
1251
1252 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1253 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1254 {
1255 int mux_idx;
1256
1257 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1258 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1259 break;
1260 return mux_idx;
1261 }
1262
1263 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1264
1265 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1266 struct hdmi_spec_per_pin *per_pin)
1267 {
1268 struct hda_codec *codec = per_pin->codec;
1269 struct hda_pcm *pcm;
1270 struct hda_pcm_stream *hinfo;
1271 struct snd_pcm_substream *substream;
1272 int mux_idx;
1273 bool non_pcm;
1274
1275 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1276 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1277 else
1278 return;
1279 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1280 return;
1281
1282 /* hdmi audio only uses playback and one substream */
1283 hinfo = pcm->stream;
1284 substream = pcm->pcm->streams[0].substream;
1285
1286 per_pin->cvt_nid = hinfo->nid;
1287
1288 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1289 if (mux_idx < per_pin->num_mux_nids)
1290 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1291 AC_VERB_SET_CONNECT_SEL,
1292 mux_idx);
1293 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1294
1295 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1296 if (substream->runtime)
1297 per_pin->channels = substream->runtime->channels;
1298 per_pin->setup = true;
1299 per_pin->mux_idx = mux_idx;
1300
1301 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1302 }
1303
1304 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1305 struct hdmi_spec_per_pin *per_pin)
1306 {
1307 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1308 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1309
1310 per_pin->chmap_set = false;
1311 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1312
1313 per_pin->setup = false;
1314 per_pin->channels = 0;
1315 }
1316
1317 /* update per_pin ELD from the given new ELD;
1318 * setup info frame and notification accordingly
1319 */
1320 static void update_eld(struct hda_codec *codec,
1321 struct hdmi_spec_per_pin *per_pin,
1322 struct hdmi_eld *eld)
1323 {
1324 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1325 struct hdmi_spec *spec = codec->spec;
1326 bool old_eld_valid = pin_eld->eld_valid;
1327 bool eld_changed;
1328 int pcm_idx = -1;
1329
1330 /* for monitor disconnection, save pcm_idx firstly */
1331 pcm_idx = per_pin->pcm_idx;
1332 if (spec->dyn_pcm_assign) {
1333 if (eld->eld_valid) {
1334 hdmi_attach_hda_pcm(spec, per_pin);
1335 hdmi_pcm_setup_pin(spec, per_pin);
1336 } else {
1337 hdmi_pcm_reset_pin(spec, per_pin);
1338 hdmi_detach_hda_pcm(spec, per_pin);
1339 }
1340 }
1341 /* if pcm_idx == -1, it means this is in monitor connection event
1342 * we can get the correct pcm_idx now.
1343 */
1344 if (pcm_idx == -1)
1345 pcm_idx = per_pin->pcm_idx;
1346
1347 if (eld->eld_valid)
1348 snd_hdmi_show_eld(codec, &eld->info);
1349
1350 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1351 if (eld->eld_valid && pin_eld->eld_valid)
1352 if (pin_eld->eld_size != eld->eld_size ||
1353 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1354 eld->eld_size) != 0)
1355 eld_changed = true;
1356
1357 pin_eld->eld_valid = eld->eld_valid;
1358 pin_eld->eld_size = eld->eld_size;
1359 if (eld->eld_valid)
1360 memcpy(pin_eld->eld_buffer, eld->eld_buffer, eld->eld_size);
1361 pin_eld->info = eld->info;
1362
1363 /*
1364 * Re-setup pin and infoframe. This is needed e.g. when
1365 * - sink is first plugged-in
1366 * - transcoder can change during stream playback on Haswell
1367 * and this can make HW reset converter selection on a pin.
1368 */
1369 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1370 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1371 intel_verify_pin_cvt_connect(codec, per_pin);
1372 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
1373 per_pin->mux_idx);
1374 }
1375
1376 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1377 }
1378
1379 if (eld_changed && pcm_idx >= 0)
1380 snd_ctl_notify(codec->card,
1381 SNDRV_CTL_EVENT_MASK_VALUE |
1382 SNDRV_CTL_EVENT_MASK_INFO,
1383 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1384 }
1385
1386 /* update ELD and jack state via HD-audio verbs */
1387 static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1388 int repoll)
1389 {
1390 struct hda_jack_tbl *jack;
1391 struct hda_codec *codec = per_pin->codec;
1392 struct hdmi_spec *spec = codec->spec;
1393 struct hdmi_eld *eld = &spec->temp_eld;
1394 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1395 hda_nid_t pin_nid = per_pin->pin_nid;
1396 /*
1397 * Always execute a GetPinSense verb here, even when called from
1398 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1399 * response's PD bit is not the real PD value, but indicates that
1400 * the real PD value changed. An older version of the HD-audio
1401 * specification worked this way. Hence, we just ignore the data in
1402 * the unsolicited response to avoid custom WARs.
1403 */
1404 int present;
1405 bool ret;
1406 bool do_repoll = false;
1407
1408 present = snd_hda_pin_sense(codec, pin_nid);
1409
1410 mutex_lock(&per_pin->lock);
1411 pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1412 if (pin_eld->monitor_present)
1413 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1414 else
1415 eld->eld_valid = false;
1416
1417 codec_dbg(codec,
1418 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1419 codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1420
1421 if (eld->eld_valid) {
1422 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1423 &eld->eld_size) < 0)
1424 eld->eld_valid = false;
1425 else {
1426 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1427 eld->eld_size) < 0)
1428 eld->eld_valid = false;
1429 }
1430 if (!eld->eld_valid && repoll)
1431 do_repoll = true;
1432 }
1433
1434 if (do_repoll)
1435 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1436 else
1437 update_eld(codec, per_pin, eld);
1438
1439 ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1440
1441 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1442 if (jack)
1443 jack->block_report = !ret;
1444
1445 mutex_unlock(&per_pin->lock);
1446 return ret;
1447 }
1448
1449 static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1450 struct hdmi_spec_per_pin *per_pin)
1451 {
1452 struct hdmi_spec *spec = codec->spec;
1453 struct snd_jack *jack = NULL;
1454 struct hda_jack_tbl *jack_tbl;
1455
1456 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1457 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1458 * NULL even after snd_hda_jack_tbl_clear() is called to
1459 * free snd_jack. This may cause access invalid memory
1460 * when calling snd_jack_report
1461 */
1462 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1463 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1464 else if (!spec->dyn_pcm_assign) {
1465 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1466 if (jack_tbl)
1467 jack = jack_tbl->jack;
1468 }
1469 return jack;
1470 }
1471
1472 /* update ELD and jack state via audio component */
1473 static void sync_eld_via_acomp(struct hda_codec *codec,
1474 struct hdmi_spec_per_pin *per_pin)
1475 {
1476 struct hdmi_spec *spec = codec->spec;
1477 struct hdmi_eld *eld = &spec->temp_eld;
1478 struct snd_jack *jack = NULL;
1479 int size;
1480
1481 mutex_lock(&per_pin->lock);
1482 size = snd_hdac_acomp_get_eld(&codec->bus->core, per_pin->pin_nid,
1483 &eld->monitor_present, eld->eld_buffer,
1484 ELD_MAX_SIZE);
1485 if (size < 0)
1486 goto unlock;
1487 if (size > 0) {
1488 size = min(size, ELD_MAX_SIZE);
1489 if (snd_hdmi_parse_eld(codec, &eld->info,
1490 eld->eld_buffer, size) < 0)
1491 size = -EINVAL;
1492 }
1493
1494 if (size > 0) {
1495 eld->eld_valid = true;
1496 eld->eld_size = size;
1497 } else {
1498 eld->eld_valid = false;
1499 eld->eld_size = 0;
1500 }
1501
1502 /* pcm_idx >=0 before update_eld() means it is in monitor
1503 * disconnected event. Jack must be fetched before update_eld()
1504 */
1505 jack = pin_idx_to_jack(codec, per_pin);
1506 update_eld(codec, per_pin, eld);
1507 if (jack == NULL)
1508 jack = pin_idx_to_jack(codec, per_pin);
1509 if (jack == NULL)
1510 goto unlock;
1511 snd_jack_report(jack,
1512 eld->monitor_present ? SND_JACK_AVOUT : 0);
1513 unlock:
1514 mutex_unlock(&per_pin->lock);
1515 }
1516
1517 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1518 {
1519 struct hda_codec *codec = per_pin->codec;
1520 struct hdmi_spec *spec = codec->spec;
1521 int ret;
1522
1523 /* no temporary power up/down needed for component notifier */
1524 if (!codec_has_acomp(codec))
1525 snd_hda_power_up_pm(codec);
1526
1527 mutex_lock(&spec->pcm_lock);
1528 if (codec_has_acomp(codec)) {
1529 sync_eld_via_acomp(codec, per_pin);
1530 ret = false; /* don't call snd_hda_jack_report_sync() */
1531 } else {
1532 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1533 }
1534 mutex_unlock(&spec->pcm_lock);
1535
1536 if (!codec_has_acomp(codec))
1537 snd_hda_power_down_pm(codec);
1538
1539 return ret;
1540 }
1541
1542 static void hdmi_repoll_eld(struct work_struct *work)
1543 {
1544 struct hdmi_spec_per_pin *per_pin =
1545 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1546
1547 if (per_pin->repoll_count++ > 6)
1548 per_pin->repoll_count = 0;
1549
1550 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1551 snd_hda_jack_report_sync(per_pin->codec);
1552 }
1553
1554 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1555 hda_nid_t nid);
1556
1557 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1558 {
1559 struct hdmi_spec *spec = codec->spec;
1560 unsigned int caps, config;
1561 int pin_idx;
1562 struct hdmi_spec_per_pin *per_pin;
1563 int err;
1564
1565 caps = snd_hda_query_pin_caps(codec, pin_nid);
1566 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1567 return 0;
1568
1569 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1570 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1571 return 0;
1572
1573 if (is_haswell_plus(codec))
1574 intel_haswell_fixup_connect_list(codec, pin_nid);
1575
1576 pin_idx = spec->num_pins;
1577 per_pin = snd_array_new(&spec->pins);
1578 if (!per_pin)
1579 return -ENOMEM;
1580
1581 per_pin->pin_nid = pin_nid;
1582 per_pin->non_pcm = false;
1583 if (spec->dyn_pcm_assign)
1584 per_pin->pcm_idx = -1;
1585 else {
1586 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1587 per_pin->pcm_idx = pin_idx;
1588 }
1589 per_pin->pin_nid_idx = pin_idx;
1590
1591 err = hdmi_read_pin_conn(codec, pin_idx);
1592 if (err < 0)
1593 return err;
1594
1595 spec->num_pins++;
1596
1597 return 0;
1598 }
1599
1600 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1601 {
1602 struct hdmi_spec *spec = codec->spec;
1603 struct hdmi_spec_per_cvt *per_cvt;
1604 unsigned int chans;
1605 int err;
1606
1607 chans = get_wcaps(codec, cvt_nid);
1608 chans = get_wcaps_channels(chans);
1609
1610 per_cvt = snd_array_new(&spec->cvts);
1611 if (!per_cvt)
1612 return -ENOMEM;
1613
1614 per_cvt->cvt_nid = cvt_nid;
1615 per_cvt->channels_min = 2;
1616 if (chans <= 16) {
1617 per_cvt->channels_max = chans;
1618 if (chans > spec->chmap.channels_max)
1619 spec->chmap.channels_max = chans;
1620 }
1621
1622 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1623 &per_cvt->rates,
1624 &per_cvt->formats,
1625 &per_cvt->maxbps);
1626 if (err < 0)
1627 return err;
1628
1629 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1630 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1631 spec->num_cvts++;
1632
1633 return 0;
1634 }
1635
1636 static int hdmi_parse_codec(struct hda_codec *codec)
1637 {
1638 hda_nid_t nid;
1639 int i, nodes;
1640
1641 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1642 if (!nid || nodes < 0) {
1643 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1644 return -EINVAL;
1645 }
1646
1647 for (i = 0; i < nodes; i++, nid++) {
1648 unsigned int caps;
1649 unsigned int type;
1650
1651 caps = get_wcaps(codec, nid);
1652 type = get_wcaps_type(caps);
1653
1654 if (!(caps & AC_WCAP_DIGITAL))
1655 continue;
1656
1657 switch (type) {
1658 case AC_WID_AUD_OUT:
1659 hdmi_add_cvt(codec, nid);
1660 break;
1661 case AC_WID_PIN:
1662 hdmi_add_pin(codec, nid);
1663 break;
1664 }
1665 }
1666
1667 return 0;
1668 }
1669
1670 /*
1671 */
1672 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1673 {
1674 struct hda_spdif_out *spdif;
1675 bool non_pcm;
1676
1677 mutex_lock(&codec->spdif_mutex);
1678 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1679 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1680 mutex_unlock(&codec->spdif_mutex);
1681 return non_pcm;
1682 }
1683
1684 /*
1685 * HDMI callbacks
1686 */
1687
1688 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1689 struct hda_codec *codec,
1690 unsigned int stream_tag,
1691 unsigned int format,
1692 struct snd_pcm_substream *substream)
1693 {
1694 hda_nid_t cvt_nid = hinfo->nid;
1695 struct hdmi_spec *spec = codec->spec;
1696 int pin_idx;
1697 struct hdmi_spec_per_pin *per_pin;
1698 hda_nid_t pin_nid;
1699 struct snd_pcm_runtime *runtime = substream->runtime;
1700 bool non_pcm;
1701 int pinctl;
1702 int err;
1703
1704 mutex_lock(&spec->pcm_lock);
1705 pin_idx = hinfo_to_pin_index(codec, hinfo);
1706 if (spec->dyn_pcm_assign && pin_idx < 0) {
1707 /* when dyn_pcm_assign and pcm is not bound to a pin
1708 * skip pin setup and return 0 to make audio playback
1709 * be ongoing
1710 */
1711 intel_not_share_assigned_cvt_nid(codec, 0, cvt_nid);
1712 snd_hda_codec_setup_stream(codec, cvt_nid,
1713 stream_tag, 0, format);
1714 mutex_unlock(&spec->pcm_lock);
1715 return 0;
1716 }
1717
1718 if (snd_BUG_ON(pin_idx < 0)) {
1719 mutex_unlock(&spec->pcm_lock);
1720 return -EINVAL;
1721 }
1722 per_pin = get_pin(spec, pin_idx);
1723 pin_nid = per_pin->pin_nid;
1724 if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1725 /* Verify pin:cvt selections to avoid silent audio after S3.
1726 * After S3, the audio driver restores pin:cvt selections
1727 * but this can happen before gfx is ready and such selection
1728 * is overlooked by HW. Thus multiple pins can share a same
1729 * default convertor and mute control will affect each other,
1730 * which can cause a resumed audio playback become silent
1731 * after S3.
1732 */
1733 intel_verify_pin_cvt_connect(codec, per_pin);
1734 intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1735 }
1736
1737 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1738 /* Todo: add DP1.2 MST audio support later */
1739 snd_hdac_sync_audio_rate(&codec->bus->core, pin_nid, runtime->rate);
1740
1741 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1742 mutex_lock(&per_pin->lock);
1743 per_pin->channels = substream->runtime->channels;
1744 per_pin->setup = true;
1745
1746 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1747 mutex_unlock(&per_pin->lock);
1748 if (spec->dyn_pin_out) {
1749 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1750 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1751 snd_hda_codec_write(codec, pin_nid, 0,
1752 AC_VERB_SET_PIN_WIDGET_CONTROL,
1753 pinctl | PIN_OUT);
1754 }
1755
1756 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1757 stream_tag, format);
1758 mutex_unlock(&spec->pcm_lock);
1759 return err;
1760 }
1761
1762 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1763 struct hda_codec *codec,
1764 struct snd_pcm_substream *substream)
1765 {
1766 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1767 return 0;
1768 }
1769
1770 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1771 struct hda_codec *codec,
1772 struct snd_pcm_substream *substream)
1773 {
1774 struct hdmi_spec *spec = codec->spec;
1775 int cvt_idx, pin_idx, pcm_idx;
1776 struct hdmi_spec_per_cvt *per_cvt;
1777 struct hdmi_spec_per_pin *per_pin;
1778 int pinctl;
1779
1780 if (hinfo->nid) {
1781 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1782 if (snd_BUG_ON(pcm_idx < 0))
1783 return -EINVAL;
1784 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1785 if (snd_BUG_ON(cvt_idx < 0))
1786 return -EINVAL;
1787 per_cvt = get_cvt(spec, cvt_idx);
1788
1789 snd_BUG_ON(!per_cvt->assigned);
1790 per_cvt->assigned = 0;
1791 hinfo->nid = 0;
1792
1793 mutex_lock(&spec->pcm_lock);
1794 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1795 clear_bit(pcm_idx, &spec->pcm_in_use);
1796 pin_idx = hinfo_to_pin_index(codec, hinfo);
1797 if (spec->dyn_pcm_assign && pin_idx < 0) {
1798 mutex_unlock(&spec->pcm_lock);
1799 return 0;
1800 }
1801
1802 if (snd_BUG_ON(pin_idx < 0)) {
1803 mutex_unlock(&spec->pcm_lock);
1804 return -EINVAL;
1805 }
1806 per_pin = get_pin(spec, pin_idx);
1807
1808 if (spec->dyn_pin_out) {
1809 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1810 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1811 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1812 AC_VERB_SET_PIN_WIDGET_CONTROL,
1813 pinctl & ~PIN_OUT);
1814 }
1815
1816 mutex_lock(&per_pin->lock);
1817 per_pin->chmap_set = false;
1818 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1819
1820 per_pin->setup = false;
1821 per_pin->channels = 0;
1822 mutex_unlock(&per_pin->lock);
1823 mutex_unlock(&spec->pcm_lock);
1824 }
1825
1826 return 0;
1827 }
1828
1829 static const struct hda_pcm_ops generic_ops = {
1830 .open = hdmi_pcm_open,
1831 .close = hdmi_pcm_close,
1832 .prepare = generic_hdmi_playback_pcm_prepare,
1833 .cleanup = generic_hdmi_playback_pcm_cleanup,
1834 };
1835
1836 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
1837 unsigned char *chmap)
1838 {
1839 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1840 struct hdmi_spec *spec = codec->spec;
1841 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1842
1843 /* chmap is already set to 0 in caller */
1844 if (!per_pin)
1845 return;
1846
1847 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
1848 }
1849
1850 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
1851 unsigned char *chmap, int prepared)
1852 {
1853 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1854 struct hdmi_spec *spec = codec->spec;
1855 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1856
1857 mutex_lock(&per_pin->lock);
1858 per_pin->chmap_set = true;
1859 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
1860 if (prepared)
1861 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1862 mutex_unlock(&per_pin->lock);
1863 }
1864
1865 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
1866 {
1867 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
1868 struct hdmi_spec *spec = codec->spec;
1869 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
1870
1871 return per_pin ? true:false;
1872 }
1873
1874 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1875 {
1876 struct hdmi_spec *spec = codec->spec;
1877 int pin_idx;
1878
1879 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1880 struct hda_pcm *info;
1881 struct hda_pcm_stream *pstr;
1882
1883 info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
1884 if (!info)
1885 return -ENOMEM;
1886
1887 spec->pcm_rec[pin_idx].pcm = info;
1888 spec->pcm_used++;
1889 info->pcm_type = HDA_PCM_TYPE_HDMI;
1890 info->own_chmap = true;
1891
1892 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1893 pstr->substreams = 1;
1894 pstr->ops = generic_ops;
1895 /* other pstr fields are set in open */
1896 }
1897
1898 return 0;
1899 }
1900
1901 static void free_hdmi_jack_priv(struct snd_jack *jack)
1902 {
1903 struct hdmi_pcm *pcm = jack->private_data;
1904
1905 pcm->jack = NULL;
1906 }
1907
1908 static int add_hdmi_jack_kctl(struct hda_codec *codec,
1909 struct hdmi_spec *spec,
1910 int pcm_idx,
1911 const char *name)
1912 {
1913 struct snd_jack *jack;
1914 int err;
1915
1916 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
1917 true, false);
1918 if (err < 0)
1919 return err;
1920
1921 spec->pcm_rec[pcm_idx].jack = jack;
1922 jack->private_data = &spec->pcm_rec[pcm_idx];
1923 jack->private_free = free_hdmi_jack_priv;
1924 return 0;
1925 }
1926
1927 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
1928 {
1929 char hdmi_str[32] = "HDMI/DP";
1930 struct hdmi_spec *spec = codec->spec;
1931 struct hdmi_spec_per_pin *per_pin;
1932 struct hda_jack_tbl *jack;
1933 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
1934 bool phantom_jack;
1935 int ret;
1936
1937 if (pcmdev > 0)
1938 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
1939
1940 if (spec->dyn_pcm_assign)
1941 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
1942
1943 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
1944 /* if !dyn_pcm_assign, it must be non-MST mode.
1945 * This means pcms and pins are statically mapped.
1946 * And pcm_idx is pin_idx.
1947 */
1948 per_pin = get_pin(spec, pcm_idx);
1949 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
1950 if (phantom_jack)
1951 strncat(hdmi_str, " Phantom",
1952 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
1953 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
1954 phantom_jack);
1955 if (ret < 0)
1956 return ret;
1957 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1958 if (jack == NULL)
1959 return 0;
1960 /* assign jack->jack to pcm_rec[].jack to
1961 * align with dyn_pcm_assign mode
1962 */
1963 spec->pcm_rec[pcm_idx].jack = jack->jack;
1964 return 0;
1965 }
1966
1967 static int generic_hdmi_build_controls(struct hda_codec *codec)
1968 {
1969 struct hdmi_spec *spec = codec->spec;
1970 int err;
1971 int pin_idx, pcm_idx;
1972
1973
1974 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
1975 err = generic_hdmi_build_jack(codec, pcm_idx);
1976 if (err < 0)
1977 return err;
1978
1979 /* create the spdif for each pcm
1980 * pin will be bound when monitor is connected
1981 */
1982 if (spec->dyn_pcm_assign)
1983 err = snd_hda_create_dig_out_ctls(codec,
1984 0, spec->cvt_nids[0],
1985 HDA_PCM_TYPE_HDMI);
1986 else {
1987 struct hdmi_spec_per_pin *per_pin =
1988 get_pin(spec, pcm_idx);
1989 err = snd_hda_create_dig_out_ctls(codec,
1990 per_pin->pin_nid,
1991 per_pin->mux_nids[0],
1992 HDA_PCM_TYPE_HDMI);
1993 }
1994 if (err < 0)
1995 return err;
1996 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1997
1998 /* add control for ELD Bytes */
1999 err = hdmi_create_eld_ctl(codec, pcm_idx,
2000 get_pcm_rec(spec, pcm_idx)->device);
2001 if (err < 0)
2002 return err;
2003 }
2004
2005 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2006 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2007
2008 hdmi_present_sense(per_pin, 0);
2009 }
2010
2011 /* add channel maps */
2012 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2013 struct hda_pcm *pcm;
2014
2015 pcm = get_pcm_rec(spec, pcm_idx);
2016 if (!pcm || !pcm->pcm)
2017 break;
2018 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2019 if (err < 0)
2020 return err;
2021 }
2022
2023 return 0;
2024 }
2025
2026 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2027 {
2028 struct hdmi_spec *spec = codec->spec;
2029 int pin_idx;
2030
2031 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2032 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2033
2034 per_pin->codec = codec;
2035 mutex_init(&per_pin->lock);
2036 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2037 eld_proc_new(per_pin, pin_idx);
2038 }
2039 return 0;
2040 }
2041
2042 static int generic_hdmi_init(struct hda_codec *codec)
2043 {
2044 struct hdmi_spec *spec = codec->spec;
2045 int pin_idx;
2046
2047 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2048 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2049 hda_nid_t pin_nid = per_pin->pin_nid;
2050
2051 hdmi_init_pin(codec, pin_nid);
2052 if (!codec_has_acomp(codec))
2053 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2054 codec->jackpoll_interval > 0 ?
2055 jack_callback : NULL);
2056 }
2057 return 0;
2058 }
2059
2060 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2061 {
2062 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2063 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2064 }
2065
2066 static void hdmi_array_free(struct hdmi_spec *spec)
2067 {
2068 snd_array_free(&spec->pins);
2069 snd_array_free(&spec->cvts);
2070 }
2071
2072 static void generic_hdmi_free(struct hda_codec *codec)
2073 {
2074 struct hdmi_spec *spec = codec->spec;
2075 int pin_idx, pcm_idx;
2076
2077 if (codec_has_acomp(codec))
2078 snd_hdac_i915_register_notifier(NULL);
2079
2080 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2081 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2082 cancel_delayed_work_sync(&per_pin->work);
2083 eld_proc_free(per_pin);
2084 }
2085
2086 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2087 if (spec->pcm_rec[pcm_idx].jack == NULL)
2088 continue;
2089 if (spec->dyn_pcm_assign)
2090 snd_device_free(codec->card,
2091 spec->pcm_rec[pcm_idx].jack);
2092 else
2093 spec->pcm_rec[pcm_idx].jack = NULL;
2094 }
2095
2096 if (spec->i915_bound)
2097 snd_hdac_i915_exit(&codec->bus->core);
2098 hdmi_array_free(spec);
2099 kfree(spec);
2100 }
2101
2102 #ifdef CONFIG_PM
2103 static int generic_hdmi_resume(struct hda_codec *codec)
2104 {
2105 struct hdmi_spec *spec = codec->spec;
2106 int pin_idx;
2107
2108 codec->patch_ops.init(codec);
2109 regcache_sync(codec->core.regmap);
2110
2111 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2112 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2113 hdmi_present_sense(per_pin, 1);
2114 }
2115 return 0;
2116 }
2117 #endif
2118
2119 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2120 .init = generic_hdmi_init,
2121 .free = generic_hdmi_free,
2122 .build_pcms = generic_hdmi_build_pcms,
2123 .build_controls = generic_hdmi_build_controls,
2124 .unsol_event = hdmi_unsol_event,
2125 #ifdef CONFIG_PM
2126 .resume = generic_hdmi_resume,
2127 #endif
2128 };
2129
2130 static const struct hdmi_ops generic_standard_hdmi_ops = {
2131 .pin_get_eld = snd_hdmi_get_eld,
2132 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2133 .pin_hbr_setup = hdmi_pin_hbr_setup,
2134 .setup_stream = hdmi_setup_stream,
2135 };
2136
2137 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2138 hda_nid_t nid)
2139 {
2140 struct hdmi_spec *spec = codec->spec;
2141 hda_nid_t conns[4];
2142 int nconns;
2143
2144 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2145 if (nconns == spec->num_cvts &&
2146 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2147 return;
2148
2149 /* override pins connection list */
2150 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2151 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2152 }
2153
2154 #define INTEL_VENDOR_NID 0x08
2155 #define INTEL_GET_VENDOR_VERB 0xf81
2156 #define INTEL_SET_VENDOR_VERB 0x781
2157 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2158 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2159
2160 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2161 bool update_tree)
2162 {
2163 unsigned int vendor_param;
2164
2165 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2166 INTEL_GET_VENDOR_VERB, 0);
2167 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2168 return;
2169
2170 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2171 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2172 INTEL_SET_VENDOR_VERB, vendor_param);
2173 if (vendor_param == -1)
2174 return;
2175
2176 if (update_tree)
2177 snd_hda_codec_update_widgets(codec);
2178 }
2179
2180 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2181 {
2182 unsigned int vendor_param;
2183
2184 vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2185 INTEL_GET_VENDOR_VERB, 0);
2186 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2187 return;
2188
2189 /* enable DP1.2 mode */
2190 vendor_param |= INTEL_EN_DP12;
2191 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2192 snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2193 INTEL_SET_VENDOR_VERB, vendor_param);
2194 }
2195
2196 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2197 * Otherwise you may get severe h/w communication errors.
2198 */
2199 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2200 unsigned int power_state)
2201 {
2202 if (power_state == AC_PWRST_D0) {
2203 intel_haswell_enable_all_pins(codec, false);
2204 intel_haswell_fixup_enable_dp12(codec);
2205 }
2206
2207 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2208 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2209 }
2210
2211 static void intel_pin_eld_notify(void *audio_ptr, int port)
2212 {
2213 struct hda_codec *codec = audio_ptr;
2214 int pin_nid = port + 0x04;
2215
2216 /* we assume only from port-B to port-D */
2217 if (port < 1 || port > 3)
2218 return;
2219
2220 /* skip notification during system suspend (but not in runtime PM);
2221 * the state will be updated at resume
2222 */
2223 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2224 return;
2225 /* ditto during suspend/resume process itself */
2226 if (atomic_read(&(codec)->core.in_pm))
2227 return;
2228
2229 check_presence_and_report(codec, pin_nid);
2230 }
2231
2232 static int patch_generic_hdmi(struct hda_codec *codec)
2233 {
2234 struct hdmi_spec *spec;
2235
2236 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2237 if (spec == NULL)
2238 return -ENOMEM;
2239
2240 spec->ops = generic_standard_hdmi_ops;
2241 mutex_init(&spec->pcm_lock);
2242 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2243
2244 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2245 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2246 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2247
2248 codec->spec = spec;
2249 hdmi_array_init(spec, 4);
2250
2251 /* Try to bind with i915 for Intel HSW+ codecs (if not done yet) */
2252 if (!codec_has_acomp(codec) &&
2253 (codec->core.vendor_id >> 16) == 0x8086 &&
2254 is_haswell_plus(codec))
2255 if (!snd_hdac_i915_init(&codec->bus->core))
2256 spec->i915_bound = true;
2257
2258 if (is_haswell_plus(codec)) {
2259 intel_haswell_enable_all_pins(codec, true);
2260 intel_haswell_fixup_enable_dp12(codec);
2261 }
2262
2263 /* For Valleyview/Cherryview, only the display codec is in the display
2264 * power well and can use link_power ops to request/release the power.
2265 * For Haswell/Broadwell, the controller is also in the power well and
2266 * can cover the codec power request, and so need not set this flag.
2267 * For previous platforms, there is no such power well feature.
2268 */
2269 if (is_valleyview_plus(codec) || is_skylake(codec) ||
2270 is_broxton(codec))
2271 codec->core.link_power_control = 1;
2272
2273 if (hdmi_parse_codec(codec) < 0) {
2274 if (spec->i915_bound)
2275 snd_hdac_i915_exit(&codec->bus->core);
2276 codec->spec = NULL;
2277 kfree(spec);
2278 return -EINVAL;
2279 }
2280 codec->patch_ops = generic_hdmi_patch_ops;
2281 if (is_haswell_plus(codec)) {
2282 codec->patch_ops.set_power_state = haswell_set_power_state;
2283 codec->dp_mst = true;
2284 }
2285
2286 /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2287 if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2288 codec->auto_runtime_pm = 1;
2289
2290 generic_hdmi_init_per_pins(codec);
2291
2292
2293 if (codec_has_acomp(codec)) {
2294 codec->depop_delay = 0;
2295 spec->i915_audio_ops.audio_ptr = codec;
2296 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2297 * will call pin_eld_notify with using audio_ptr pointer
2298 * We need make sure audio_ptr is really setup
2299 */
2300 wmb();
2301 spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
2302 snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
2303 }
2304
2305 WARN_ON(spec->dyn_pcm_assign && !codec_has_acomp(codec));
2306 return 0;
2307 }
2308
2309 /*
2310 * Shared non-generic implementations
2311 */
2312
2313 static int simple_playback_build_pcms(struct hda_codec *codec)
2314 {
2315 struct hdmi_spec *spec = codec->spec;
2316 struct hda_pcm *info;
2317 unsigned int chans;
2318 struct hda_pcm_stream *pstr;
2319 struct hdmi_spec_per_cvt *per_cvt;
2320
2321 per_cvt = get_cvt(spec, 0);
2322 chans = get_wcaps(codec, per_cvt->cvt_nid);
2323 chans = get_wcaps_channels(chans);
2324
2325 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2326 if (!info)
2327 return -ENOMEM;
2328 spec->pcm_rec[0].pcm = info;
2329 info->pcm_type = HDA_PCM_TYPE_HDMI;
2330 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2331 *pstr = spec->pcm_playback;
2332 pstr->nid = per_cvt->cvt_nid;
2333 if (pstr->channels_max <= 2 && chans && chans <= 16)
2334 pstr->channels_max = chans;
2335
2336 return 0;
2337 }
2338
2339 /* unsolicited event for jack sensing */
2340 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2341 unsigned int res)
2342 {
2343 snd_hda_jack_set_dirty_all(codec);
2344 snd_hda_jack_report_sync(codec);
2345 }
2346
2347 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2348 * as long as spec->pins[] is set correctly
2349 */
2350 #define simple_hdmi_build_jack generic_hdmi_build_jack
2351
2352 static int simple_playback_build_controls(struct hda_codec *codec)
2353 {
2354 struct hdmi_spec *spec = codec->spec;
2355 struct hdmi_spec_per_cvt *per_cvt;
2356 int err;
2357
2358 per_cvt = get_cvt(spec, 0);
2359 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2360 per_cvt->cvt_nid,
2361 HDA_PCM_TYPE_HDMI);
2362 if (err < 0)
2363 return err;
2364 return simple_hdmi_build_jack(codec, 0);
2365 }
2366
2367 static int simple_playback_init(struct hda_codec *codec)
2368 {
2369 struct hdmi_spec *spec = codec->spec;
2370 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2371 hda_nid_t pin = per_pin->pin_nid;
2372
2373 snd_hda_codec_write(codec, pin, 0,
2374 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2375 /* some codecs require to unmute the pin */
2376 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2377 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2378 AMP_OUT_UNMUTE);
2379 snd_hda_jack_detect_enable(codec, pin);
2380 return 0;
2381 }
2382
2383 static void simple_playback_free(struct hda_codec *codec)
2384 {
2385 struct hdmi_spec *spec = codec->spec;
2386
2387 hdmi_array_free(spec);
2388 kfree(spec);
2389 }
2390
2391 /*
2392 * Nvidia specific implementations
2393 */
2394
2395 #define Nv_VERB_SET_Channel_Allocation 0xF79
2396 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2397 #define Nv_VERB_SET_Audio_Protection_On 0xF98
2398 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
2399
2400 #define nvhdmi_master_con_nid_7x 0x04
2401 #define nvhdmi_master_pin_nid_7x 0x05
2402
2403 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2404 /*front, rear, clfe, rear_surr */
2405 0x6, 0x8, 0xa, 0xc,
2406 };
2407
2408 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2409 /* set audio protect on */
2410 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2411 /* enable digital output on pin widget */
2412 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2413 {} /* terminator */
2414 };
2415
2416 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2417 /* set audio protect on */
2418 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2419 /* enable digital output on pin widget */
2420 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2421 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2422 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2423 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2424 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2425 {} /* terminator */
2426 };
2427
2428 #ifdef LIMITED_RATE_FMT_SUPPORT
2429 /* support only the safe format and rate */
2430 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
2431 #define SUPPORTED_MAXBPS 16
2432 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
2433 #else
2434 /* support all rates and formats */
2435 #define SUPPORTED_RATES \
2436 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2437 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2438 SNDRV_PCM_RATE_192000)
2439 #define SUPPORTED_MAXBPS 24
2440 #define SUPPORTED_FORMATS \
2441 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2442 #endif
2443
2444 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2445 {
2446 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2447 return 0;
2448 }
2449
2450 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2451 {
2452 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2453 return 0;
2454 }
2455
2456 static unsigned int channels_2_6_8[] = {
2457 2, 6, 8
2458 };
2459
2460 static unsigned int channels_2_8[] = {
2461 2, 8
2462 };
2463
2464 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2465 .count = ARRAY_SIZE(channels_2_6_8),
2466 .list = channels_2_6_8,
2467 .mask = 0,
2468 };
2469
2470 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2471 .count = ARRAY_SIZE(channels_2_8),
2472 .list = channels_2_8,
2473 .mask = 0,
2474 };
2475
2476 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2477 struct hda_codec *codec,
2478 struct snd_pcm_substream *substream)
2479 {
2480 struct hdmi_spec *spec = codec->spec;
2481 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2482
2483 switch (codec->preset->vendor_id) {
2484 case 0x10de0002:
2485 case 0x10de0003:
2486 case 0x10de0005:
2487 case 0x10de0006:
2488 hw_constraints_channels = &hw_constraints_2_8_channels;
2489 break;
2490 case 0x10de0007:
2491 hw_constraints_channels = &hw_constraints_2_6_8_channels;
2492 break;
2493 default:
2494 break;
2495 }
2496
2497 if (hw_constraints_channels != NULL) {
2498 snd_pcm_hw_constraint_list(substream->runtime, 0,
2499 SNDRV_PCM_HW_PARAM_CHANNELS,
2500 hw_constraints_channels);
2501 } else {
2502 snd_pcm_hw_constraint_step(substream->runtime, 0,
2503 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2504 }
2505
2506 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2507 }
2508
2509 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2510 struct hda_codec *codec,
2511 struct snd_pcm_substream *substream)
2512 {
2513 struct hdmi_spec *spec = codec->spec;
2514 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2515 }
2516
2517 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2518 struct hda_codec *codec,
2519 unsigned int stream_tag,
2520 unsigned int format,
2521 struct snd_pcm_substream *substream)
2522 {
2523 struct hdmi_spec *spec = codec->spec;
2524 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2525 stream_tag, format, substream);
2526 }
2527
2528 static const struct hda_pcm_stream simple_pcm_playback = {
2529 .substreams = 1,
2530 .channels_min = 2,
2531 .channels_max = 2,
2532 .ops = {
2533 .open = simple_playback_pcm_open,
2534 .close = simple_playback_pcm_close,
2535 .prepare = simple_playback_pcm_prepare
2536 },
2537 };
2538
2539 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2540 .build_controls = simple_playback_build_controls,
2541 .build_pcms = simple_playback_build_pcms,
2542 .init = simple_playback_init,
2543 .free = simple_playback_free,
2544 .unsol_event = simple_hdmi_unsol_event,
2545 };
2546
2547 static int patch_simple_hdmi(struct hda_codec *codec,
2548 hda_nid_t cvt_nid, hda_nid_t pin_nid)
2549 {
2550 struct hdmi_spec *spec;
2551 struct hdmi_spec_per_cvt *per_cvt;
2552 struct hdmi_spec_per_pin *per_pin;
2553
2554 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2555 if (!spec)
2556 return -ENOMEM;
2557
2558 codec->spec = spec;
2559 hdmi_array_init(spec, 1);
2560
2561 spec->multiout.num_dacs = 0; /* no analog */
2562 spec->multiout.max_channels = 2;
2563 spec->multiout.dig_out_nid = cvt_nid;
2564 spec->num_cvts = 1;
2565 spec->num_pins = 1;
2566 per_pin = snd_array_new(&spec->pins);
2567 per_cvt = snd_array_new(&spec->cvts);
2568 if (!per_pin || !per_cvt) {
2569 simple_playback_free(codec);
2570 return -ENOMEM;
2571 }
2572 per_cvt->cvt_nid = cvt_nid;
2573 per_pin->pin_nid = pin_nid;
2574 spec->pcm_playback = simple_pcm_playback;
2575
2576 codec->patch_ops = simple_hdmi_patch_ops;
2577
2578 return 0;
2579 }
2580
2581 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2582 int channels)
2583 {
2584 unsigned int chanmask;
2585 int chan = channels ? (channels - 1) : 1;
2586
2587 switch (channels) {
2588 default:
2589 case 0:
2590 case 2:
2591 chanmask = 0x00;
2592 break;
2593 case 4:
2594 chanmask = 0x08;
2595 break;
2596 case 6:
2597 chanmask = 0x0b;
2598 break;
2599 case 8:
2600 chanmask = 0x13;
2601 break;
2602 }
2603
2604 /* Set the audio infoframe channel allocation and checksum fields. The
2605 * channel count is computed implicitly by the hardware. */
2606 snd_hda_codec_write(codec, 0x1, 0,
2607 Nv_VERB_SET_Channel_Allocation, chanmask);
2608
2609 snd_hda_codec_write(codec, 0x1, 0,
2610 Nv_VERB_SET_Info_Frame_Checksum,
2611 (0x71 - chan - chanmask));
2612 }
2613
2614 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2615 struct hda_codec *codec,
2616 struct snd_pcm_substream *substream)
2617 {
2618 struct hdmi_spec *spec = codec->spec;
2619 int i;
2620
2621 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2622 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2623 for (i = 0; i < 4; i++) {
2624 /* set the stream id */
2625 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2626 AC_VERB_SET_CHANNEL_STREAMID, 0);
2627 /* set the stream format */
2628 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2629 AC_VERB_SET_STREAM_FORMAT, 0);
2630 }
2631
2632 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
2633 * streams are disabled. */
2634 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2635
2636 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2637 }
2638
2639 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2640 struct hda_codec *codec,
2641 unsigned int stream_tag,
2642 unsigned int format,
2643 struct snd_pcm_substream *substream)
2644 {
2645 int chs;
2646 unsigned int dataDCC2, channel_id;
2647 int i;
2648 struct hdmi_spec *spec = codec->spec;
2649 struct hda_spdif_out *spdif;
2650 struct hdmi_spec_per_cvt *per_cvt;
2651
2652 mutex_lock(&codec->spdif_mutex);
2653 per_cvt = get_cvt(spec, 0);
2654 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2655
2656 chs = substream->runtime->channels;
2657
2658 dataDCC2 = 0x2;
2659
2660 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2661 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2662 snd_hda_codec_write(codec,
2663 nvhdmi_master_con_nid_7x,
2664 0,
2665 AC_VERB_SET_DIGI_CONVERT_1,
2666 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2667
2668 /* set the stream id */
2669 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2670 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2671
2672 /* set the stream format */
2673 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2674 AC_VERB_SET_STREAM_FORMAT, format);
2675
2676 /* turn on again (if needed) */
2677 /* enable and set the channel status audio/data flag */
2678 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2679 snd_hda_codec_write(codec,
2680 nvhdmi_master_con_nid_7x,
2681 0,
2682 AC_VERB_SET_DIGI_CONVERT_1,
2683 spdif->ctls & 0xff);
2684 snd_hda_codec_write(codec,
2685 nvhdmi_master_con_nid_7x,
2686 0,
2687 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2688 }
2689
2690 for (i = 0; i < 4; i++) {
2691 if (chs == 2)
2692 channel_id = 0;
2693 else
2694 channel_id = i * 2;
2695
2696 /* turn off SPDIF once;
2697 *otherwise the IEC958 bits won't be updated
2698 */
2699 if (codec->spdif_status_reset &&
2700 (spdif->ctls & AC_DIG1_ENABLE))
2701 snd_hda_codec_write(codec,
2702 nvhdmi_con_nids_7x[i],
2703 0,
2704 AC_VERB_SET_DIGI_CONVERT_1,
2705 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2706 /* set the stream id */
2707 snd_hda_codec_write(codec,
2708 nvhdmi_con_nids_7x[i],
2709 0,
2710 AC_VERB_SET_CHANNEL_STREAMID,
2711 (stream_tag << 4) | channel_id);
2712 /* set the stream format */
2713 snd_hda_codec_write(codec,
2714 nvhdmi_con_nids_7x[i],
2715 0,
2716 AC_VERB_SET_STREAM_FORMAT,
2717 format);
2718 /* turn on again (if needed) */
2719 /* enable and set the channel status audio/data flag */
2720 if (codec->spdif_status_reset &&
2721 (spdif->ctls & AC_DIG1_ENABLE)) {
2722 snd_hda_codec_write(codec,
2723 nvhdmi_con_nids_7x[i],
2724 0,
2725 AC_VERB_SET_DIGI_CONVERT_1,
2726 spdif->ctls & 0xff);
2727 snd_hda_codec_write(codec,
2728 nvhdmi_con_nids_7x[i],
2729 0,
2730 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2731 }
2732 }
2733
2734 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2735
2736 mutex_unlock(&codec->spdif_mutex);
2737 return 0;
2738 }
2739
2740 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2741 .substreams = 1,
2742 .channels_min = 2,
2743 .channels_max = 8,
2744 .nid = nvhdmi_master_con_nid_7x,
2745 .rates = SUPPORTED_RATES,
2746 .maxbps = SUPPORTED_MAXBPS,
2747 .formats = SUPPORTED_FORMATS,
2748 .ops = {
2749 .open = simple_playback_pcm_open,
2750 .close = nvhdmi_8ch_7x_pcm_close,
2751 .prepare = nvhdmi_8ch_7x_pcm_prepare
2752 },
2753 };
2754
2755 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2756 {
2757 struct hdmi_spec *spec;
2758 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2759 nvhdmi_master_pin_nid_7x);
2760 if (err < 0)
2761 return err;
2762
2763 codec->patch_ops.init = nvhdmi_7x_init_2ch;
2764 /* override the PCM rates, etc, as the codec doesn't give full list */
2765 spec = codec->spec;
2766 spec->pcm_playback.rates = SUPPORTED_RATES;
2767 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2768 spec->pcm_playback.formats = SUPPORTED_FORMATS;
2769 return 0;
2770 }
2771
2772 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2773 {
2774 struct hdmi_spec *spec = codec->spec;
2775 int err = simple_playback_build_pcms(codec);
2776 if (!err) {
2777 struct hda_pcm *info = get_pcm_rec(spec, 0);
2778 info->own_chmap = true;
2779 }
2780 return err;
2781 }
2782
2783 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2784 {
2785 struct hdmi_spec *spec = codec->spec;
2786 struct hda_pcm *info;
2787 struct snd_pcm_chmap *chmap;
2788 int err;
2789
2790 err = simple_playback_build_controls(codec);
2791 if (err < 0)
2792 return err;
2793
2794 /* add channel maps */
2795 info = get_pcm_rec(spec, 0);
2796 err = snd_pcm_add_chmap_ctls(info->pcm,
2797 SNDRV_PCM_STREAM_PLAYBACK,
2798 snd_pcm_alt_chmaps, 8, 0, &chmap);
2799 if (err < 0)
2800 return err;
2801 switch (codec->preset->vendor_id) {
2802 case 0x10de0002:
2803 case 0x10de0003:
2804 case 0x10de0005:
2805 case 0x10de0006:
2806 chmap->channel_mask = (1U << 2) | (1U << 8);
2807 break;
2808 case 0x10de0007:
2809 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2810 }
2811 return 0;
2812 }
2813
2814 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2815 {
2816 struct hdmi_spec *spec;
2817 int err = patch_nvhdmi_2ch(codec);
2818 if (err < 0)
2819 return err;
2820 spec = codec->spec;
2821 spec->multiout.max_channels = 8;
2822 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2823 codec->patch_ops.init = nvhdmi_7x_init_8ch;
2824 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2825 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2826
2827 /* Initialize the audio infoframe channel mask and checksum to something
2828 * valid */
2829 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2830
2831 return 0;
2832 }
2833
2834 /*
2835 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2836 * - 0x10de0015
2837 * - 0x10de0040
2838 */
2839 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
2840 struct hdac_cea_channel_speaker_allocation *cap, int channels)
2841 {
2842 if (cap->ca_index == 0x00 && channels == 2)
2843 return SNDRV_CTL_TLVT_CHMAP_FIXED;
2844
2845 /* If the speaker allocation matches the channel count, it is OK. */
2846 if (cap->channels != channels)
2847 return -1;
2848
2849 /* all channels are remappable freely */
2850 return SNDRV_CTL_TLVT_CHMAP_VAR;
2851 }
2852
2853 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
2854 int ca, int chs, unsigned char *map)
2855 {
2856 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2857 return -EINVAL;
2858
2859 return 0;
2860 }
2861
2862 static int patch_nvhdmi(struct hda_codec *codec)
2863 {
2864 struct hdmi_spec *spec;
2865 int err;
2866
2867 err = patch_generic_hdmi(codec);
2868 if (err)
2869 return err;
2870
2871 spec = codec->spec;
2872 spec->dyn_pin_out = true;
2873
2874 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
2875 nvhdmi_chmap_cea_alloc_validate_get_type;
2876 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
2877
2878 return 0;
2879 }
2880
2881 /*
2882 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2883 * accessed using vendor-defined verbs. These registers can be used for
2884 * interoperability between the HDA and HDMI drivers.
2885 */
2886
2887 /* Audio Function Group node */
2888 #define NVIDIA_AFG_NID 0x01
2889
2890 /*
2891 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2892 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2893 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2894 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2895 * additional bit (at position 30) to signal the validity of the format.
2896 *
2897 * | 31 | 30 | 29 16 | 15 0 |
2898 * +---------+-------+--------+--------+
2899 * | TRIGGER | VALID | UNUSED | FORMAT |
2900 * +-----------------------------------|
2901 *
2902 * Note that for the trigger bit to take effect it needs to change value
2903 * (i.e. it needs to be toggled).
2904 */
2905 #define NVIDIA_GET_SCRATCH0 0xfa6
2906 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
2907 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
2908 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
2909 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
2910 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2911 #define NVIDIA_SCRATCH_VALID (1 << 6)
2912
2913 #define NVIDIA_GET_SCRATCH1 0xfab
2914 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
2915 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
2916 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
2917 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
2918
2919 /*
2920 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2921 * the format is invalidated so that the HDMI codec can be disabled.
2922 */
2923 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
2924 {
2925 unsigned int value;
2926
2927 /* bits [31:30] contain the trigger and valid bits */
2928 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
2929 NVIDIA_GET_SCRATCH0, 0);
2930 value = (value >> 24) & 0xff;
2931
2932 /* bits [15:0] are used to store the HDA format */
2933 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2934 NVIDIA_SET_SCRATCH0_BYTE0,
2935 (format >> 0) & 0xff);
2936 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2937 NVIDIA_SET_SCRATCH0_BYTE1,
2938 (format >> 8) & 0xff);
2939
2940 /* bits [16:24] are unused */
2941 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2942 NVIDIA_SET_SCRATCH0_BYTE2, 0);
2943
2944 /*
2945 * Bit 30 signals that the data is valid and hence that HDMI audio can
2946 * be enabled.
2947 */
2948 if (format == 0)
2949 value &= ~NVIDIA_SCRATCH_VALID;
2950 else
2951 value |= NVIDIA_SCRATCH_VALID;
2952
2953 /*
2954 * Whenever the trigger bit is toggled, an interrupt is raised in the
2955 * HDMI codec. The HDMI driver will use that as trigger to update its
2956 * configuration.
2957 */
2958 value ^= NVIDIA_SCRATCH_TRIGGER;
2959
2960 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2961 NVIDIA_SET_SCRATCH0_BYTE3, value);
2962 }
2963
2964 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
2965 struct hda_codec *codec,
2966 unsigned int stream_tag,
2967 unsigned int format,
2968 struct snd_pcm_substream *substream)
2969 {
2970 int err;
2971
2972 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
2973 format, substream);
2974 if (err < 0)
2975 return err;
2976
2977 /* notify the HDMI codec of the format change */
2978 tegra_hdmi_set_format(codec, format);
2979
2980 return 0;
2981 }
2982
2983 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
2984 struct hda_codec *codec,
2985 struct snd_pcm_substream *substream)
2986 {
2987 /* invalidate the format in the HDMI codec */
2988 tegra_hdmi_set_format(codec, 0);
2989
2990 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
2991 }
2992
2993 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
2994 {
2995 struct hdmi_spec *spec = codec->spec;
2996 unsigned int i;
2997
2998 for (i = 0; i < spec->num_pins; i++) {
2999 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3000
3001 if (pcm->pcm_type == type)
3002 return pcm;
3003 }
3004
3005 return NULL;
3006 }
3007
3008 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3009 {
3010 struct hda_pcm_stream *stream;
3011 struct hda_pcm *pcm;
3012 int err;
3013
3014 err = generic_hdmi_build_pcms(codec);
3015 if (err < 0)
3016 return err;
3017
3018 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3019 if (!pcm)
3020 return -ENODEV;
3021
3022 /*
3023 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3024 * codec about format changes.
3025 */
3026 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3027 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3028 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3029
3030 return 0;
3031 }
3032
3033 static int patch_tegra_hdmi(struct hda_codec *codec)
3034 {
3035 int err;
3036
3037 err = patch_generic_hdmi(codec);
3038 if (err)
3039 return err;
3040
3041 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3042
3043 return 0;
3044 }
3045
3046 /*
3047 * ATI/AMD-specific implementations
3048 */
3049
3050 #define is_amdhdmi_rev3_or_later(codec) \
3051 ((codec)->core.vendor_id == 0x1002aa01 && \
3052 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3053 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3054
3055 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3056 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3057 #define ATI_VERB_SET_DOWNMIX_INFO 0x772
3058 #define ATI_VERB_SET_MULTICHANNEL_01 0x777
3059 #define ATI_VERB_SET_MULTICHANNEL_23 0x778
3060 #define ATI_VERB_SET_MULTICHANNEL_45 0x779
3061 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3062 #define ATI_VERB_SET_HBR_CONTROL 0x77c
3063 #define ATI_VERB_SET_MULTICHANNEL_1 0x785
3064 #define ATI_VERB_SET_MULTICHANNEL_3 0x786
3065 #define ATI_VERB_SET_MULTICHANNEL_5 0x787
3066 #define ATI_VERB_SET_MULTICHANNEL_7 0x788
3067 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3068 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3069 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3070 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3071 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3072 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3073 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3074 #define ATI_VERB_GET_HBR_CONTROL 0xf7c
3075 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3076 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3077 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3078 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3079 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3080
3081 /* AMD specific HDA cvt verbs */
3082 #define ATI_VERB_SET_RAMP_RATE 0x770
3083 #define ATI_VERB_GET_RAMP_RATE 0xf70
3084
3085 #define ATI_OUT_ENABLE 0x1
3086
3087 #define ATI_MULTICHANNEL_MODE_PAIRED 0
3088 #define ATI_MULTICHANNEL_MODE_SINGLE 1
3089
3090 #define ATI_HBR_CAPABLE 0x01
3091 #define ATI_HBR_ENABLE 0x10
3092
3093 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3094 unsigned char *buf, int *eld_size)
3095 {
3096 /* call hda_eld.c ATI/AMD-specific function */
3097 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3098 is_amdhdmi_rev3_or_later(codec));
3099 }
3100
3101 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3102 int active_channels, int conn_type)
3103 {
3104 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3105 }
3106
3107 static int atihdmi_paired_swap_fc_lfe(int pos)
3108 {
3109 /*
3110 * ATI/AMD have automatic FC/LFE swap built-in
3111 * when in pairwise mapping mode.
3112 */
3113
3114 switch (pos) {
3115 /* see channel_allocations[].speakers[] */
3116 case 2: return 3;
3117 case 3: return 2;
3118 default: break;
3119 }
3120
3121 return pos;
3122 }
3123
3124 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3125 int ca, int chs, unsigned char *map)
3126 {
3127 struct hdac_cea_channel_speaker_allocation *cap;
3128 int i, j;
3129
3130 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3131
3132 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3133 for (i = 0; i < chs; ++i) {
3134 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3135 bool ok = false;
3136 bool companion_ok = false;
3137
3138 if (!mask)
3139 continue;
3140
3141 for (j = 0 + i % 2; j < 8; j += 2) {
3142 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3143 if (cap->speakers[chan_idx] == mask) {
3144 /* channel is in a supported position */
3145 ok = true;
3146
3147 if (i % 2 == 0 && i + 1 < chs) {
3148 /* even channel, check the odd companion */
3149 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3150 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3151 int comp_mask_act = cap->speakers[comp_chan_idx];
3152
3153 if (comp_mask_req == comp_mask_act)
3154 companion_ok = true;
3155 else
3156 return -EINVAL;
3157 }
3158 break;
3159 }
3160 }
3161
3162 if (!ok)
3163 return -EINVAL;
3164
3165 if (companion_ok)
3166 i++; /* companion channel already checked */
3167 }
3168
3169 return 0;
3170 }
3171
3172 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3173 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3174 {
3175 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3176 int verb;
3177 int ati_channel_setup = 0;
3178
3179 if (hdmi_slot > 7)
3180 return -EINVAL;
3181
3182 if (!has_amd_full_remap_support(codec)) {
3183 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3184
3185 /* In case this is an odd slot but without stream channel, do not
3186 * disable the slot since the corresponding even slot could have a
3187 * channel. In case neither have a channel, the slot pair will be
3188 * disabled when this function is called for the even slot. */
3189 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3190 return 0;
3191
3192 hdmi_slot -= hdmi_slot % 2;
3193
3194 if (stream_channel != 0xf)
3195 stream_channel -= stream_channel % 2;
3196 }
3197
3198 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3199
3200 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3201
3202 if (stream_channel != 0xf)
3203 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3204
3205 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3206 }
3207
3208 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3209 hda_nid_t pin_nid, int asp_slot)
3210 {
3211 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3212 bool was_odd = false;
3213 int ati_asp_slot = asp_slot;
3214 int verb;
3215 int ati_channel_setup;
3216
3217 if (asp_slot > 7)
3218 return -EINVAL;
3219
3220 if (!has_amd_full_remap_support(codec)) {
3221 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3222 if (ati_asp_slot % 2 != 0) {
3223 ati_asp_slot -= 1;
3224 was_odd = true;
3225 }
3226 }
3227
3228 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3229
3230 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3231
3232 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3233 return 0xf;
3234
3235 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3236 }
3237
3238 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3239 struct hdac_chmap *chmap,
3240 struct hdac_cea_channel_speaker_allocation *cap,
3241 int channels)
3242 {
3243 int c;
3244
3245 /*
3246 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3247 * we need to take that into account (a single channel may take 2
3248 * channel slots if we need to carry a silent channel next to it).
3249 * On Rev3+ AMD codecs this function is not used.
3250 */
3251 int chanpairs = 0;
3252
3253 /* We only produce even-numbered channel count TLVs */
3254 if ((channels % 2) != 0)
3255 return -1;
3256
3257 for (c = 0; c < 7; c += 2) {
3258 if (cap->speakers[c] || cap->speakers[c+1])
3259 chanpairs++;
3260 }
3261
3262 if (chanpairs * 2 != channels)
3263 return -1;
3264
3265 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3266 }
3267
3268 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3269 struct hdac_cea_channel_speaker_allocation *cap,
3270 unsigned int *chmap, int channels)
3271 {
3272 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3273 int count = 0;
3274 int c;
3275
3276 for (c = 7; c >= 0; c--) {
3277 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3278 int spk = cap->speakers[chan];
3279 if (!spk) {
3280 /* add N/A channel if the companion channel is occupied */
3281 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3282 chmap[count++] = SNDRV_CHMAP_NA;
3283
3284 continue;
3285 }
3286
3287 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3288 }
3289
3290 WARN_ON(count != channels);
3291 }
3292
3293 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3294 bool hbr)
3295 {
3296 int hbr_ctl, hbr_ctl_new;
3297
3298 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3299 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3300 if (hbr)
3301 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3302 else
3303 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3304
3305 codec_dbg(codec,
3306 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3307 pin_nid,
3308 hbr_ctl == hbr_ctl_new ? "" : "new-",
3309 hbr_ctl_new);
3310
3311 if (hbr_ctl != hbr_ctl_new)
3312 snd_hda_codec_write(codec, pin_nid, 0,
3313 ATI_VERB_SET_HBR_CONTROL,
3314 hbr_ctl_new);
3315
3316 } else if (hbr)
3317 return -EINVAL;
3318
3319 return 0;
3320 }
3321
3322 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3323 hda_nid_t pin_nid, u32 stream_tag, int format)
3324 {
3325
3326 if (is_amdhdmi_rev3_or_later(codec)) {
3327 int ramp_rate = 180; /* default as per AMD spec */
3328 /* disable ramp-up/down for non-pcm as per AMD spec */
3329 if (format & AC_FMT_TYPE_NON_PCM)
3330 ramp_rate = 0;
3331
3332 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3333 }
3334
3335 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3336 }
3337
3338
3339 static int atihdmi_init(struct hda_codec *codec)
3340 {
3341 struct hdmi_spec *spec = codec->spec;
3342 int pin_idx, err;
3343
3344 err = generic_hdmi_init(codec);
3345
3346 if (err)
3347 return err;
3348
3349 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3350 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3351
3352 /* make sure downmix information in infoframe is zero */
3353 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3354
3355 /* enable channel-wise remap mode if supported */
3356 if (has_amd_full_remap_support(codec))
3357 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3358 ATI_VERB_SET_MULTICHANNEL_MODE,
3359 ATI_MULTICHANNEL_MODE_SINGLE);
3360 }
3361
3362 return 0;
3363 }
3364
3365 static int patch_atihdmi(struct hda_codec *codec)
3366 {
3367 struct hdmi_spec *spec;
3368 struct hdmi_spec_per_cvt *per_cvt;
3369 int err, cvt_idx;
3370
3371 err = patch_generic_hdmi(codec);
3372
3373 if (err)
3374 return err;
3375
3376 codec->patch_ops.init = atihdmi_init;
3377
3378 spec = codec->spec;
3379
3380 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3381 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3382 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3383 spec->ops.setup_stream = atihdmi_setup_stream;
3384
3385 if (!has_amd_full_remap_support(codec)) {
3386 /* override to ATI/AMD-specific versions with pairwise mapping */
3387 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3388 atihdmi_paired_chmap_cea_alloc_validate_get_type;
3389 spec->chmap.ops.cea_alloc_to_tlv_chmap =
3390 atihdmi_paired_cea_alloc_to_tlv_chmap;
3391 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
3392 spec->chmap.ops.pin_get_slot_channel =
3393 atihdmi_pin_get_slot_channel;
3394 spec->chmap.ops.pin_set_slot_channel =
3395 atihdmi_pin_set_slot_channel;
3396 }
3397
3398 /* ATI/AMD converters do not advertise all of their capabilities */
3399 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3400 per_cvt = get_cvt(spec, cvt_idx);
3401 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3402 per_cvt->rates |= SUPPORTED_RATES;
3403 per_cvt->formats |= SUPPORTED_FORMATS;
3404 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3405 }
3406
3407 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
3408
3409 return 0;
3410 }
3411
3412 /* VIA HDMI Implementation */
3413 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
3414 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
3415
3416 static int patch_via_hdmi(struct hda_codec *codec)
3417 {
3418 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3419 }
3420
3421 /*
3422 * patch entries
3423 */
3424 static const struct hda_device_id snd_hda_id_hdmi[] = {
3425 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
3426 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
3427 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
3428 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
3429 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
3430 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
3431 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
3432 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3433 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3434 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3435 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
3436 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
3437 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
3438 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
3439 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
3440 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
3441 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
3442 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
3443 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
3444 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
3445 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
3446 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
3447 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
3448 /* 17 is known to be absent */
3449 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
3450 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
3451 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
3452 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
3453 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
3454 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
3455 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
3456 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
3457 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
3458 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
3459 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
3460 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
3461 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
3462 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
3463 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
3464 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
3465 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
3466 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
3467 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
3468 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
3469 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
3470 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
3471 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
3472 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
3473 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
3474 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
3475 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
3476 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
3477 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
3478 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
3479 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
3480 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
3481 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
3482 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
3483 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
3484 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
3485 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
3486 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
3487 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
3488 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
3489 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
3490 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
3491 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
3492 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
3493 /* special ID for generic HDMI */
3494 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
3495 {} /* terminator */
3496 };
3497 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
3498
3499 MODULE_LICENSE("GPL");
3500 MODULE_DESCRIPTION("HDMI HD-audio codec");
3501 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3502 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3503 MODULE_ALIAS("snd-hda-codec-atihdmi");
3504
3505 static struct hda_codec_driver hdmi_driver = {
3506 .id = snd_hda_id_hdmi,
3507 };
3508
3509 module_hda_codec_driver(hdmi_driver);
CRIS linux kernel tree