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frv: Select GENERIC_HARDIRQS_NO_DEPRECATED
[cris-mirror.git] / arch / arm / plat-nomadik / gpio.c
blob80643bc38e10deb1695d210d9ec29bab823275ab
1 /*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/platform_device.h>
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/slab.h>
25
26 #include <plat/pincfg.h>
27 #include <mach/hardware.h>
28 #include <mach/gpio.h>
29
30 /*
31 * The GPIO module in the Nomadik family of Systems-on-Chip is an
32 * AMBA device, managing 32 pins and alternate functions. The logic block
33 * is currently used in the Nomadik and ux500.
34 *
35 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
36 */
37
38 #define NMK_GPIO_PER_CHIP 32
39
40 struct nmk_gpio_chip {
41 struct gpio_chip chip;
42 void __iomem *addr;
43 struct clk *clk;
44 unsigned int bank;
45 unsigned int parent_irq;
46 int secondary_parent_irq;
47 u32 (*get_secondary_status)(unsigned int bank);
48 void (*set_ioforce)(bool enable);
49 spinlock_t lock;
50 /* Keep track of configured edges */
51 u32 edge_rising;
52 u32 edge_falling;
53 u32 real_wake;
54 u32 rwimsc;
55 u32 fwimsc;
56 u32 slpm;
57 };
58
59 static struct nmk_gpio_chip *
60 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
61
62 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
63
64 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
65
66 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
67 unsigned offset, int gpio_mode)
68 {
69 u32 bit = 1 << offset;
70 u32 afunc, bfunc;
71
72 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
73 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
74 if (gpio_mode & NMK_GPIO_ALT_A)
75 afunc |= bit;
76 if (gpio_mode & NMK_GPIO_ALT_B)
77 bfunc |= bit;
78 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
79 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
80 }
81
82 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
83 unsigned offset, enum nmk_gpio_slpm mode)
84 {
85 u32 bit = 1 << offset;
86 u32 slpm;
87
88 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
89 if (mode == NMK_GPIO_SLPM_NOCHANGE)
90 slpm |= bit;
91 else
92 slpm &= ~bit;
93 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
94 }
95
96 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
97 unsigned offset, enum nmk_gpio_pull pull)
98 {
99 u32 bit = 1 << offset;
100 u32 pdis;
101
102 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
103 if (pull == NMK_GPIO_PULL_NONE)
104 pdis |= bit;
105 else
106 pdis &= ~bit;
107 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
108
109 if (pull == NMK_GPIO_PULL_UP)
110 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
111 else if (pull == NMK_GPIO_PULL_DOWN)
112 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
113 }
114
115 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
116 unsigned offset)
117 {
118 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
119 }
120
121 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
122 unsigned offset, int val)
123 {
124 if (val)
125 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
126 else
127 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
128 }
129
130 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
131 unsigned offset, int val)
132 {
133 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
134 __nmk_gpio_set_output(nmk_chip, offset, val);
135 }
136
137 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
138 unsigned offset, int gpio_mode,
139 bool glitch)
140 {
141 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
142 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
143
144 if (glitch && nmk_chip->set_ioforce) {
145 u32 bit = BIT(offset);
146
147 /* Prevent spurious wakeups */
148 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
149 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
150
151 nmk_chip->set_ioforce(true);
152 }
153
154 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
155
156 if (glitch && nmk_chip->set_ioforce) {
157 nmk_chip->set_ioforce(false);
158
159 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
160 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
161 }
162 }
163
164 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
165 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
166 {
167 static const char *afnames[] = {
168 [NMK_GPIO_ALT_GPIO] = "GPIO",
169 [NMK_GPIO_ALT_A] = "A",
170 [NMK_GPIO_ALT_B] = "B",
171 [NMK_GPIO_ALT_C] = "C"
172 };
173 static const char *pullnames[] = {
174 [NMK_GPIO_PULL_NONE] = "none",
175 [NMK_GPIO_PULL_UP] = "up",
176 [NMK_GPIO_PULL_DOWN] = "down",
177 [3] /* illegal */ = "??"
178 };
179 static const char *slpmnames[] = {
180 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
181 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
182 };
183
184 int pin = PIN_NUM(cfg);
185 int pull = PIN_PULL(cfg);
186 int af = PIN_ALT(cfg);
187 int slpm = PIN_SLPM(cfg);
188 int output = PIN_DIR(cfg);
189 int val = PIN_VAL(cfg);
190 bool glitch = af == NMK_GPIO_ALT_C;
191
192 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
193 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
194 output ? "output " : "input",
195 output ? (val ? "high" : "low") : "");
196
197 if (sleep) {
198 int slpm_pull = PIN_SLPM_PULL(cfg);
199 int slpm_output = PIN_SLPM_DIR(cfg);
200 int slpm_val = PIN_SLPM_VAL(cfg);
201
202 af = NMK_GPIO_ALT_GPIO;
203
204 /*
205 * The SLPM_* values are normal values + 1 to allow zero to
206 * mean "same as normal".
207 */
208 if (slpm_pull)
209 pull = slpm_pull - 1;
210 if (slpm_output)
211 output = slpm_output - 1;
212 if (slpm_val)
213 val = slpm_val - 1;
214
215 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
216 pin,
217 slpm_pull ? pullnames[pull] : "same",
218 slpm_output ? (output ? "output" : "input") : "same",
219 slpm_val ? (val ? "high" : "low") : "same");
220 }
221
222 if (output)
223 __nmk_gpio_make_output(nmk_chip, offset, val);
224 else {
225 __nmk_gpio_make_input(nmk_chip, offset);
226 __nmk_gpio_set_pull(nmk_chip, offset, pull);
227 }
228
229 /*
230 * If we've backed up the SLPM registers (glitch workaround), modify
231 * the backups since they will be restored.
232 */
233 if (slpmregs) {
234 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
235 slpmregs[nmk_chip->bank] |= BIT(offset);
236 else
237 slpmregs[nmk_chip->bank] &= ~BIT(offset);
238 } else
239 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
240
241 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
242 }
243
244 /*
245 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
246 * - Save SLPM registers
247 * - Set SLPM=0 for the IOs you want to switch and others to 1
248 * - Configure the GPIO registers for the IOs that are being switched
249 * - Set IOFORCE=1
250 * - Modify the AFLSA/B registers for the IOs that are being switched
251 * - Set IOFORCE=0
252 * - Restore SLPM registers
253 * - Any spurious wake up event during switch sequence to be ignored and
254 * cleared
255 */
256 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
257 {
258 int i;
259
260 for (i = 0; i < NUM_BANKS; i++) {
261 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
262 unsigned int temp = slpm[i];
263
264 if (!chip)
265 break;
266
267 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
268 writel(temp, chip->addr + NMK_GPIO_SLPC);
269 }
270 }
271
272 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
273 {
274 int i;
275
276 for (i = 0; i < NUM_BANKS; i++) {
277 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
278
279 if (!chip)
280 break;
281
282 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
283 }
284 }
285
286 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
287 {
288 static unsigned int slpm[NUM_BANKS];
289 unsigned long flags;
290 bool glitch = false;
291 int ret = 0;
292 int i;
293
294 for (i = 0; i < num; i++) {
295 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
296 glitch = true;
297 break;
298 }
299 }
300
301 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
302
303 if (glitch) {
304 memset(slpm, 0xff, sizeof(slpm));
305
306 for (i = 0; i < num; i++) {
307 int pin = PIN_NUM(cfgs[i]);
308 int offset = pin % NMK_GPIO_PER_CHIP;
309
310 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
311 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
312 }
313
314 nmk_gpio_glitch_slpm_init(slpm);
315 }
316
317 for (i = 0; i < num; i++) {
318 struct nmk_gpio_chip *nmk_chip;
319 int pin = PIN_NUM(cfgs[i]);
320
321 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
322 if (!nmk_chip) {
323 ret = -EINVAL;
324 break;
325 }
326
327 spin_lock(&nmk_chip->lock);
328 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
329 cfgs[i], sleep, glitch ? slpm : NULL);
330 spin_unlock(&nmk_chip->lock);
331 }
332
333 if (glitch)
334 nmk_gpio_glitch_slpm_restore(slpm);
335
336 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
337
338 return ret;
339 }
340
341 /**
342 * nmk_config_pin - configure a pin's mux attributes
343 * @cfg: pin confguration
344 *
345 * Configures a pin's mode (alternate function or GPIO), its pull up status,
346 * and its sleep mode based on the specified configuration. The @cfg is
347 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
348 * are constructed using, and can be further enhanced with, the macros in
349 * plat/pincfg.h.
350 *
351 * If a pin's mode is set to GPIO, it is configured as an input to avoid
352 * side-effects. The gpio can be manipulated later using standard GPIO API
353 * calls.
354 */
355 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
356 {
357 return __nmk_config_pins(&cfg, 1, sleep);
358 }
359 EXPORT_SYMBOL(nmk_config_pin);
360
361 /**
362 * nmk_config_pins - configure several pins at once
363 * @cfgs: array of pin configurations
364 * @num: number of elments in the array
365 *
366 * Configures several pins using nmk_config_pin(). Refer to that function for
367 * further information.
368 */
369 int nmk_config_pins(pin_cfg_t *cfgs, int num)
370 {
371 return __nmk_config_pins(cfgs, num, false);
372 }
373 EXPORT_SYMBOL(nmk_config_pins);
374
375 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
376 {
377 return __nmk_config_pins(cfgs, num, true);
378 }
379 EXPORT_SYMBOL(nmk_config_pins_sleep);
380
381 /**
382 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
383 * @gpio: pin number
384 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
385 *
386 * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is
387 * changed to an input (with pullup/down enabled) in sleep and deep sleep. If
388 * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
389 * configured even when in sleep and deep sleep.
390 *
391 * On DB8500v2 onwards, this setting loses the previous meaning and instead
392 * indicates if wakeup detection is enabled on the pin. Note that
393 * enable_irq_wake() will automatically enable wakeup detection.
394 */
395 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
396 {
397 struct nmk_gpio_chip *nmk_chip;
398 unsigned long flags;
399
400 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
401 if (!nmk_chip)
402 return -EINVAL;
403
404 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
405 spin_lock(&nmk_chip->lock);
406
407 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
408
409 spin_unlock(&nmk_chip->lock);
410 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
411
412 return 0;
413 }
414
415 /**
416 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
417 * @gpio: pin number
418 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
419 *
420 * Enables/disables pull up/down on a specified pin. This only takes effect if
421 * the pin is configured as an input (either explicitly or by the alternate
422 * function).
423 *
424 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
425 * configured as an input. Otherwise, due to the way the controller registers
426 * work, this function will change the value output on the pin.
427 */
428 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
429 {
430 struct nmk_gpio_chip *nmk_chip;
431 unsigned long flags;
432
433 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
434 if (!nmk_chip)
435 return -EINVAL;
436
437 spin_lock_irqsave(&nmk_chip->lock, flags);
438 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
439 spin_unlock_irqrestore(&nmk_chip->lock, flags);
440
441 return 0;
442 }
443
444 /* Mode functions */
445 /**
446 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
447 * @gpio: pin number
448 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
449 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
450 *
451 * Sets the mode of the specified pin to one of the alternate functions or
452 * plain GPIO.
453 */
454 int nmk_gpio_set_mode(int gpio, int gpio_mode)
455 {
456 struct nmk_gpio_chip *nmk_chip;
457 unsigned long flags;
458
459 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
460 if (!nmk_chip)
461 return -EINVAL;
462
463 spin_lock_irqsave(&nmk_chip->lock, flags);
464 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
465 spin_unlock_irqrestore(&nmk_chip->lock, flags);
466
467 return 0;
468 }
469 EXPORT_SYMBOL(nmk_gpio_set_mode);
470
471 int nmk_gpio_get_mode(int gpio)
472 {
473 struct nmk_gpio_chip *nmk_chip;
474 u32 afunc, bfunc, bit;
475
476 nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
477 if (!nmk_chip)
478 return -EINVAL;
479
480 bit = 1 << (gpio - nmk_chip->chip.base);
481
482 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
483 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
484
485 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
486 }
487 EXPORT_SYMBOL(nmk_gpio_get_mode);
488
489
490 /* IRQ functions */
491 static inline int nmk_gpio_get_bitmask(int gpio)
492 {
493 return 1 << (gpio % 32);
494 }
495
496 static void nmk_gpio_irq_ack(struct irq_data *d)
497 {
498 int gpio;
499 struct nmk_gpio_chip *nmk_chip;
500
501 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
502 nmk_chip = irq_data_get_irq_chip_data(d);
503 if (!nmk_chip)
504 return;
505 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
506 }
507
508 enum nmk_gpio_irq_type {
509 NORMAL,
510 WAKE,
511 };
512
513 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
514 int gpio, enum nmk_gpio_irq_type which,
515 bool enable)
516 {
517 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
518 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
519 u32 bitmask = nmk_gpio_get_bitmask(gpio);
520 u32 reg;
521
522 /* we must individually set/clear the two edges */
523 if (nmk_chip->edge_rising & bitmask) {
524 reg = readl(nmk_chip->addr + rimsc);
525 if (enable)
526 reg |= bitmask;
527 else
528 reg &= ~bitmask;
529 writel(reg, nmk_chip->addr + rimsc);
530 }
531 if (nmk_chip->edge_falling & bitmask) {
532 reg = readl(nmk_chip->addr + fimsc);
533 if (enable)
534 reg |= bitmask;
535 else
536 reg &= ~bitmask;
537 writel(reg, nmk_chip->addr + fimsc);
538 }
539 }
540
541 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
542 int gpio, bool on)
543 {
544 #ifdef CONFIG_ARCH_U8500
545 if (cpu_is_u8500v2()) {
546 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
547 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
548 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
549 }
550 #endif
551 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
552 }
553
554 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
555 {
556 int gpio;
557 struct nmk_gpio_chip *nmk_chip;
558 unsigned long flags;
559 u32 bitmask;
560
561 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
562 nmk_chip = irq_data_get_irq_chip_data(d);
563 bitmask = nmk_gpio_get_bitmask(gpio);
564 if (!nmk_chip)
565 return -EINVAL;
566
567 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
568 spin_lock(&nmk_chip->lock);
569
570 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
571
572 if (!(nmk_chip->real_wake & bitmask))
573 __nmk_gpio_set_wake(nmk_chip, gpio, enable);
574
575 spin_unlock(&nmk_chip->lock);
576 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
577
578 return 0;
579 }
580
581 static void nmk_gpio_irq_mask(struct irq_data *d)
582 {
583 nmk_gpio_irq_maskunmask(d, false);
584 }
585
586 static void nmk_gpio_irq_unmask(struct irq_data *d)
587 {
588 nmk_gpio_irq_maskunmask(d, true);
589 }
590
591 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
592 {
593 struct irq_desc *desc = irq_to_desc(d->irq);
594 bool enabled = !(desc->status & IRQ_DISABLED);
595 struct nmk_gpio_chip *nmk_chip;
596 unsigned long flags;
597 u32 bitmask;
598 int gpio;
599
600 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
601 nmk_chip = irq_data_get_irq_chip_data(d);
602 if (!nmk_chip)
603 return -EINVAL;
604 bitmask = nmk_gpio_get_bitmask(gpio);
605
606 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
607 spin_lock(&nmk_chip->lock);
608
609 if (!enabled)
610 __nmk_gpio_set_wake(nmk_chip, gpio, on);
611
612 if (on)
613 nmk_chip->real_wake |= bitmask;
614 else
615 nmk_chip->real_wake &= ~bitmask;
616
617 spin_unlock(&nmk_chip->lock);
618 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
619
620 return 0;
621 }
622
623 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
624 {
625 struct irq_desc *desc = irq_to_desc(d->irq);
626 bool enabled = !(desc->status & IRQ_DISABLED);
627 bool wake = desc->wake_depth;
628 int gpio;
629 struct nmk_gpio_chip *nmk_chip;
630 unsigned long flags;
631 u32 bitmask;
632
633 gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
634 nmk_chip = irq_data_get_irq_chip_data(d);
635 bitmask = nmk_gpio_get_bitmask(gpio);
636 if (!nmk_chip)
637 return -EINVAL;
638
639 if (type & IRQ_TYPE_LEVEL_HIGH)
640 return -EINVAL;
641 if (type & IRQ_TYPE_LEVEL_LOW)
642 return -EINVAL;
643
644 spin_lock_irqsave(&nmk_chip->lock, flags);
645
646 if (enabled)
647 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
648
649 if (enabled || wake)
650 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
651
652 nmk_chip->edge_rising &= ~bitmask;
653 if (type & IRQ_TYPE_EDGE_RISING)
654 nmk_chip->edge_rising |= bitmask;
655
656 nmk_chip->edge_falling &= ~bitmask;
657 if (type & IRQ_TYPE_EDGE_FALLING)
658 nmk_chip->edge_falling |= bitmask;
659
660 if (enabled)
661 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
662
663 if (enabled || wake)
664 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
665
666 spin_unlock_irqrestore(&nmk_chip->lock, flags);
667
668 return 0;
669 }
670
671 static struct irq_chip nmk_gpio_irq_chip = {
672 .name = "Nomadik-GPIO",
673 .irq_ack = nmk_gpio_irq_ack,
674 .irq_mask = nmk_gpio_irq_mask,
675 .irq_unmask = nmk_gpio_irq_unmask,
676 .irq_set_type = nmk_gpio_irq_set_type,
677 .irq_set_wake = nmk_gpio_irq_set_wake,
678 };
679
680 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
681 u32 status)
682 {
683 struct nmk_gpio_chip *nmk_chip;
684 struct irq_chip *host_chip = get_irq_chip(irq);
685 unsigned int first_irq;
686
687 if (host_chip->irq_mask_ack)
688 host_chip->irq_mask_ack(&desc->irq_data);
689 else {
690 host_chip->irq_mask(&desc->irq_data);
691 if (host_chip->irq_ack)
692 host_chip->irq_ack(&desc->irq_data);
693 }
694
695 nmk_chip = get_irq_data(irq);
696 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
697 while (status) {
698 int bit = __ffs(status);
699
700 generic_handle_irq(first_irq + bit);
701 status &= ~BIT(bit);
702 }
703
704 host_chip->irq_unmask(&desc->irq_data);
705 }
706
707 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
708 {
709 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
710 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
711
712 __nmk_gpio_irq_handler(irq, desc, status);
713 }
714
715 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
716 struct irq_desc *desc)
717 {
718 struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
719 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
720
721 __nmk_gpio_irq_handler(irq, desc, status);
722 }
723
724 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
725 {
726 unsigned int first_irq;
727 int i;
728
729 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
730 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
731 set_irq_chip(i, &nmk_gpio_irq_chip);
732 set_irq_handler(i, handle_edge_irq);
733 set_irq_flags(i, IRQF_VALID);
734 set_irq_chip_data(i, nmk_chip);
735 set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
736 }
737
738 set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
739 set_irq_data(nmk_chip->parent_irq, nmk_chip);
740
741 if (nmk_chip->secondary_parent_irq >= 0) {
742 set_irq_chained_handler(nmk_chip->secondary_parent_irq,
743 nmk_gpio_secondary_irq_handler);
744 set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
745 }
746
747 return 0;
748 }
749
750 /* I/O Functions */
751 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
752 {
753 struct nmk_gpio_chip *nmk_chip =
754 container_of(chip, struct nmk_gpio_chip, chip);
755
756 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
757 return 0;
758 }
759
760 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
761 {
762 struct nmk_gpio_chip *nmk_chip =
763 container_of(chip, struct nmk_gpio_chip, chip);
764 u32 bit = 1 << offset;
765
766 return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
767 }
768
769 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
770 int val)
771 {
772 struct nmk_gpio_chip *nmk_chip =
773 container_of(chip, struct nmk_gpio_chip, chip);
774
775 __nmk_gpio_set_output(nmk_chip, offset, val);
776 }
777
778 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
779 int val)
780 {
781 struct nmk_gpio_chip *nmk_chip =
782 container_of(chip, struct nmk_gpio_chip, chip);
783
784 __nmk_gpio_make_output(nmk_chip, offset, val);
785
786 return 0;
787 }
788
789 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
790 {
791 struct nmk_gpio_chip *nmk_chip =
792 container_of(chip, struct nmk_gpio_chip, chip);
793
794 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
795 }
796
797 #ifdef CONFIG_DEBUG_FS
798
799 #include <linux/seq_file.h>
800
801 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
802 {
803 int mode;
804 unsigned i;
805 unsigned gpio = chip->base;
806 int is_out;
807 struct nmk_gpio_chip *nmk_chip =
808 container_of(chip, struct nmk_gpio_chip, chip);
809 const char *modes[] = {
810 [NMK_GPIO_ALT_GPIO] = "gpio",
811 [NMK_GPIO_ALT_A] = "altA",
812 [NMK_GPIO_ALT_B] = "altB",
813 [NMK_GPIO_ALT_C] = "altC",
814 };
815
816 for (i = 0; i < chip->ngpio; i++, gpio++) {
817 const char *label = gpiochip_is_requested(chip, i);
818 bool pull;
819 u32 bit = 1 << i;
820
821 if (!label)
822 continue;
823
824 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
825 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
826 mode = nmk_gpio_get_mode(gpio);
827 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
828 gpio, label,
829 is_out ? "out" : "in ",
830 chip->get
831 ? (chip->get(chip, i) ? "hi" : "lo")
832 : "? ",
833 (mode < 0) ? "unknown" : modes[mode],
834 pull ? "pull" : "none");
835 seq_printf(s, "\n");
836 }
837 }
838
839 #else
840 #define nmk_gpio_dbg_show NULL
841 #endif
842
843 /* This structure is replicated for each GPIO block allocated at probe time */
844 static struct gpio_chip nmk_gpio_template = {
845 .direction_input = nmk_gpio_make_input,
846 .get = nmk_gpio_get_input,
847 .direction_output = nmk_gpio_make_output,
848 .set = nmk_gpio_set_output,
849 .to_irq = nmk_gpio_to_irq,
850 .dbg_show = nmk_gpio_dbg_show,
851 .can_sleep = 0,
852 };
853
854 /*
855 * Called from the suspend/resume path to only keep the real wakeup interrupts
856 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
857 * and not the rest of the interrupts which we needed to have as wakeups for
858 * cpuidle.
859 *
860 * PM ops are not used since this needs to be done at the end, after all the
861 * other drivers are done with their suspend callbacks.
862 */
863 void nmk_gpio_wakeups_suspend(void)
864 {
865 int i;
866
867 for (i = 0; i < NUM_BANKS; i++) {
868 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
869
870 if (!chip)
871 break;
872
873 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
874 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
875
876 writel(chip->rwimsc & chip->real_wake,
877 chip->addr + NMK_GPIO_RWIMSC);
878 writel(chip->fwimsc & chip->real_wake,
879 chip->addr + NMK_GPIO_FWIMSC);
880
881 if (cpu_is_u8500v2()) {
882 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
883
884 /* 0 -> wakeup enable */
885 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
886 }
887 }
888 }
889
890 void nmk_gpio_wakeups_resume(void)
891 {
892 int i;
893
894 for (i = 0; i < NUM_BANKS; i++) {
895 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
896
897 if (!chip)
898 break;
899
900 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
901 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
902
903 if (cpu_is_u8500v2())
904 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
905 }
906 }
907
908 static int __devinit nmk_gpio_probe(struct platform_device *dev)
909 {
910 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
911 struct nmk_gpio_chip *nmk_chip;
912 struct gpio_chip *chip;
913 struct resource *res;
914 struct clk *clk;
915 int secondary_irq;
916 int irq;
917 int ret;
918
919 if (!pdata)
920 return -ENODEV;
921
922 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
923 if (!res) {
924 ret = -ENOENT;
925 goto out;
926 }
927
928 irq = platform_get_irq(dev, 0);
929 if (irq < 0) {
930 ret = irq;
931 goto out;
932 }
933
934 secondary_irq = platform_get_irq(dev, 1);
935 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
936 ret = -EINVAL;
937 goto out;
938 }
939
940 if (request_mem_region(res->start, resource_size(res),
941 dev_name(&dev->dev)) == NULL) {
942 ret = -EBUSY;
943 goto out;
944 }
945
946 clk = clk_get(&dev->dev, NULL);
947 if (IS_ERR(clk)) {
948 ret = PTR_ERR(clk);
949 goto out_release;
950 }
951
952 clk_enable(clk);
953
954 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
955 if (!nmk_chip) {
956 ret = -ENOMEM;
957 goto out_clk;
958 }
959 /*
960 * The virt address in nmk_chip->addr is in the nomadik register space,
961 * so we can simply convert the resource address, without remapping
962 */
963 nmk_chip->bank = dev->id;
964 nmk_chip->clk = clk;
965 nmk_chip->addr = io_p2v(res->start);
966 nmk_chip->chip = nmk_gpio_template;
967 nmk_chip->parent_irq = irq;
968 nmk_chip->secondary_parent_irq = secondary_irq;
969 nmk_chip->get_secondary_status = pdata->get_secondary_status;
970 nmk_chip->set_ioforce = pdata->set_ioforce;
971 spin_lock_init(&nmk_chip->lock);
972
973 chip = &nmk_chip->chip;
974 chip->base = pdata->first_gpio;
975 chip->ngpio = pdata->num_gpio;
976 chip->label = pdata->name ?: dev_name(&dev->dev);
977 chip->dev = &dev->dev;
978 chip->owner = THIS_MODULE;
979
980 ret = gpiochip_add(&nmk_chip->chip);
981 if (ret)
982 goto out_free;
983
984 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
985
986 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
987 platform_set_drvdata(dev, nmk_chip);
988
989 nmk_gpio_init_irq(nmk_chip);
990
991 dev_info(&dev->dev, "Bits %i-%i at address %p\n",
992 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
993 return 0;
994
995 out_free:
996 kfree(nmk_chip);
997 out_clk:
998 clk_disable(clk);
999 clk_put(clk);
1000 out_release:
1001 release_mem_region(res->start, resource_size(res));
1002 out:
1003 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1004 pdata->first_gpio, pdata->first_gpio+31);
1005 return ret;
1006 }
1007
1008 static struct platform_driver nmk_gpio_driver = {
1009 .driver = {
1010 .owner = THIS_MODULE,
1011 .name = "gpio",
1012 },
1013 .probe = nmk_gpio_probe,
1014 };
1015
1016 static int __init nmk_gpio_init(void)
1017 {
1018 return platform_driver_register(&nmk_gpio_driver);
1019 }
1020
1021 core_initcall(nmk_gpio_init);
1022
1023 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1024 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1025 MODULE_LICENSE("GPL");
1026
1027
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