arch/arm/plat-nomadik/include/plat/ste_dma40.h

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2007-2010
   3  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
   4  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
   5  * License terms: GNU General Public License (GPL) version 2
   6  */
   7
   8
   9 #ifndef STE_DMA40_H
  10 #define STE_DMA40_H
  11
  12 #include <linux/dmaengine.h>
  13 #include <linux/workqueue.h>
  14 #include <linux/interrupt.h>
  15
  16 /*
  17  * Maxium size for a single dma descriptor
  18  * Size is limited to 16 bits.
  19  * Size is in the units of addr-widths (1,2,4,8 bytes)
  20  * Larger transfers will be split up to multiple linked desc
  21  */
  22 #define STEDMA40_MAX_SEG_SIZE 0xFFFF
  23
  24 /* dev types for memcpy */
  25 #define STEDMA40_DEV_DST_MEMORY (-1)
  26 #define STEDMA40_DEV_SRC_MEMORY (-1)
  27
  28 enum stedma40_mode {
  29         STEDMA40_MODE_LOGICAL = 0,
  30         STEDMA40_MODE_PHYSICAL,
  31         STEDMA40_MODE_OPERATION,
  32 };
  33
  34 enum stedma40_mode_opt {
  35         STEDMA40_PCHAN_BASIC_MODE = 0,
  36         STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
  37         STEDMA40_PCHAN_MODULO_MODE,
  38         STEDMA40_PCHAN_DOUBLE_DST_MODE,
  39         STEDMA40_LCHAN_SRC_PHY_DST_LOG,
  40         STEDMA40_LCHAN_SRC_LOG_DST_PHY,
  41 };
  42
  43 #define STEDMA40_ESIZE_8_BIT  0x0
  44 #define STEDMA40_ESIZE_16_BIT 0x1
  45 #define STEDMA40_ESIZE_32_BIT 0x2
  46 #define STEDMA40_ESIZE_64_BIT 0x3
  47
  48 /* The value 4 indicates that PEN-reg shall be set to 0 */
  49 #define STEDMA40_PSIZE_PHY_1  0x4
  50 #define STEDMA40_PSIZE_PHY_2  0x0
  51 #define STEDMA40_PSIZE_PHY_4  0x1
  52 #define STEDMA40_PSIZE_PHY_8  0x2
  53 #define STEDMA40_PSIZE_PHY_16 0x3
  54
  55 /*
  56  * The number of elements differ in logical and
  57  * physical mode
  58  */
  59 #define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
  60 #define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
  61 #define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
  62 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
  63
  64 /* Maximum number of possible physical channels */
  65 #define STEDMA40_MAX_PHYS 32
  66
  67 enum stedma40_flow_ctrl {
  68         STEDMA40_NO_FLOW_CTRL,
  69         STEDMA40_FLOW_CTRL,
  70 };
  71
  72 enum stedma40_periph_data_width {
  73         STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
  74         STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
  75         STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
  76         STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
  77 };
  78
  79 enum stedma40_xfer_dir {
  80         STEDMA40_MEM_TO_MEM = 1,
  81         STEDMA40_MEM_TO_PERIPH,
  82         STEDMA40_PERIPH_TO_MEM,
  83         STEDMA40_PERIPH_TO_PERIPH
  84 };
  85
  86
  87 /**
  88  * struct stedma40_chan_cfg - dst/src channel configuration
  89  *
  90  * @big_endian: true if the src/dst should be read as big endian
  91  * @data_width: Data width of the src/dst hardware
  92  * @p_size: Burst size
  93  * @flow_ctrl: Flow control on/off.
  94  */
  95 struct stedma40_half_channel_info {
  96         bool big_endian;
  97         enum stedma40_periph_data_width data_width;
  98         int psize;
  99         enum stedma40_flow_ctrl flow_ctrl;
 100 };
 101
 102 /**
 103  * struct stedma40_chan_cfg - Structure to be filled by client drivers.
 104  *
 105  * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
 106  * @high_priority: true if high-priority
 107  * @realtime: true if realtime mode is to be enabled.  Only available on DMA40
 108  * version 3+, i.e DB8500v2+
 109  * @mode: channel mode: physical, logical, or operation
 110  * @mode_opt: options for the chosen channel mode
 111  * @src_dev_type: Src device type
 112  * @dst_dev_type: Dst device type
 113  * @src_info: Parameters for dst half channel
 114  * @dst_info: Parameters for dst half channel
 115  *
 116  *
 117  * This structure has to be filled by the client drivers.
 118  * It is recommended to do all dma configurations for clients in the machine.
 119  *
 120  */
 121 struct stedma40_chan_cfg {
 122         enum stedma40_xfer_dir                   dir;
 123         bool                                     high_priority;
 124         bool                                     realtime;
 125         enum stedma40_mode                       mode;
 126         enum stedma40_mode_opt                   mode_opt;
 127         int                                      src_dev_type;
 128         int                                      dst_dev_type;
 129         struct stedma40_half_channel_info        src_info;
 130         struct stedma40_half_channel_info        dst_info;
 131 };
 132
 133 /**
 134  * struct stedma40_platform_data - Configuration struct for the dma device.
 135  *
 136  * @dev_len: length of dev_tx and dev_rx
 137  * @dev_tx: mapping between destination event line and io address
 138  * @dev_rx: mapping between source event line and io address
 139  * @memcpy: list of memcpy event lines
 140  * @memcpy_len: length of memcpy
 141  * @memcpy_conf_phy: default configuration of physical channel memcpy
 142  * @memcpy_conf_log: default configuration of logical channel memcpy
 143  * @disabled_channels: A vector, ending with -1, that marks physical channels
 144  * that are for different reasons not available for the driver.
 145  */
 146 struct stedma40_platform_data {
 147         u32                              dev_len;
 148         const dma_addr_t                *dev_tx;
 149         const dma_addr_t                *dev_rx;
 150         int                             *memcpy;
 151         u32                              memcpy_len;
 152         struct stedma40_chan_cfg        *memcpy_conf_phy;
 153         struct stedma40_chan_cfg        *memcpy_conf_log;
 154         int                              disabled_channels[STEDMA40_MAX_PHYS];
 155 };
 156
 157 #ifdef CONFIG_STE_DMA40
 158
 159 /**
 160  * stedma40_filter() - Provides stedma40_chan_cfg to the
 161  * ste_dma40 dma driver via the dmaengine framework.
 162  * does some checking of what's provided.
 163  *
 164  * Never directly called by client. It used by dmaengine.
 165  * @chan: dmaengine handle.
 166  * @data: Must be of type: struct stedma40_chan_cfg and is
 167  * the configuration of the framework.
 168  *
 169  *
 170  */
 171
 172 bool stedma40_filter(struct dma_chan *chan, void *data);
 173
 174 /**
 175  * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
 176  * (=device)
 177  *
 178  * @chan: dmaengine handle
 179  * @addr: source or destination physicall address.
 180  * @size: bytes to transfer
 181  * @direction: direction of transfer
 182  * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 183  */
 184
 185 static inline struct
 186 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
 187                                             dma_addr_t addr,
 188                                             unsigned int size,
 189                                             enum dma_data_direction direction,
 190                                             unsigned long flags)
 191 {
 192         struct scatterlist sg;
 193         sg_init_table(&sg, 1);
 194         sg.dma_address = addr;
 195         sg.length = size;
 196
 197         return chan->device->device_prep_slave_sg(chan, &sg, 1,
 198                                                   direction, flags);
 199 }
 200
 201 #else
 202 static inline bool stedma40_filter(struct dma_chan *chan, void *data)
 203 {
 204         return false;
 205 }
 206
 207 static inline struct
 208 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
 209                                             dma_addr_t addr,
 210                                             unsigned int size,
 211                                             enum dma_data_direction direction,
 212                                             unsigned long flags)
 213 {
 214         return NULL;
 215 }
 216 #endif
 217
 218 #endif