2 * Copyright (C) 1995 Linus Torvalds
3 * Copyright 2010 Tilera Corporation. All Rights Reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for
16 #include <linux/module.h>
17 #include <linux/signal.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/string.h>
22 #include <linux/types.h>
23 #include <linux/ptrace.h>
24 #include <linux/mman.h>
26 #include <linux/hugetlb.h>
27 #include <linux/swap.h>
28 #include <linux/smp.h>
29 #include <linux/init.h>
30 #include <linux/highmem.h>
31 #include <linux/pagemap.h>
32 #include <linux/poison.h>
33 #include <linux/bootmem.h>
34 #include <linux/slab.h>
35 #include <linux/proc_fs.h>
36 #include <linux/efi.h>
37 #include <linux/memory_hotplug.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/processor.h>
41 #include <asm/system.h>
42 #include <asm/pgtable.h>
43 #include <asm/pgalloc.h>
45 #include <asm/fixmap.h>
47 #include <asm/tlbflush.h>
48 #include <asm/sections.h>
49 #include <asm/setup.h>
50 #include <asm/homecache.h>
51 #include <hv/hypervisor.h>
52 #include <arch/chip.h>
56 #define clear_pgd(pmdptr) (*(pmdptr) = hv_pte(0))
59 unsigned long VMALLOC_RESERVE
= CONFIG_VMALLOC_RESERVE
;
60 EXPORT_SYMBOL(VMALLOC_RESERVE
);
63 DEFINE_PER_CPU(struct mmu_gather
, mmu_gathers
);
65 /* Create an L2 page table */
66 static pte_t
* __init
alloc_pte(void)
68 return __alloc_bootmem(L2_KERNEL_PGTABLE_SIZE
, HV_PAGE_TABLE_ALIGN
, 0);
72 * L2 page tables per controller. We allocate these all at once from
73 * the bootmem allocator and store them here. This saves on kernel L2
74 * page table memory, compared to allocating a full 64K page per L2
75 * page table, and also means that in cases where we use huge pages,
76 * we are guaranteed to later be able to shatter those huge pages and
77 * switch to using these page tables instead, without requiring
78 * further allocation. Each l2_ptes[] entry points to the first page
79 * table for the first hugepage-size piece of memory on the
80 * controller; other page tables are just indexed directly, i.e. the
81 * L2 page tables are contiguous in memory for each controller.
83 static pte_t
*l2_ptes
[MAX_NUMNODES
];
84 static int num_l2_ptes
[MAX_NUMNODES
];
86 static void init_prealloc_ptes(int node
, int pages
)
88 BUG_ON(pages
& (HV_L2_ENTRIES
-1));
90 num_l2_ptes
[node
] = pages
;
91 l2_ptes
[node
] = __alloc_bootmem(pages
* sizeof(pte_t
),
92 HV_PAGE_TABLE_ALIGN
, 0);
96 pte_t
*get_prealloc_pte(unsigned long pfn
)
98 int node
= pfn_to_nid(pfn
);
99 pfn
&= ~(-1UL << (NR_PA_HIGHBIT_SHIFT
- PAGE_SHIFT
));
100 BUG_ON(node
>= MAX_NUMNODES
);
101 BUG_ON(pfn
>= num_l2_ptes
[node
]);
102 return &l2_ptes
[node
][pfn
];
106 * What caching do we expect pages from the heap to have when
107 * they are allocated during bootup? (Once we've installed the
108 * "real" swapper_pg_dir.)
110 static int initial_heap_home(void)
112 #if CHIP_HAS_CBOX_HOME_MAP()
114 return PAGE_HOME_HASH
;
116 return smp_processor_id();
120 * Place a pointer to an L2 page table in a middle page
123 static void __init
assign_pte(pmd_t
*pmd
, pte_t
*page_table
)
125 phys_addr_t pa
= __pa(page_table
);
126 unsigned long l2_ptfn
= pa
>> HV_LOG2_PAGE_TABLE_ALIGN
;
127 pte_t pteval
= hv_pte_set_ptfn(__pgprot(_PAGE_TABLE
), l2_ptfn
);
128 BUG_ON((pa
& (HV_PAGE_TABLE_ALIGN
-1)) != 0);
129 pteval
= pte_set_home(pteval
, initial_heap_home());
130 *(pte_t
*)pmd
= pteval
;
131 if (page_table
!= (pte_t
*)pmd_page_vaddr(*pmd
))
137 #if HV_L1_SIZE != HV_L2_SIZE
138 # error Rework assumption that L1 and L2 page tables are same size.
141 /* Since pmd_t arrays and pte_t arrays are the same size, just use casts. */
142 static inline pmd_t
*alloc_pmd(void)
144 return (pmd_t
*)alloc_pte();
147 static inline void assign_pmd(pud_t
*pud
, pmd_t
*pmd
)
149 assign_pte((pmd_t
*)pud
, (pte_t
*)pmd
);
152 #endif /* __tilegx__ */
154 /* Replace the given pmd with a full PTE table. */
155 void __init
shatter_pmd(pmd_t
*pmd
)
157 pte_t
*pte
= get_prealloc_pte(pte_pfn(*(pte_t
*)pmd
));
158 assign_pte(pmd
, pte
);
161 #ifdef CONFIG_HIGHMEM
163 * This function initializes a certain range of kernel virtual memory
164 * with new bootmem page tables, everywhere page tables are missing in
169 * NOTE: The pagetables are allocated contiguous on the physical space
170 * so we can cache the place of the first one and move around without
171 * checking the pgd every time.
173 static void __init
page_table_range_init(unsigned long start
,
174 unsigned long end
, pgd_t
*pgd_base
)
181 pgd_idx
= pgd_index(vaddr
);
182 pgd
= pgd_base
+ pgd_idx
;
184 for ( ; (pgd_idx
< PTRS_PER_PGD
) && (vaddr
!= end
); pgd
++, pgd_idx
++) {
185 pmd_t
*pmd
= pmd_offset(pud_offset(pgd
, vaddr
), vaddr
);
187 assign_pte(pmd
, alloc_pte());
191 #endif /* CONFIG_HIGHMEM */
194 #if CHIP_HAS_CBOX_HOME_MAP()
196 static int __initdata ktext_hash
= 1; /* .text pages */
197 static int __initdata kdata_hash
= 1; /* .data and .bss pages */
198 int __write_once hash_default
= 1; /* kernel allocator pages */
199 EXPORT_SYMBOL(hash_default
);
200 int __write_once kstack_hash
= 1; /* if no homecaching, use h4h */
201 #endif /* CHIP_HAS_CBOX_HOME_MAP */
204 * CPUs to use to for striping the pages of kernel data. If hash-for-home
205 * is available, this is only relevant if kcache_hash sets up the
206 * .data and .bss to be page-homed, and we don't want the default mode
207 * of using the full set of kernel cpus for the striping.
209 static __initdata
struct cpumask kdata_mask
;
210 static __initdata
int kdata_arg_seen
;
212 int __write_once kdata_huge
; /* if no homecaching, small pages */
215 /* Combine a generic pgprot_t with cache home to get a cache-aware pgprot. */
216 static pgprot_t __init
construct_pgprot(pgprot_t prot
, int home
)
218 prot
= pte_set_home(prot
, home
);
219 #if CHIP_HAS_CBOX_HOME_MAP()
220 if (home
== PAGE_HOME_IMMUTABLE
) {
222 prot
= hv_pte_set_mode(prot
, HV_PTE_MODE_CACHE_HASH_L3
);
224 prot
= hv_pte_set_mode(prot
, HV_PTE_MODE_CACHE_NO_L3
);
231 * For a given kernel data VA, how should it be cached?
232 * We return the complete pgprot_t with caching bits set.
234 static pgprot_t __init
init_pgprot(ulong address
)
238 enum { CODE_DELTA
= MEM_SV_INTRPT
- PAGE_OFFSET
};
240 #if CHIP_HAS_CBOX_HOME_MAP()
241 /* For kdata=huge, everything is just hash-for-home. */
243 return construct_pgprot(PAGE_KERNEL
, PAGE_HOME_HASH
);
246 /* We map the aliased pages of permanent text inaccessible. */
247 if (address
< (ulong
) _sinittext
- CODE_DELTA
)
251 * We map read-only data non-coherent for performance. We could
252 * use neighborhood caching on TILE64, but it's not clear it's a win.
254 if ((address
>= (ulong
) __start_rodata
&&
255 address
< (ulong
) __end_rodata
) ||
256 address
== (ulong
) empty_zero_page
) {
257 return construct_pgprot(PAGE_KERNEL_RO
, PAGE_HOME_IMMUTABLE
);
260 /* As a performance optimization, keep the boot init stack here. */
261 if (address
>= (ulong
)&init_thread_union
&&
262 address
< (ulong
)&init_thread_union
+ THREAD_SIZE
)
263 return construct_pgprot(PAGE_KERNEL
, smp_processor_id());
266 #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
267 /* Force the atomic_locks[] array page to be hash-for-home. */
268 if (address
== (ulong
) atomic_locks
)
269 return construct_pgprot(PAGE_KERNEL
, PAGE_HOME_HASH
);
274 * Everything else that isn't data or bss is heap, so mark it
275 * with the initial heap home (hash-for-home, or this cpu). This
276 * includes any addresses after the loaded image and any address before
277 * _einitdata, since we already captured the case of text before
278 * _sinittext, and __pa(einittext) is approximately __pa(sinitdata).
280 * All the LOWMEM pages that we mark this way will get their
281 * struct page homecache properly marked later, in set_page_homes().
282 * The HIGHMEM pages we leave with a default zero for their
283 * homes, but with a zero free_time we don't have to actually
284 * do a flush action the first time we use them, either.
286 if (address
>= (ulong
) _end
|| address
< (ulong
) _einitdata
)
287 return construct_pgprot(PAGE_KERNEL
, initial_heap_home());
289 #if CHIP_HAS_CBOX_HOME_MAP()
290 /* Use hash-for-home if requested for data/bss. */
292 return construct_pgprot(PAGE_KERNEL
, PAGE_HOME_HASH
);
296 * Make the w1data homed like heap to start with, to avoid
297 * making it part of the page-striped data area when we're just
298 * going to convert it to read-only soon anyway.
300 if (address
>= (ulong
)__w1data_begin
&& address
< (ulong
)__w1data_end
)
301 return construct_pgprot(PAGE_KERNEL
, initial_heap_home());
304 * Otherwise we just hand out consecutive cpus. To avoid
305 * requiring this function to hold state, we just walk forward from
306 * _sdata by PAGE_SIZE, skipping the readonly and init data, to reach
307 * the requested address, while walking cpu home around kdata_mask.
308 * This is typically no more than a dozen or so iterations.
310 page
= (((ulong
)__w1data_end
) + PAGE_SIZE
- 1) & PAGE_MASK
;
311 BUG_ON(address
< page
|| address
>= (ulong
)_end
);
312 cpu
= cpumask_first(&kdata_mask
);
313 for (; page
< address
; page
+= PAGE_SIZE
) {
314 if (page
>= (ulong
)&init_thread_union
&&
315 page
< (ulong
)&init_thread_union
+ THREAD_SIZE
)
317 if (page
== (ulong
)empty_zero_page
)
320 #if !ATOMIC_LOCKS_FOUND_VIA_TABLE()
321 if (page
== (ulong
)atomic_locks
)
325 cpu
= cpumask_next(cpu
, &kdata_mask
);
327 cpu
= cpumask_first(&kdata_mask
);
329 return construct_pgprot(PAGE_KERNEL
, cpu
);
333 * This function sets up how we cache the kernel text. If we have
334 * hash-for-home support, normally that is used instead (see the
335 * kcache_hash boot flag for more information). But if we end up
336 * using a page-based caching technique, this option sets up the
337 * details of that. In addition, the "ktext=nocache" option may
338 * always be used to disable local caching of text pages, if desired.
341 static int __initdata ktext_arg_seen
;
342 static int __initdata ktext_small
;
343 static int __initdata ktext_local
;
344 static int __initdata ktext_all
;
345 static int __initdata ktext_nondataplane
;
346 static int __initdata ktext_nocache
;
347 static struct cpumask __initdata ktext_mask
;
349 static int __init
setup_ktext(char *str
)
354 /* If you have a leading "nocache", turn off ktext caching */
355 if (strncmp(str
, "nocache", 7) == 0) {
357 pr_info("ktext: disabling local caching of kernel text\n");
367 /* Default setting on Tile64: use a huge page */
368 if (strcmp(str
, "huge") == 0)
369 pr_info("ktext: using one huge locally cached page\n");
371 /* Pay TLB cost but get no cache benefit: cache small pages locally */
372 else if (strcmp(str
, "local") == 0) {
375 pr_info("ktext: using small pages with local caching\n");
378 /* Neighborhood cache ktext pages on all cpus. */
379 else if (strcmp(str
, "all") == 0) {
382 pr_info("ktext: using maximal caching neighborhood\n");
386 /* Neighborhood ktext pages on specified mask */
387 else if (cpulist_parse(str
, &ktext_mask
) == 0) {
388 char buf
[NR_CPUS
* 5];
389 cpulist_scnprintf(buf
, sizeof(buf
), &ktext_mask
);
390 if (cpumask_weight(&ktext_mask
) > 1) {
392 pr_info("ktext: using caching neighborhood %s "
393 "with small pages\n", buf
);
395 pr_info("ktext: caching on cpu %s with one huge page\n",
406 early_param("ktext", setup_ktext
);
409 static inline pgprot_t
ktext_set_nocache(pgprot_t prot
)
412 prot
= hv_pte_set_nc(prot
);
413 #if CHIP_HAS_NC_AND_NOALLOC_BITS()
415 prot
= hv_pte_set_no_alloc_l2(prot
);
421 static pmd_t
*__init
get_pmd(pgd_t pgtables
[], unsigned long va
)
423 return pmd_offset(pud_offset(&pgtables
[pgd_index(va
)], va
), va
);
426 static pmd_t
*__init
get_pmd(pgd_t pgtables
[], unsigned long va
)
428 pud_t
*pud
= pud_offset(&pgtables
[pgd_index(va
)], va
);
430 assign_pmd(pud
, alloc_pmd());
431 return pmd_offset(pud
, va
);
435 /* Temporary page table we use for staging. */
436 static pgd_t pgtables
[PTRS_PER_PGD
]
437 __attribute__((aligned(HV_PAGE_TABLE_ALIGN
)));
440 * This maps the physical memory to kernel virtual address space, a total
441 * of max_low_pfn pages, by creating page tables starting from address
444 * This routine transitions us from using a set of compiled-in large
445 * pages to using some more precise caching, including removing access
446 * to code pages mapped at PAGE_OFFSET (executed only at MEM_SV_START)
447 * marking read-only data as locally cacheable, striping the remaining
448 * .data and .bss across all the available tiles, and removing access
449 * to pages above the top of RAM (thus ensuring a page fault from a bad
450 * virtual address rather than a hypervisor shoot down for accessing
451 * memory outside the assigned limits).
453 static void __init
kernel_physical_mapping_init(pgd_t
*pgd_base
)
455 unsigned long address
, pfn
;
459 const struct cpumask
*my_cpu_mask
= cpumask_of(smp_processor_id());
460 struct cpumask kstripe_mask
;
463 #if CHIP_HAS_CBOX_HOME_MAP()
464 if (ktext_arg_seen
&& ktext_hash
) {
465 pr_warning("warning: \"ktext\" boot argument ignored"
466 " if \"kcache_hash\" sets up text hash-for-home\n");
470 if (kdata_arg_seen
&& kdata_hash
) {
471 pr_warning("warning: \"kdata\" boot argument ignored"
472 " if \"kcache_hash\" sets up data hash-for-home\n");
475 if (kdata_huge
&& !hash_default
) {
476 pr_warning("warning: disabling \"kdata=huge\"; requires"
477 " kcache_hash=all or =allbutstack\n");
483 * Set up a mask for cpus to use for kernel striping.
484 * This is normally all cpus, but minus dataplane cpus if any.
485 * If the dataplane covers the whole chip, we stripe over
486 * the whole chip too.
488 cpumask_copy(&kstripe_mask
, cpu_possible_mask
);
490 kdata_mask
= kstripe_mask
;
492 /* Allocate and fill in L2 page tables */
493 for (i
= 0; i
< MAX_NUMNODES
; ++i
) {
494 #ifdef CONFIG_HIGHMEM
495 unsigned long end_pfn
= node_lowmem_end_pfn
[i
];
497 unsigned long end_pfn
= node_end_pfn
[i
];
499 unsigned long end_huge_pfn
= 0;
501 /* Pre-shatter the last huge page to allow per-cpu pages. */
503 end_huge_pfn
= end_pfn
- (HPAGE_SIZE
>> PAGE_SHIFT
);
505 pfn
= node_start_pfn
[i
];
507 /* Allocate enough memory to hold L2 page tables for node. */
508 init_prealloc_ptes(i
, end_pfn
- pfn
);
510 address
= (unsigned long) pfn_to_kaddr(pfn
);
511 while (pfn
< end_pfn
) {
512 BUG_ON(address
& (HPAGE_SIZE
-1));
513 pmd
= get_pmd(pgtables
, address
);
514 pte
= get_prealloc_pte(pfn
);
515 if (pfn
< end_huge_pfn
) {
516 pgprot_t prot
= init_pgprot(address
);
517 *(pte_t
*)pmd
= pte_mkhuge(pfn_pte(pfn
, prot
));
518 for (pte_ofs
= 0; pte_ofs
< PTRS_PER_PTE
;
519 pfn
++, pte_ofs
++, address
+= PAGE_SIZE
)
520 pte
[pte_ofs
] = pfn_pte(pfn
, prot
);
523 printk(KERN_DEBUG
"pre-shattered huge"
524 " page at %#lx\n", address
);
525 for (pte_ofs
= 0; pte_ofs
< PTRS_PER_PTE
;
526 pfn
++, pte_ofs
++, address
+= PAGE_SIZE
) {
527 pgprot_t prot
= init_pgprot(address
);
528 pte
[pte_ofs
] = pfn_pte(pfn
, prot
);
530 assign_pte(pmd
, pte
);
536 * Set or check ktext_map now that we have cpu_possible_mask
537 * and kstripe_mask to work with.
540 cpumask_copy(&ktext_mask
, cpu_possible_mask
);
541 else if (ktext_nondataplane
)
542 ktext_mask
= kstripe_mask
;
543 else if (!cpumask_empty(&ktext_mask
)) {
544 /* Sanity-check any mask that was requested */
546 cpumask_andnot(&bad
, &ktext_mask
, cpu_possible_mask
);
547 cpumask_and(&ktext_mask
, &ktext_mask
, cpu_possible_mask
);
548 if (!cpumask_empty(&bad
)) {
549 char buf
[NR_CPUS
* 5];
550 cpulist_scnprintf(buf
, sizeof(buf
), &bad
);
551 pr_info("ktext: not using unavailable cpus %s\n", buf
);
553 if (cpumask_empty(&ktext_mask
)) {
554 pr_warning("ktext: no valid cpus; caching on %d.\n",
556 cpumask_copy(&ktext_mask
,
557 cpumask_of(smp_processor_id()));
561 address
= MEM_SV_INTRPT
;
562 pmd
= get_pmd(pgtables
, address
);
564 /* Allocate an L2 PTE for the kernel text */
566 pgprot_t prot
= construct_pgprot(PAGE_KERNEL_EXEC
,
567 PAGE_HOME_IMMUTABLE
);
571 prot
= hv_pte_set_mode(prot
,
572 HV_PTE_MODE_UNCACHED
);
574 prot
= hv_pte_set_mode(prot
,
575 HV_PTE_MODE_CACHE_NO_L3
);
577 prot
= hv_pte_set_mode(prot
,
578 HV_PTE_MODE_CACHE_TILE_L3
);
579 cpu
= cpumask_first(&ktext_mask
);
581 prot
= ktext_set_nocache(prot
);
584 BUG_ON(address
!= (unsigned long)_stext
);
585 pfn
= 0; /* code starts at PA 0 */
587 for (pte_ofs
= 0; address
< (unsigned long)_einittext
;
588 pfn
++, pte_ofs
++, address
+= PAGE_SIZE
) {
590 prot
= set_remote_cache_cpu(prot
, cpu
);
591 cpu
= cpumask_next(cpu
, &ktext_mask
);
593 cpu
= cpumask_first(&ktext_mask
);
595 pte
[pte_ofs
] = pfn_pte(pfn
, prot
);
597 assign_pte(pmd
, pte
);
599 pte_t pteval
= pfn_pte(0, PAGE_KERNEL_EXEC
);
600 pteval
= pte_mkhuge(pteval
);
601 #if CHIP_HAS_CBOX_HOME_MAP()
603 pteval
= hv_pte_set_mode(pteval
,
604 HV_PTE_MODE_CACHE_HASH_L3
);
605 pteval
= ktext_set_nocache(pteval
);
607 #endif /* CHIP_HAS_CBOX_HOME_MAP() */
608 if (cpumask_weight(&ktext_mask
) == 1) {
609 pteval
= set_remote_cache_cpu(pteval
,
610 cpumask_first(&ktext_mask
));
611 pteval
= hv_pte_set_mode(pteval
,
612 HV_PTE_MODE_CACHE_TILE_L3
);
613 pteval
= ktext_set_nocache(pteval
);
614 } else if (ktext_nocache
)
615 pteval
= hv_pte_set_mode(pteval
,
616 HV_PTE_MODE_UNCACHED
);
618 pteval
= hv_pte_set_mode(pteval
,
619 HV_PTE_MODE_CACHE_NO_L3
);
620 *(pte_t
*)pmd
= pteval
;
623 /* Set swapper_pgprot here so it is flushed to memory right away. */
624 swapper_pgprot
= init_pgprot((unsigned long)swapper_pg_dir
);
627 * Since we may be changing the caching of the stack and page
628 * table itself, we invoke an assembly helper to do the
631 * - flush the cache so we start with an empty slate
632 * - install pgtables[] as the real page table
633 * - flush the TLB so the new page table takes effect
635 rc
= flush_and_install_context(__pa(pgtables
),
636 init_pgprot((unsigned long)pgtables
),
637 __get_cpu_var(current_asid
),
638 cpumask_bits(my_cpu_mask
));
641 /* Copy the page table back to the normal swapper_pg_dir. */
642 memcpy(pgd_base
, pgtables
, sizeof(pgtables
));
643 __install_page_table(pgd_base
, __get_cpu_var(current_asid
),
647 * We just read swapper_pgprot and thus brought it into the cache,
648 * with its new home & caching mode. When we start the other CPUs,
649 * they're going to reference swapper_pgprot via their initial fake
650 * VA-is-PA mappings, which cache everything locally. At that
651 * time, if it's in our cache with a conflicting home, the
652 * simulator's coherence checker will complain. So, flush it out
653 * of our cache; we're not going to ever use it again anyway.
655 __insn_finv(&swapper_pgprot
);
659 * devmem_is_allowed() checks to see if /dev/mem access to a certain address
660 * is valid. The argument is a physical page number.
662 * On Tile, the only valid things for which we can just hand out unchecked
663 * PTEs are the kernel code and data. Anything else might change its
664 * homing with time, and we wouldn't know to adjust the /dev/mem PTEs.
665 * Note that init_thread_union is released to heap soon after boot,
666 * so we include it in the init data.
668 * For TILE-Gx, we might want to consider allowing access to PA
669 * regions corresponding to PCI space, etc.
671 int devmem_is_allowed(unsigned long pagenr
)
673 return pagenr
< kaddr_to_pfn(_end
) &&
674 !(pagenr
>= kaddr_to_pfn(&init_thread_union
) ||
675 pagenr
< kaddr_to_pfn(_einitdata
)) &&
676 !(pagenr
>= kaddr_to_pfn(_sinittext
) ||
677 pagenr
<= kaddr_to_pfn(_einittext
-1));
680 #ifdef CONFIG_HIGHMEM
681 static void __init
permanent_kmaps_init(pgd_t
*pgd_base
)
690 page_table_range_init(vaddr
, vaddr
+ PAGE_SIZE
*LAST_PKMAP
, pgd_base
);
692 pgd
= swapper_pg_dir
+ pgd_index(vaddr
);
693 pud
= pud_offset(pgd
, vaddr
);
694 pmd
= pmd_offset(pud
, vaddr
);
695 pte
= pte_offset_kernel(pmd
, vaddr
);
696 pkmap_page_table
= pte
;
698 #endif /* CONFIG_HIGHMEM */
701 static void __init
init_free_pfn_range(unsigned long start
, unsigned long end
)
704 struct page
*page
= pfn_to_page(start
);
706 for (pfn
= start
; pfn
< end
; ) {
707 /* Optimize by freeing pages in large batches */
708 int order
= __ffs(pfn
);
712 if (order
>= MAX_ORDER
)
715 while (pfn
+ count
> end
) {
719 for (p
= page
, i
= 0; i
< count
; ++i
, ++p
) {
720 __ClearPageReserved(p
);
722 * Hacky direct set to avoid unnecessary
723 * lock take/release for EVERY page here.
725 p
->_count
.counter
= 0;
726 p
->_mapcount
.counter
= -1;
728 init_page_count(page
);
729 __free_pages(page
, order
);
730 totalram_pages
+= count
;
737 static void __init
set_non_bootmem_pages_init(void)
741 unsigned long start
, end
;
742 int nid
= z
->zone_pgdat
->node_id
;
743 int idx
= zone_idx(z
);
745 start
= z
->zone_start_pfn
;
747 continue; /* bootmem */
748 end
= start
+ z
->spanned_pages
;
749 if (idx
== ZONE_NORMAL
) {
750 BUG_ON(start
!= node_start_pfn
[nid
]);
751 start
= node_free_pfn
[nid
];
753 #ifdef CONFIG_HIGHMEM
754 if (idx
== ZONE_HIGHMEM
)
755 totalhigh_pages
+= z
->spanned_pages
;
758 unsigned long percpu_pfn
= node_percpu_pfn
[nid
];
759 if (start
< percpu_pfn
&& end
> percpu_pfn
)
763 if (start
<= pci_reserve_start_pfn
&&
764 end
> pci_reserve_start_pfn
) {
765 if (end
> pci_reserve_end_pfn
)
766 init_free_pfn_range(pci_reserve_end_pfn
, end
);
767 end
= pci_reserve_start_pfn
;
770 init_free_pfn_range(start
, end
);
775 * paging_init() sets up the page tables - note that all of lowmem is
776 * already mapped by head.S.
778 void __init
paging_init(void)
780 #ifdef CONFIG_HIGHMEM
781 unsigned long vaddr
, end
;
786 pgd_t
*pgd_base
= swapper_pg_dir
;
788 kernel_physical_mapping_init(pgd_base
);
790 #ifdef CONFIG_HIGHMEM
792 * Fixed mappings, only the page table structure has to be
793 * created - mappings will be set by set_fixmap():
795 vaddr
= __fix_to_virt(__end_of_fixed_addresses
- 1) & PMD_MASK
;
796 end
= (FIXADDR_TOP
+ PMD_SIZE
- 1) & PMD_MASK
;
797 page_table_range_init(vaddr
, end
, pgd_base
);
798 permanent_kmaps_init(pgd_base
);
803 * Since GX allocates just one pmd_t array worth of vmalloc space,
804 * we go ahead and allocate it statically here, then share it
805 * globally. As a result we don't have to worry about any task
806 * changing init_mm once we get up and running, and there's no
807 * need for e.g. vmalloc_sync_all().
809 BUILD_BUG_ON(pgd_index(VMALLOC_START
) != pgd_index(VMALLOC_END
));
810 pud
= pud_offset(pgd_base
+ pgd_index(VMALLOC_START
), VMALLOC_START
);
811 assign_pmd(pud
, alloc_pmd());
817 * Walk the kernel page tables and derive the page_home() from
818 * the PTEs, so that set_pte() can properly validate the caching
819 * of all PTEs it sees.
821 void __init
set_page_homes(void)
825 static void __init
set_max_mapnr_init(void)
827 #ifdef CONFIG_FLATMEM
828 max_mapnr
= max_low_pfn
;
832 void __init
mem_init(void)
834 int codesize
, datasize
, initsize
;
840 #ifdef CONFIG_FLATMEM
845 #ifdef CONFIG_HIGHMEM
846 /* check that fixmap and pkmap do not overlap */
847 if (PKMAP_ADDR(LAST_PKMAP
-1) >= FIXADDR_START
) {
848 pr_err("fixmap and kmap areas overlap"
849 " - this will crash\n");
850 pr_err("pkstart: %lxh pkend: %lxh fixstart %lxh\n",
851 PKMAP_BASE
, PKMAP_ADDR(LAST_PKMAP
-1),
857 set_max_mapnr_init();
859 /* this will put all bootmem onto the freelists */
860 totalram_pages
+= free_all_bootmem();
862 /* count all remaining LOWMEM and give all HIGHMEM to page allocator */
863 set_non_bootmem_pages_init();
865 codesize
= (unsigned long)&_etext
- (unsigned long)&_text
;
866 datasize
= (unsigned long)&_end
- (unsigned long)&_sdata
;
867 initsize
= (unsigned long)&_einittext
- (unsigned long)&_sinittext
;
868 initsize
+= (unsigned long)&_einitdata
- (unsigned long)&_sinitdata
;
870 pr_info("Memory: %luk/%luk available (%dk kernel code, %dk data, %dk init, %ldk highmem)\n",
871 (unsigned long) nr_free_pages() << (PAGE_SHIFT
-10),
872 num_physpages
<< (PAGE_SHIFT
-10),
876 (unsigned long) (totalhigh_pages
<< (PAGE_SHIFT
-10))
880 * In debug mode, dump some interesting memory mappings.
882 #ifdef CONFIG_HIGHMEM
883 printk(KERN_DEBUG
" KMAP %#lx - %#lx\n",
884 FIXADDR_START
, FIXADDR_TOP
+ PAGE_SIZE
- 1);
885 printk(KERN_DEBUG
" PKMAP %#lx - %#lx\n",
886 PKMAP_BASE
, PKMAP_ADDR(LAST_PKMAP
) - 1);
888 #ifdef CONFIG_HUGEVMAP
889 printk(KERN_DEBUG
" HUGEMAP %#lx - %#lx\n",
890 HUGE_VMAP_BASE
, HUGE_VMAP_END
- 1);
892 printk(KERN_DEBUG
" VMALLOC %#lx - %#lx\n",
893 _VMALLOC_START
, _VMALLOC_END
- 1);
895 for (i
= MAX_NUMNODES
-1; i
>= 0; --i
) {
896 struct pglist_data
*node
= &node_data
[i
];
897 if (node
->node_present_pages
) {
898 unsigned long start
= (unsigned long)
899 pfn_to_kaddr(node
->node_start_pfn
);
900 unsigned long end
= start
+
901 (node
->node_present_pages
<< PAGE_SHIFT
);
902 printk(KERN_DEBUG
" MEM%d %#lx - %#lx\n",
908 for (i
= MAX_NUMNODES
-1; i
>= 0; --i
) {
909 if ((unsigned long)vbase_map
[i
] != -1UL) {
910 printk(KERN_DEBUG
" LOWMEM%d %#lx - %#lx\n",
911 i
, (unsigned long) (vbase_map
[i
]),
912 (unsigned long) (last
-1));
920 * Convert from using one lock for all atomic operations to
923 __init_atomic_per_cpu();
928 * this is for the non-NUMA, single node SMP system case.
929 * Specifically, in the case of x86, we will always add
930 * memory to the highmem for now.
932 #ifndef CONFIG_NEED_MULTIPLE_NODES
933 int arch_add_memory(u64 start
, u64 size
)
935 struct pglist_data
*pgdata
= &contig_page_data
;
936 struct zone
*zone
= pgdata
->node_zones
+ MAX_NR_ZONES
-1;
937 unsigned long start_pfn
= start
>> PAGE_SHIFT
;
938 unsigned long nr_pages
= size
>> PAGE_SHIFT
;
940 return __add_pages(zone
, start_pfn
, nr_pages
);
943 int remove_memory(u64 start
, u64 size
)
949 struct kmem_cache
*pgd_cache
;
951 void __init
pgtable_cache_init(void)
953 pgd_cache
= kmem_cache_create("pgd", SIZEOF_PGD
, SIZEOF_PGD
, 0, NULL
);
955 panic("pgtable_cache_init(): Cannot create pgd cache");
958 #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
960 * The __w1data area holds data that is only written during initialization,
961 * and is read-only and thus freely cacheable thereafter. Fix the page
962 * table entries that cover that region accordingly.
964 static void mark_w1data_ro(void)
966 /* Loop over page table entries */
967 unsigned long addr
= (unsigned long)__w1data_begin
;
968 BUG_ON((addr
& (PAGE_SIZE
-1)) != 0);
969 for (; addr
<= (unsigned long)__w1data_end
- 1; addr
+= PAGE_SIZE
) {
970 unsigned long pfn
= kaddr_to_pfn((void *)addr
);
971 pte_t
*ptep
= virt_to_pte(NULL
, addr
);
972 BUG_ON(pte_huge(*ptep
)); /* not relevant for kdata_huge */
973 set_pte_at(&init_mm
, addr
, ptep
, pfn_pte(pfn
, PAGE_KERNEL_RO
));
978 #ifdef CONFIG_DEBUG_PAGEALLOC
979 static long __write_once initfree
;
981 static long __write_once initfree
= 1;
984 /* Select whether to free (1) or mark unusable (0) the __init pages. */
985 static int __init
set_initfree(char *str
)
988 if (strict_strtol(str
, 0, &val
) == 0) {
990 pr_info("initfree: %s free init pages\n",
991 initfree
? "will" : "won't");
995 __setup("initfree=", set_initfree
);
997 static void free_init_pages(char *what
, unsigned long begin
, unsigned long end
)
999 unsigned long addr
= (unsigned long) begin
;
1001 if (kdata_huge
&& !initfree
) {
1002 pr_warning("Warning: ignoring initfree=0:"
1003 " incompatible with kdata=huge\n");
1006 end
= (end
+ PAGE_SIZE
- 1) & PAGE_MASK
;
1007 local_flush_tlb_pages(NULL
, begin
, PAGE_SIZE
, end
- begin
);
1008 for (addr
= begin
; addr
< end
; addr
+= PAGE_SIZE
) {
1010 * Note we just reset the home here directly in the
1011 * page table. We know this is safe because our caller
1012 * just flushed the caches on all the other cpus,
1013 * and they won't be touching any of these pages.
1015 int pfn
= kaddr_to_pfn((void *)addr
);
1016 struct page
*page
= pfn_to_page(pfn
);
1017 pte_t
*ptep
= virt_to_pte(NULL
, addr
);
1020 * If debugging page accesses then do not free
1021 * this memory but mark them not present - any
1022 * buggy init-section access will create a
1023 * kernel page fault:
1025 pte_clear(&init_mm
, addr
, ptep
);
1028 __ClearPageReserved(page
);
1029 init_page_count(page
);
1030 if (pte_huge(*ptep
))
1031 BUG_ON(!kdata_huge
);
1033 set_pte_at(&init_mm
, addr
, ptep
,
1034 pfn_pte(pfn
, PAGE_KERNEL
));
1035 memset((void *)addr
, POISON_FREE_INITMEM
, PAGE_SIZE
);
1039 pr_info("Freeing %s: %ldk freed\n", what
, (end
- begin
) >> 10);
1042 void free_initmem(void)
1044 const unsigned long text_delta
= MEM_SV_INTRPT
- PAGE_OFFSET
;
1047 * Evict the dirty initdata on the boot cpu, evict the w1data
1048 * wherever it's homed, and evict all the init code everywhere.
1049 * We are guaranteed that no one will touch the init pages any
1050 * more, and although other cpus may be touching the w1data,
1051 * we only actually change the caching on tile64, which won't
1052 * be keeping local copies in the other tiles' caches anyway.
1054 homecache_evict(&cpu_cacheable_map
);
1056 /* Free the data pages that we won't use again after init. */
1057 free_init_pages("unused kernel data",
1058 (unsigned long)_sinitdata
,
1059 (unsigned long)_einitdata
);
1062 * Free the pages mapped from 0xc0000000 that correspond to code
1063 * pages from MEM_SV_INTRPT that we won't use again after init.
1065 free_init_pages("unused kernel text",
1066 (unsigned long)_sinittext
- text_delta
,
1067 (unsigned long)_einittext
- text_delta
);
1069 #if !CHIP_HAS_COHERENT_LOCAL_CACHE()
1071 * Upgrade the .w1data section to globally cached.
1072 * We don't do this on tilepro, since the cache architecture
1073 * pretty much makes it irrelevant, and in any case we end
1074 * up having racing issues with other tiles that may touch
1075 * the data after we flush the cache but before we update
1076 * the PTEs and flush the TLBs, causing sharer shootdowns
1077 * later. Even though this is to clean data, it seems like
1078 * an unnecessary complication.
1083 /* Do a global TLB flush so everyone sees the changes. */