drivers/block/cciss.h

   1 #ifndef CCISS_H
   2 #define CCISS_H
   3
   4 #include <linux/genhd.h>
   5 #include <linux/mutex.h>
   6
   7 #include "cciss_cmd.h"
   8
   9
  10 #define NWD_SHIFT       4
  11 #define MAX_PART        (1 << NWD_SHIFT)
  12
  13 #define IO_OK           0
  14 #define IO_ERROR        1
  15 #define IO_NEEDS_RETRY  3
  16
  17 #define VENDOR_LEN      8
  18 #define MODEL_LEN       16
  19 #define REV_LEN         4
  20
  21 struct ctlr_info;
  22 typedef struct ctlr_info ctlr_info_t;
  23
  24 struct access_method {
  25         void (*submit_command)(ctlr_info_t *h, CommandList_struct *c);
  26         void (*set_intr_mask)(ctlr_info_t *h, unsigned long val);
  27         unsigned long (*fifo_full)(ctlr_info_t *h);
  28         unsigned long (*intr_pending)(ctlr_info_t *h);
  29         unsigned long (*command_completed)(ctlr_info_t *h);
  30 };
  31 typedef struct _drive_info_struct
  32 {
  33         unsigned char LunID[8];
  34         int     usage_count;
  35         struct request_queue *queue;
  36         sector_t nr_blocks;
  37         int     block_size;
  38         int     heads;
  39         int     sectors;
  40         int     cylinders;
  41         int     raid_level; /* set to -1 to indicate that
  42                              * the drive is not in use/configured
  43                              */
  44         int     busy_configuring; /* This is set when a drive is being removed
  45                                    * to prevent it from being opened or it's
  46                                    * queue from being started.
  47                                    */
  48         struct  device dev;
  49         __u8 serial_no[16]; /* from inquiry page 0x83,
  50                              * not necc. null terminated.
  51                              */
  52         char vendor[VENDOR_LEN + 1]; /* SCSI vendor string */
  53         char model[MODEL_LEN + 1];   /* SCSI model string */
  54         char rev[REV_LEN + 1];       /* SCSI revision string */
  55         char device_initialized;     /* indicates whether dev is initialized */
  56 } drive_info_struct;
  57
  58 struct Cmd_sg_list {
  59         SGDescriptor_struct     *sgchain;
  60         dma_addr_t              sg_chain_dma;
  61         int                     chain_block_size;
  62 };
  63
  64 struct ctlr_info
  65 {
  66         int     ctlr;
  67         char    devname[8];
  68         char    *product_name;
  69         char    firm_ver[4]; // Firmware version
  70         struct pci_dev *pdev;
  71         __u32   board_id;
  72         void __iomem *vaddr;
  73         unsigned long paddr;
  74         int     nr_cmds; /* Number of commands allowed on this controller */
  75         CfgTable_struct __iomem *cfgtable;
  76         int     interrupts_enabled;
  77         int     major;
  78         int     max_commands;
  79         int     commands_outstanding;
  80         int     max_outstanding; /* Debug */
  81         int     num_luns;
  82         int     highest_lun;
  83         int     usage_count;  /* number of opens all all minor devices */
  84         /* Need space for temp sg list
  85          * number of scatter/gathers supported
  86          * number of scatter/gathers in chained block
  87          */
  88         struct  scatterlist **scatter_list;
  89         int     maxsgentries;
  90         int     chainsize;
  91         int     max_cmd_sgentries;
  92         struct Cmd_sg_list **cmd_sg_list;
  93
  94 #       define DOORBELL_INT     0
  95 #       define PERF_MODE_INT    1
  96 #       define SIMPLE_MODE_INT  2
  97 #       define MEMQ_MODE_INT    3
  98         unsigned int intr[4];
  99         unsigned int msix_vector;
 100         unsigned int msi_vector;
 101         int     cciss_max_sectors;
 102         BYTE    cciss_read;
 103         BYTE    cciss_write;
 104         BYTE    cciss_read_capacity;
 105
 106         // information about each logical volume
 107         drive_info_struct *drv[CISS_MAX_LUN];
 108
 109         struct access_method access;
 110
 111         /* queue and queue Info */
 112         struct hlist_head reqQ;
 113         struct hlist_head cmpQ;
 114         unsigned int Qdepth;
 115         unsigned int maxQsinceinit;
 116         unsigned int maxSG;
 117         spinlock_t lock;
 118
 119         //* pointers to command and error info pool */
 120         CommandList_struct      *cmd_pool;
 121         dma_addr_t              cmd_pool_dhandle;
 122         ErrorInfo_struct        *errinfo_pool;
 123         dma_addr_t              errinfo_pool_dhandle;
 124         unsigned long           *cmd_pool_bits;
 125         int                     nr_allocs;
 126         int                     nr_frees;
 127         int                     busy_configuring;
 128         int                     busy_initializing;
 129         int                     busy_scanning;
 130         struct mutex            busy_shutting_down;
 131
 132         /* This element holds the zero based queue number of the last
 133          * queue to be started.  It is used for fairness.
 134         */
 135         int                     next_to_run;
 136
 137         // Disk structures we need to pass back
 138         struct gendisk   *gendisk[CISS_MAX_LUN];
 139 #ifdef CONFIG_CISS_SCSI_TAPE
 140         void *scsi_ctlr; /* ptr to structure containing scsi related stuff */
 141         /* list of block side commands the scsi error handling sucked up */
 142         /* and saved for later processing */
 143 #endif
 144         unsigned char alive;
 145         struct list_head scan_list;
 146         struct completion scan_wait;
 147         struct device dev;
 148 };
 149
 150 /*  Defining the diffent access_menthods */
 151 /*
 152  * Memory mapped FIFO interface (SMART 53xx cards)
 153  */
 154 #define SA5_DOORBELL    0x20
 155 #define SA5_REQUEST_PORT_OFFSET 0x40
 156 #define SA5_REPLY_INTR_MASK_OFFSET      0x34
 157 #define SA5_REPLY_PORT_OFFSET           0x44
 158 #define SA5_INTR_STATUS         0x30
 159 #define SA5_SCRATCHPAD_OFFSET   0xB0
 160
 161 #define SA5_CTCFG_OFFSET        0xB4
 162 #define SA5_CTMEM_OFFSET        0xB8
 163
 164 #define SA5_INTR_OFF            0x08
 165 #define SA5B_INTR_OFF           0x04
 166 #define SA5_INTR_PENDING        0x08
 167 #define SA5B_INTR_PENDING       0x04
 168 #define FIFO_EMPTY              0xffffffff
 169 #define CCISS_FIRMWARE_READY    0xffff0000 /* value in scratchpad register */
 170
 171 #define  CISS_ERROR_BIT         0x02
 172
 173 #define CCISS_INTR_ON   1
 174 #define CCISS_INTR_OFF  0
 175 /*
 176         Send the command to the hardware
 177 */
 178 static void SA5_submit_command( ctlr_info_t *h, CommandList_struct *c)
 179 {
 180 #ifdef CCISS_DEBUG
 181          printk("Sending %x - down to controller\n", c->busaddr );
 182 #endif /* CCISS_DEBUG */
 183          writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
 184          h->commands_outstanding++;
 185          if ( h->commands_outstanding > h->max_outstanding)
 186                 h->max_outstanding = h->commands_outstanding;
 187 }
 188
 189 /*
 190  *  This card is the opposite of the other cards.
 191  *   0 turns interrupts on...
 192  *   0x08 turns them off...
 193  */
 194 static void SA5_intr_mask(ctlr_info_t *h, unsigned long val)
 195 {
 196         if (val)
 197         { /* Turn interrupts on */
 198                 h->interrupts_enabled = 1;
 199                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 200         } else /* Turn them off */
 201         {
 202                 h->interrupts_enabled = 0;
 203                 writel( SA5_INTR_OFF,
 204                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 205         }
 206 }
 207 /*
 208  *  This card is the opposite of the other cards.
 209  *   0 turns interrupts on...
 210  *   0x04 turns them off...
 211  */
 212 static void SA5B_intr_mask(ctlr_info_t *h, unsigned long val)
 213 {
 214         if (val)
 215         { /* Turn interrupts on */
 216                 h->interrupts_enabled = 1;
 217                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 218         } else /* Turn them off */
 219         {
 220                 h->interrupts_enabled = 0;
 221                 writel( SA5B_INTR_OFF,
 222                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 223         }
 224 }
 225 /*
 226  *  Returns true if fifo is full.
 227  *
 228  */
 229 static unsigned long SA5_fifo_full(ctlr_info_t *h)
 230 {
 231         if( h->commands_outstanding >= h->max_commands)
 232                 return(1);
 233         else
 234                 return(0);
 235
 236 }
 237 /*
 238  *   returns value read from hardware.
 239  *     returns FIFO_EMPTY if there is nothing to read
 240  */
 241 static unsigned long SA5_completed(ctlr_info_t *h)
 242 {
 243         unsigned long register_value
 244                 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
 245         if(register_value != FIFO_EMPTY)
 246         {
 247                 h->commands_outstanding--;
 248 #ifdef CCISS_DEBUG
 249                 printk("cciss:  Read %lx back from board\n", register_value);
 250 #endif /* CCISS_DEBUG */
 251         }
 252 #ifdef CCISS_DEBUG
 253         else
 254         {
 255                 printk("cciss:  FIFO Empty read\n");
 256         }
 257 #endif
 258         return ( register_value);
 259
 260 }
 261 /*
 262  *      Returns true if an interrupt is pending..
 263  */
 264 static unsigned long SA5_intr_pending(ctlr_info_t *h)
 265 {
 266         unsigned long register_value  =
 267                 readl(h->vaddr + SA5_INTR_STATUS);
 268 #ifdef CCISS_DEBUG
 269         printk("cciss: intr_pending %lx\n", register_value);
 270 #endif  /* CCISS_DEBUG */
 271         if( register_value &  SA5_INTR_PENDING)
 272                 return  1;
 273         return 0 ;
 274 }
 275
 276 /*
 277  *      Returns true if an interrupt is pending..
 278  */
 279 static unsigned long SA5B_intr_pending(ctlr_info_t *h)
 280 {
 281         unsigned long register_value  =
 282                 readl(h->vaddr + SA5_INTR_STATUS);
 283 #ifdef CCISS_DEBUG
 284         printk("cciss: intr_pending %lx\n", register_value);
 285 #endif  /* CCISS_DEBUG */
 286         if( register_value &  SA5B_INTR_PENDING)
 287                 return  1;
 288         return 0 ;
 289 }
 290
 291
 292 static struct access_method SA5_access = {
 293         SA5_submit_command,
 294         SA5_intr_mask,
 295         SA5_fifo_full,
 296         SA5_intr_pending,
 297         SA5_completed,
 298 };
 299
 300 static struct access_method SA5B_access = {
 301         SA5_submit_command,
 302         SA5B_intr_mask,
 303         SA5_fifo_full,
 304         SA5B_intr_pending,
 305         SA5_completed,
 306 };
 307
 308 struct board_type {
 309         __u32   board_id;
 310         char    *product_name;
 311         struct access_method *access;
 312         int nr_cmds; /* Max cmds this kind of ctlr can handle. */
 313 };
 314
 315 #define CCISS_LOCK(i)   (&hba[i]->lock)
 316
 317 #endif /* CCISS_H */
 318