drivers/gpu/drm/i915/dvo_ivch.c

   1 /*
   2  * Copyright © 2006 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "dvo.h"
  29
  30 /*
  31  * register definitions for the i82807aa.
  32  *
  33  * Documentation on this chipset can be found in datasheet #29069001 at
  34  * intel.com.
  35  */
  36
  37 /*
  38  * VCH Revision & GMBus Base Addr
  39  */
  40 #define VR00            0x00
  41 # define VR00_BASE_ADDRESS_MASK         0x007f
  42
  43 /*
  44  * Functionality Enable
  45  */
  46 #define VR01            0x01
  47
  48 /*
  49  * Enable the panel fitter
  50  */
  51 # define VR01_PANEL_FIT_ENABLE          (1 << 3)
  52 /*
  53  * Enables the LCD display.
  54  *
  55  * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
  56  */
  57 # define VR01_LCD_ENABLE                (1 << 2)
  58 /** Enables the DVO repeater. */
  59 # define VR01_DVO_BYPASS_ENABLE         (1 << 1)
  60 /** Enables the DVO clock */
  61 # define VR01_DVO_ENABLE                (1 << 0)
  62
  63 /*
  64  * LCD Interface Format
  65  */
  66 #define VR10            0x10
  67 /** Enables LVDS output instead of CMOS */
  68 # define VR10_LVDS_ENABLE               (1 << 4)
  69 /** Enables 18-bit LVDS output. */
  70 # define VR10_INTERFACE_1X18            (0 << 2)
  71 /** Enables 24-bit LVDS or CMOS output */
  72 # define VR10_INTERFACE_1X24            (1 << 2)
  73 /** Enables 2x18-bit LVDS or CMOS output. */
  74 # define VR10_INTERFACE_2X18            (2 << 2)
  75 /** Enables 2x24-bit LVDS output */
  76 # define VR10_INTERFACE_2X24            (3 << 2)
  77
  78 /*
  79  * VR20 LCD Horizontal Display Size
  80  */
  81 #define VR20    0x20
  82
  83 /*
  84  * LCD Vertical Display Size
  85  */
  86 #define VR21    0x20
  87
  88 /*
  89  * Panel power down status
  90  */
  91 #define VR30            0x30
  92 /** Read only bit indicating that the panel is not in a safe poweroff state. */
  93 # define VR30_PANEL_ON                  (1 << 15)
  94
  95 #define VR40            0x40
  96 # define VR40_STALL_ENABLE              (1 << 13)
  97 # define VR40_VERTICAL_INTERP_ENABLE    (1 << 12)
  98 # define VR40_ENHANCED_PANEL_FITTING    (1 << 11)
  99 # define VR40_HORIZONTAL_INTERP_ENABLE  (1 << 10)
 100 # define VR40_AUTO_RATIO_ENABLE         (1 << 9)
 101 # define VR40_CLOCK_GATING_ENABLE       (1 << 8)
 102
 103 /*
 104  * Panel Fitting Vertical Ratio
 105  * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
 106  */
 107 #define VR41            0x41
 108
 109 /*
 110  * Panel Fitting Horizontal Ratio
 111  * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
 112  */
 113 #define VR42            0x42
 114
 115 /*
 116  * Horizontal Image Size
 117  */
 118 #define VR43            0x43
 119
 120 /* VR80 GPIO 0
 121  */
 122 #define VR80        0x80
 123 #define VR81        0x81
 124 #define VR82        0x82
 125 #define VR83        0x83
 126 #define VR84        0x84
 127 #define VR85        0x85
 128 #define VR86        0x86
 129 #define VR87        0x87
 130
 131 /* VR88 GPIO 8
 132  */
 133 #define VR88        0x88
 134
 135 /* Graphics BIOS scratch 0
 136  */
 137 #define VR8E        0x8E
 138 # define VR8E_PANEL_TYPE_MASK           (0xf << 0)
 139 # define VR8E_PANEL_INTERFACE_CMOS      (0 << 4)
 140 # define VR8E_PANEL_INTERFACE_LVDS      (1 << 4)
 141 # define VR8E_FORCE_DEFAULT_PANEL       (1 << 5)
 142
 143 /* Graphics BIOS scratch 1
 144  */
 145 #define VR8F        0x8F
 146 # define VR8F_VCH_PRESENT               (1 << 0)
 147 # define VR8F_DISPLAY_CONN              (1 << 1)
 148 # define VR8F_POWER_MASK                (0x3c)
 149 # define VR8F_POWER_POS                 (2)
 150
 151
 152 struct ivch_priv {
 153         bool quiet;
 154
 155         uint16_t width, height;
 156
 157         uint16_t save_VR01;
 158         uint16_t save_VR40;
 159 };
 160
 161
 162 static void ivch_dump_regs(struct intel_dvo_device *dvo);
 163
 164 /**
 165  * Reads a register on the ivch.
 166  *
 167  * Each of the 256 registers are 16 bits long.
 168  */
 169 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
 170 {
 171         struct ivch_priv *priv = dvo->dev_priv;
 172         struct i2c_adapter *adapter = dvo->i2c_bus;
 173         struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
 174         u8 out_buf[1];
 175         u8 in_buf[2];
 176
 177         struct i2c_msg msgs[] = {
 178                 {
 179                         .addr = dvo->slave_addr,
 180                         .flags = I2C_M_RD,
 181                         .len = 0,
 182                 },
 183                 {
 184                         .addr = 0,
 185                         .flags = I2C_M_NOSTART,
 186                         .len = 1,
 187                         .buf = out_buf,
 188                 },
 189                 {
 190                         .addr = dvo->slave_addr,
 191                         .flags = I2C_M_RD | I2C_M_NOSTART,
 192                         .len = 2,
 193                         .buf = in_buf,
 194                 }
 195         };
 196
 197         out_buf[0] = addr;
 198
 199         if (i2c_transfer(&i2cbus->adapter, msgs, 3) == 3) {
 200                 *data = (in_buf[1] << 8) | in_buf[0];
 201                 return true;
 202         };
 203
 204         if (!priv->quiet) {
 205                 DRM_DEBUG_KMS("Unable to read register 0x%02x from "
 206                                 "%s:%02x.\n",
 207                           addr, i2cbus->adapter.name, dvo->slave_addr);
 208         }
 209         return false;
 210 }
 211
 212 /** Writes a 16-bit register on the ivch */
 213 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
 214 {
 215         struct ivch_priv *priv = dvo->dev_priv;
 216         struct i2c_adapter *adapter = dvo->i2c_bus;
 217         struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
 218         u8 out_buf[3];
 219         struct i2c_msg msg = {
 220                 .addr = dvo->slave_addr,
 221                 .flags = 0,
 222                 .len = 3,
 223                 .buf = out_buf,
 224         };
 225
 226         out_buf[0] = addr;
 227         out_buf[1] = data & 0xff;
 228         out_buf[2] = data >> 8;
 229
 230         if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
 231                 return true;
 232
 233         if (!priv->quiet) {
 234                 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
 235                           addr, i2cbus->adapter.name, dvo->slave_addr);
 236         }
 237
 238         return false;
 239 }
 240
 241 /** Probes the given bus and slave address for an ivch */
 242 static bool ivch_init(struct intel_dvo_device *dvo,
 243                       struct i2c_adapter *adapter)
 244 {
 245         struct ivch_priv *priv;
 246         uint16_t temp;
 247
 248         priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
 249         if (priv == NULL)
 250                 return false;
 251
 252         dvo->i2c_bus = adapter;
 253         dvo->dev_priv = priv;
 254         priv->quiet = true;
 255
 256         if (!ivch_read(dvo, VR00, &temp))
 257                 goto out;
 258         priv->quiet = false;
 259
 260         /* Since the identification bits are probably zeroes, which doesn't seem
 261          * very unique, check that the value in the base address field matches
 262          * the address it's responding on.
 263          */
 264         if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
 265                 DRM_DEBUG_KMS("ivch detect failed due to address mismatch "
 266                           "(%d vs %d)\n",
 267                           (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
 268                 goto out;
 269         }
 270
 271         ivch_read(dvo, VR20, &priv->width);
 272         ivch_read(dvo, VR21, &priv->height);
 273
 274         return true;
 275
 276 out:
 277         kfree(priv);
 278         return false;
 279 }
 280
 281 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
 282 {
 283         return connector_status_connected;
 284 }
 285
 286 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
 287                                             struct drm_display_mode *mode)
 288 {
 289         if (mode->clock > 112000)
 290                 return MODE_CLOCK_HIGH;
 291
 292         return MODE_OK;
 293 }
 294
 295 /** Sets the power state of the panel connected to the ivch */
 296 static void ivch_dpms(struct intel_dvo_device *dvo, int mode)
 297 {
 298         int i;
 299         uint16_t vr01, vr30, backlight;
 300
 301         /* Set the new power state of the panel. */
 302         if (!ivch_read(dvo, VR01, &vr01))
 303                 return;
 304
 305         if (mode == DRM_MODE_DPMS_ON)
 306                 backlight = 1;
 307         else
 308                 backlight = 0;
 309         ivch_write(dvo, VR80, backlight);
 310
 311         if (mode == DRM_MODE_DPMS_ON)
 312                 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
 313         else
 314                 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
 315
 316         ivch_write(dvo, VR01, vr01);
 317
 318         /* Wait for the panel to make its state transition */
 319         for (i = 0; i < 100; i++) {
 320                 if (!ivch_read(dvo, VR30, &vr30))
 321                         break;
 322
 323                 if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DRM_MODE_DPMS_ON))
 324                         break;
 325                 udelay(1000);
 326         }
 327         /* wait some more; vch may fail to resync sometimes without this */
 328         udelay(16 * 1000);
 329 }
 330
 331 static void ivch_mode_set(struct intel_dvo_device *dvo,
 332                           struct drm_display_mode *mode,
 333                           struct drm_display_mode *adjusted_mode)
 334 {
 335         uint16_t vr40 = 0;
 336         uint16_t vr01;
 337
 338         vr01 = 0;
 339         vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
 340                 VR40_HORIZONTAL_INTERP_ENABLE);
 341
 342         if (mode->hdisplay != adjusted_mode->hdisplay ||
 343             mode->vdisplay != adjusted_mode->vdisplay) {
 344                 uint16_t x_ratio, y_ratio;
 345
 346                 vr01 |= VR01_PANEL_FIT_ENABLE;
 347                 vr40 |= VR40_CLOCK_GATING_ENABLE;
 348                 x_ratio = (((mode->hdisplay - 1) << 16) /
 349                            (adjusted_mode->hdisplay - 1)) >> 2;
 350                 y_ratio = (((mode->vdisplay - 1) << 16) /
 351                            (adjusted_mode->vdisplay - 1)) >> 2;
 352                 ivch_write (dvo, VR42, x_ratio);
 353                 ivch_write (dvo, VR41, y_ratio);
 354         } else {
 355                 vr01 &= ~VR01_PANEL_FIT_ENABLE;
 356                 vr40 &= ~VR40_CLOCK_GATING_ENABLE;
 357         }
 358         vr40 &= ~VR40_AUTO_RATIO_ENABLE;
 359
 360         ivch_write(dvo, VR01, vr01);
 361         ivch_write(dvo, VR40, vr40);
 362
 363         ivch_dump_regs(dvo);
 364 }
 365
 366 static void ivch_dump_regs(struct intel_dvo_device *dvo)
 367 {
 368         uint16_t val;
 369
 370         ivch_read(dvo, VR00, &val);
 371         DRM_LOG_KMS("VR00: 0x%04x\n", val);
 372         ivch_read(dvo, VR01, &val);
 373         DRM_LOG_KMS("VR01: 0x%04x\n", val);
 374         ivch_read(dvo, VR30, &val);
 375         DRM_LOG_KMS("VR30: 0x%04x\n", val);
 376         ivch_read(dvo, VR40, &val);
 377         DRM_LOG_KMS("VR40: 0x%04x\n", val);
 378
 379         /* GPIO registers */
 380         ivch_read(dvo, VR80, &val);
 381         DRM_LOG_KMS("VR80: 0x%04x\n", val);
 382         ivch_read(dvo, VR81, &val);
 383         DRM_LOG_KMS("VR81: 0x%04x\n", val);
 384         ivch_read(dvo, VR82, &val);
 385         DRM_LOG_KMS("VR82: 0x%04x\n", val);
 386         ivch_read(dvo, VR83, &val);
 387         DRM_LOG_KMS("VR83: 0x%04x\n", val);
 388         ivch_read(dvo, VR84, &val);
 389         DRM_LOG_KMS("VR84: 0x%04x\n", val);
 390         ivch_read(dvo, VR85, &val);
 391         DRM_LOG_KMS("VR85: 0x%04x\n", val);
 392         ivch_read(dvo, VR86, &val);
 393         DRM_LOG_KMS("VR86: 0x%04x\n", val);
 394         ivch_read(dvo, VR87, &val);
 395         DRM_LOG_KMS("VR87: 0x%04x\n", val);
 396         ivch_read(dvo, VR88, &val);
 397         DRM_LOG_KMS("VR88: 0x%04x\n", val);
 398
 399         /* Scratch register 0 - AIM Panel type */
 400         ivch_read(dvo, VR8E, &val);
 401         DRM_LOG_KMS("VR8E: 0x%04x\n", val);
 402
 403         /* Scratch register 1 - Status register */
 404         ivch_read(dvo, VR8F, &val);
 405         DRM_LOG_KMS("VR8F: 0x%04x\n", val);
 406 }
 407
 408 static void ivch_save(struct intel_dvo_device *dvo)
 409 {
 410         struct ivch_priv *priv = dvo->dev_priv;
 411
 412         ivch_read(dvo, VR01, &priv->save_VR01);
 413         ivch_read(dvo, VR40, &priv->save_VR40);
 414 }
 415
 416 static void ivch_restore(struct intel_dvo_device *dvo)
 417 {
 418         struct ivch_priv *priv = dvo->dev_priv;
 419
 420         ivch_write(dvo, VR01, priv->save_VR01);
 421         ivch_write(dvo, VR40, priv->save_VR40);
 422 }
 423
 424 static void ivch_destroy(struct intel_dvo_device *dvo)
 425 {
 426         struct ivch_priv *priv = dvo->dev_priv;
 427
 428         if (priv) {
 429                 kfree(priv);
 430                 dvo->dev_priv = NULL;
 431         }
 432 }
 433
 434 struct intel_dvo_dev_ops ivch_ops= {
 435         .init = ivch_init,
 436         .dpms = ivch_dpms,
 437         .save = ivch_save,
 438         .restore = ivch_restore,
 439         .mode_valid = ivch_mode_valid,
 440         .mode_set = ivch_mode_set,
 441         .detect = ivch_detect,
 442         .dump_regs = ivch_dump_regs,
 443         .destroy = ivch_destroy,
 444 };