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Linux 2.6.33-rc6
[cris-mirror.git] / drivers / gpu / drm / i915 / intel_display.c
blob45da78ef4a926c4f0d2e84c812bd6f870a2f425d
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include "drmP.h"
32 #include "intel_drv.h"
33 #include "i915_drm.h"
34 #include "i915_drv.h"
35 #include "drm_dp_helper.h"
36
37 #include "drm_crtc_helper.h"
38
39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
40
41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
42 static void intel_update_watermarks(struct drm_device *dev);
43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
44
45 typedef struct {
46 /* given values */
47 int n;
48 int m1, m2;
49 int p1, p2;
50 /* derived values */
51 int dot;
52 int vco;
53 int m;
54 int p;
55 } intel_clock_t;
56
57 typedef struct {
58 int min, max;
59 } intel_range_t;
60
61 typedef struct {
62 int dot_limit;
63 int p2_slow, p2_fast;
64 } intel_p2_t;
65
66 #define INTEL_P2_NUM 2
67 typedef struct intel_limit intel_limit_t;
68 struct intel_limit {
69 intel_range_t dot, vco, n, m, m1, m2, p, p1;
70 intel_p2_t p2;
71 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
72 int, int, intel_clock_t *);
73 };
74
75 #define I8XX_DOT_MIN 25000
76 #define I8XX_DOT_MAX 350000
77 #define I8XX_VCO_MIN 930000
78 #define I8XX_VCO_MAX 1400000
79 #define I8XX_N_MIN 3
80 #define I8XX_N_MAX 16
81 #define I8XX_M_MIN 96
82 #define I8XX_M_MAX 140
83 #define I8XX_M1_MIN 18
84 #define I8XX_M1_MAX 26
85 #define I8XX_M2_MIN 6
86 #define I8XX_M2_MAX 16
87 #define I8XX_P_MIN 4
88 #define I8XX_P_MAX 128
89 #define I8XX_P1_MIN 2
90 #define I8XX_P1_MAX 33
91 #define I8XX_P1_LVDS_MIN 1
92 #define I8XX_P1_LVDS_MAX 6
93 #define I8XX_P2_SLOW 4
94 #define I8XX_P2_FAST 2
95 #define I8XX_P2_LVDS_SLOW 14
96 #define I8XX_P2_LVDS_FAST 7
97 #define I8XX_P2_SLOW_LIMIT 165000
98
99 #define I9XX_DOT_MIN 20000
100 #define I9XX_DOT_MAX 400000
101 #define I9XX_VCO_MIN 1400000
102 #define I9XX_VCO_MAX 2800000
103 #define PINEVIEW_VCO_MIN 1700000
104 #define PINEVIEW_VCO_MAX 3500000
105 #define I9XX_N_MIN 1
106 #define I9XX_N_MAX 6
107 /* Pineview's Ncounter is a ring counter */
108 #define PINEVIEW_N_MIN 3
109 #define PINEVIEW_N_MAX 6
110 #define I9XX_M_MIN 70
111 #define I9XX_M_MAX 120
112 #define PINEVIEW_M_MIN 2
113 #define PINEVIEW_M_MAX 256
114 #define I9XX_M1_MIN 10
115 #define I9XX_M1_MAX 22
116 #define I9XX_M2_MIN 5
117 #define I9XX_M2_MAX 9
118 /* Pineview M1 is reserved, and must be 0 */
119 #define PINEVIEW_M1_MIN 0
120 #define PINEVIEW_M1_MAX 0
121 #define PINEVIEW_M2_MIN 0
122 #define PINEVIEW_M2_MAX 254
123 #define I9XX_P_SDVO_DAC_MIN 5
124 #define I9XX_P_SDVO_DAC_MAX 80
125 #define I9XX_P_LVDS_MIN 7
126 #define I9XX_P_LVDS_MAX 98
127 #define PINEVIEW_P_LVDS_MIN 7
128 #define PINEVIEW_P_LVDS_MAX 112
129 #define I9XX_P1_MIN 1
130 #define I9XX_P1_MAX 8
131 #define I9XX_P2_SDVO_DAC_SLOW 10
132 #define I9XX_P2_SDVO_DAC_FAST 5
133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
134 #define I9XX_P2_LVDS_SLOW 14
135 #define I9XX_P2_LVDS_FAST 7
136 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
137
138 /*The parameter is for SDVO on G4x platform*/
139 #define G4X_DOT_SDVO_MIN 25000
140 #define G4X_DOT_SDVO_MAX 270000
141 #define G4X_VCO_MIN 1750000
142 #define G4X_VCO_MAX 3500000
143 #define G4X_N_SDVO_MIN 1
144 #define G4X_N_SDVO_MAX 4
145 #define G4X_M_SDVO_MIN 104
146 #define G4X_M_SDVO_MAX 138
147 #define G4X_M1_SDVO_MIN 17
148 #define G4X_M1_SDVO_MAX 23
149 #define G4X_M2_SDVO_MIN 5
150 #define G4X_M2_SDVO_MAX 11
151 #define G4X_P_SDVO_MIN 10
152 #define G4X_P_SDVO_MAX 30
153 #define G4X_P1_SDVO_MIN 1
154 #define G4X_P1_SDVO_MAX 3
155 #define G4X_P2_SDVO_SLOW 10
156 #define G4X_P2_SDVO_FAST 10
157 #define G4X_P2_SDVO_LIMIT 270000
158
159 /*The parameter is for HDMI_DAC on G4x platform*/
160 #define G4X_DOT_HDMI_DAC_MIN 22000
161 #define G4X_DOT_HDMI_DAC_MAX 400000
162 #define G4X_N_HDMI_DAC_MIN 1
163 #define G4X_N_HDMI_DAC_MAX 4
164 #define G4X_M_HDMI_DAC_MIN 104
165 #define G4X_M_HDMI_DAC_MAX 138
166 #define G4X_M1_HDMI_DAC_MIN 16
167 #define G4X_M1_HDMI_DAC_MAX 23
168 #define G4X_M2_HDMI_DAC_MIN 5
169 #define G4X_M2_HDMI_DAC_MAX 11
170 #define G4X_P_HDMI_DAC_MIN 5
171 #define G4X_P_HDMI_DAC_MAX 80
172 #define G4X_P1_HDMI_DAC_MIN 1
173 #define G4X_P1_HDMI_DAC_MAX 8
174 #define G4X_P2_HDMI_DAC_SLOW 10
175 #define G4X_P2_HDMI_DAC_FAST 5
176 #define G4X_P2_HDMI_DAC_LIMIT 165000
177
178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
196
197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
215
216 /*The parameter is for DISPLAY PORT on G4x platform*/
217 #define G4X_DOT_DISPLAY_PORT_MIN 161670
218 #define G4X_DOT_DISPLAY_PORT_MAX 227000
219 #define G4X_N_DISPLAY_PORT_MIN 1
220 #define G4X_N_DISPLAY_PORT_MAX 2
221 #define G4X_M_DISPLAY_PORT_MIN 97
222 #define G4X_M_DISPLAY_PORT_MAX 108
223 #define G4X_M1_DISPLAY_PORT_MIN 0x10
224 #define G4X_M1_DISPLAY_PORT_MAX 0x12
225 #define G4X_M2_DISPLAY_PORT_MIN 0x05
226 #define G4X_M2_DISPLAY_PORT_MAX 0x06
227 #define G4X_P_DISPLAY_PORT_MIN 10
228 #define G4X_P_DISPLAY_PORT_MAX 20
229 #define G4X_P1_DISPLAY_PORT_MIN 1
230 #define G4X_P1_DISPLAY_PORT_MAX 2
231 #define G4X_P2_DISPLAY_PORT_SLOW 10
232 #define G4X_P2_DISPLAY_PORT_FAST 10
233 #define G4X_P2_DISPLAY_PORT_LIMIT 0
234
235 /* Ironlake */
236 /* as we calculate clock using (register_value + 2) for
237 N/M1/M2, so here the range value for them is (actual_value-2).
238 */
239 #define IRONLAKE_DOT_MIN 25000
240 #define IRONLAKE_DOT_MAX 350000
241 #define IRONLAKE_VCO_MIN 1760000
242 #define IRONLAKE_VCO_MAX 3510000
243 #define IRONLAKE_N_MIN 1
244 #define IRONLAKE_N_MAX 6
245 #define IRONLAKE_M_MIN 79
246 #define IRONLAKE_M_MAX 127
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P_SDVO_DAC_MIN 5
252 #define IRONLAKE_P_SDVO_DAC_MAX 80
253 #define IRONLAKE_P_LVDS_MIN 28
254 #define IRONLAKE_P_LVDS_MAX 112
255 #define IRONLAKE_P1_MIN 1
256 #define IRONLAKE_P1_MAX 8
257 #define IRONLAKE_P2_SDVO_DAC_SLOW 10
258 #define IRONLAKE_P2_SDVO_DAC_FAST 5
259 #define IRONLAKE_P2_LVDS_SLOW 14 /* single channel */
260 #define IRONLAKE_P2_LVDS_FAST 7 /* double channel */
261 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
262
263 #define IRONLAKE_P_DISPLAY_PORT_MIN 10
264 #define IRONLAKE_P_DISPLAY_PORT_MAX 20
265 #define IRONLAKE_P2_DISPLAY_PORT_FAST 10
266 #define IRONLAKE_P2_DISPLAY_PORT_SLOW 10
267 #define IRONLAKE_P2_DISPLAY_PORT_LIMIT 0
268 #define IRONLAKE_P1_DISPLAY_PORT_MIN 1
269 #define IRONLAKE_P1_DISPLAY_PORT_MAX 2
270
271 static bool
272 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
273 int target, int refclk, intel_clock_t *best_clock);
274 static bool
275 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
276 int target, int refclk, intel_clock_t *best_clock);
277
278 static bool
279 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
280 int target, int refclk, intel_clock_t *best_clock);
281 static bool
282 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
283 int target, int refclk, intel_clock_t *best_clock);
284
285 static const intel_limit_t intel_limits_i8xx_dvo = {
286 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
287 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
288 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
289 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
290 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
291 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
292 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
293 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
294 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
295 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
296 .find_pll = intel_find_best_PLL,
297 };
298
299 static const intel_limit_t intel_limits_i8xx_lvds = {
300 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
301 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
302 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
303 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
304 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
305 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
306 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
307 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
308 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
309 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
310 .find_pll = intel_find_best_PLL,
311 };
312
313 static const intel_limit_t intel_limits_i9xx_sdvo = {
314 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
315 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
316 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
317 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
318 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
319 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
320 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
321 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
322 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
323 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
324 .find_pll = intel_find_best_PLL,
325 };
326
327 static const intel_limit_t intel_limits_i9xx_lvds = {
328 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
329 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
330 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
331 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
332 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
333 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
334 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
335 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
336 /* The single-channel range is 25-112Mhz, and dual-channel
337 * is 80-224Mhz. Prefer single channel as much as possible.
338 */
339 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
340 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
341 .find_pll = intel_find_best_PLL,
342 };
343
344 /* below parameter and function is for G4X Chipset Family*/
345 static const intel_limit_t intel_limits_g4x_sdvo = {
346 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
347 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
348 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
349 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
350 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
351 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
352 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
353 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
354 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
355 .p2_slow = G4X_P2_SDVO_SLOW,
356 .p2_fast = G4X_P2_SDVO_FAST
357 },
358 .find_pll = intel_g4x_find_best_PLL,
359 };
360
361 static const intel_limit_t intel_limits_g4x_hdmi = {
362 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
363 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
364 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
365 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
366 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
367 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
368 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
369 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
370 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
371 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
372 .p2_fast = G4X_P2_HDMI_DAC_FAST
373 },
374 .find_pll = intel_g4x_find_best_PLL,
375 };
376
377 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
378 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
379 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
380 .vco = { .min = G4X_VCO_MIN,
381 .max = G4X_VCO_MAX },
382 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
383 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
384 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
385 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
386 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
387 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
388 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
389 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
390 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
391 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
392 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
393 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
394 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
395 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
396 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
397 },
398 .find_pll = intel_g4x_find_best_PLL,
399 };
400
401 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
402 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
403 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
404 .vco = { .min = G4X_VCO_MIN,
405 .max = G4X_VCO_MAX },
406 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
407 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
408 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
409 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
410 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
411 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
412 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
413 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
414 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
415 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
416 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
417 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
418 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
419 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
420 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
421 },
422 .find_pll = intel_g4x_find_best_PLL,
423 };
424
425 static const intel_limit_t intel_limits_g4x_display_port = {
426 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
427 .max = G4X_DOT_DISPLAY_PORT_MAX },
428 .vco = { .min = G4X_VCO_MIN,
429 .max = G4X_VCO_MAX},
430 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
431 .max = G4X_N_DISPLAY_PORT_MAX },
432 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
433 .max = G4X_M_DISPLAY_PORT_MAX },
434 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
435 .max = G4X_M1_DISPLAY_PORT_MAX },
436 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
437 .max = G4X_M2_DISPLAY_PORT_MAX },
438 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
439 .max = G4X_P_DISPLAY_PORT_MAX },
440 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
441 .max = G4X_P1_DISPLAY_PORT_MAX},
442 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
443 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
444 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
445 .find_pll = intel_find_pll_g4x_dp,
446 };
447
448 static const intel_limit_t intel_limits_pineview_sdvo = {
449 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
450 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
451 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
452 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
453 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
454 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
455 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
456 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
457 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
458 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
459 .find_pll = intel_find_best_PLL,
460 };
461
462 static const intel_limit_t intel_limits_pineview_lvds = {
463 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
464 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
465 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
466 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
467 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
468 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
469 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
470 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
471 /* Pineview only supports single-channel mode. */
472 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
473 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
474 .find_pll = intel_find_best_PLL,
475 };
476
477 static const intel_limit_t intel_limits_ironlake_sdvo = {
478 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
479 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
480 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
481 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
482 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
483 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
484 .p = { .min = IRONLAKE_P_SDVO_DAC_MIN, .max = IRONLAKE_P_SDVO_DAC_MAX },
485 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
486 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
487 .p2_slow = IRONLAKE_P2_SDVO_DAC_SLOW,
488 .p2_fast = IRONLAKE_P2_SDVO_DAC_FAST },
489 .find_pll = intel_g4x_find_best_PLL,
490 };
491
492 static const intel_limit_t intel_limits_ironlake_lvds = {
493 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
494 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
495 .n = { .min = IRONLAKE_N_MIN, .max = IRONLAKE_N_MAX },
496 .m = { .min = IRONLAKE_M_MIN, .max = IRONLAKE_M_MAX },
497 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
498 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
499 .p = { .min = IRONLAKE_P_LVDS_MIN, .max = IRONLAKE_P_LVDS_MAX },
500 .p1 = { .min = IRONLAKE_P1_MIN, .max = IRONLAKE_P1_MAX },
501 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
502 .p2_slow = IRONLAKE_P2_LVDS_SLOW,
503 .p2_fast = IRONLAKE_P2_LVDS_FAST },
504 .find_pll = intel_g4x_find_best_PLL,
505 };
506
507 static const intel_limit_t intel_limits_ironlake_display_port = {
508 .dot = { .min = IRONLAKE_DOT_MIN,
509 .max = IRONLAKE_DOT_MAX },
510 .vco = { .min = IRONLAKE_VCO_MIN,
511 .max = IRONLAKE_VCO_MAX},
512 .n = { .min = IRONLAKE_N_MIN,
513 .max = IRONLAKE_N_MAX },
514 .m = { .min = IRONLAKE_M_MIN,
515 .max = IRONLAKE_M_MAX },
516 .m1 = { .min = IRONLAKE_M1_MIN,
517 .max = IRONLAKE_M1_MAX },
518 .m2 = { .min = IRONLAKE_M2_MIN,
519 .max = IRONLAKE_M2_MAX },
520 .p = { .min = IRONLAKE_P_DISPLAY_PORT_MIN,
521 .max = IRONLAKE_P_DISPLAY_PORT_MAX },
522 .p1 = { .min = IRONLAKE_P1_DISPLAY_PORT_MIN,
523 .max = IRONLAKE_P1_DISPLAY_PORT_MAX},
524 .p2 = { .dot_limit = IRONLAKE_P2_DISPLAY_PORT_LIMIT,
525 .p2_slow = IRONLAKE_P2_DISPLAY_PORT_SLOW,
526 .p2_fast = IRONLAKE_P2_DISPLAY_PORT_FAST },
527 .find_pll = intel_find_pll_ironlake_dp,
528 };
529
530 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
531 {
532 const intel_limit_t *limit;
533 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
534 limit = &intel_limits_ironlake_lvds;
535 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
536 HAS_eDP)
537 limit = &intel_limits_ironlake_display_port;
538 else
539 limit = &intel_limits_ironlake_sdvo;
540
541 return limit;
542 }
543
544 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
545 {
546 struct drm_device *dev = crtc->dev;
547 struct drm_i915_private *dev_priv = dev->dev_private;
548 const intel_limit_t *limit;
549
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
551 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
552 LVDS_CLKB_POWER_UP)
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_dual_channel_lvds;
555 else
556 /* LVDS with dual channel */
557 limit = &intel_limits_g4x_single_channel_lvds;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
559 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
560 limit = &intel_limits_g4x_hdmi;
561 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
562 limit = &intel_limits_g4x_sdvo;
563 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
564 limit = &intel_limits_g4x_display_port;
565 } else /* The option is for other outputs */
566 limit = &intel_limits_i9xx_sdvo;
567
568 return limit;
569 }
570
571 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
572 {
573 struct drm_device *dev = crtc->dev;
574 const intel_limit_t *limit;
575
576 if (IS_IRONLAKE(dev))
577 limit = intel_ironlake_limit(crtc);
578 else if (IS_G4X(dev)) {
579 limit = intel_g4x_limit(crtc);
580 } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
581 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
582 limit = &intel_limits_i9xx_lvds;
583 else
584 limit = &intel_limits_i9xx_sdvo;
585 } else if (IS_PINEVIEW(dev)) {
586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
587 limit = &intel_limits_pineview_lvds;
588 else
589 limit = &intel_limits_pineview_sdvo;
590 } else {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
592 limit = &intel_limits_i8xx_lvds;
593 else
594 limit = &intel_limits_i8xx_dvo;
595 }
596 return limit;
597 }
598
599 /* m1 is reserved as 0 in Pineview, n is a ring counter */
600 static void pineview_clock(int refclk, intel_clock_t *clock)
601 {
602 clock->m = clock->m2 + 2;
603 clock->p = clock->p1 * clock->p2;
604 clock->vco = refclk * clock->m / clock->n;
605 clock->dot = clock->vco / clock->p;
606 }
607
608 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
609 {
610 if (IS_PINEVIEW(dev)) {
611 pineview_clock(refclk, clock);
612 return;
613 }
614 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / (clock->n + 2);
617 clock->dot = clock->vco / clock->p;
618 }
619
620 /**
621 * Returns whether any output on the specified pipe is of the specified type
622 */
623 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
624 {
625 struct drm_device *dev = crtc->dev;
626 struct drm_mode_config *mode_config = &dev->mode_config;
627 struct drm_connector *l_entry;
628
629 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
630 if (l_entry->encoder &&
631 l_entry->encoder->crtc == crtc) {
632 struct intel_output *intel_output = to_intel_output(l_entry);
633 if (intel_output->type == type)
634 return true;
635 }
636 }
637 return false;
638 }
639
640 struct drm_connector *
641 intel_pipe_get_output (struct drm_crtc *crtc)
642 {
643 struct drm_device *dev = crtc->dev;
644 struct drm_mode_config *mode_config = &dev->mode_config;
645 struct drm_connector *l_entry, *ret = NULL;
646
647 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
648 if (l_entry->encoder &&
649 l_entry->encoder->crtc == crtc) {
650 ret = l_entry;
651 break;
652 }
653 }
654 return ret;
655 }
656
657 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
658 /**
659 * Returns whether the given set of divisors are valid for a given refclk with
660 * the given connectors.
661 */
662
663 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
664 {
665 const intel_limit_t *limit = intel_limit (crtc);
666 struct drm_device *dev = crtc->dev;
667
668 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
669 INTELPllInvalid ("p1 out of range\n");
670 if (clock->p < limit->p.min || limit->p.max < clock->p)
671 INTELPllInvalid ("p out of range\n");
672 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
673 INTELPllInvalid ("m2 out of range\n");
674 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
675 INTELPllInvalid ("m1 out of range\n");
676 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
677 INTELPllInvalid ("m1 <= m2\n");
678 if (clock->m < limit->m.min || limit->m.max < clock->m)
679 INTELPllInvalid ("m out of range\n");
680 if (clock->n < limit->n.min || limit->n.max < clock->n)
681 INTELPllInvalid ("n out of range\n");
682 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
683 INTELPllInvalid ("vco out of range\n");
684 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
685 * connector, etc., rather than just a single range.
686 */
687 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
688 INTELPllInvalid ("dot out of range\n");
689
690 return true;
691 }
692
693 static bool
694 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
695 int target, int refclk, intel_clock_t *best_clock)
696
697 {
698 struct drm_device *dev = crtc->dev;
699 struct drm_i915_private *dev_priv = dev->dev_private;
700 intel_clock_t clock;
701 int err = target;
702
703 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
704 (I915_READ(LVDS)) != 0) {
705 /*
706 * For LVDS, if the panel is on, just rely on its current
707 * settings for dual-channel. We haven't figured out how to
708 * reliably set up different single/dual channel state, if we
709 * even can.
710 */
711 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
712 LVDS_CLKB_POWER_UP)
713 clock.p2 = limit->p2.p2_fast;
714 else
715 clock.p2 = limit->p2.p2_slow;
716 } else {
717 if (target < limit->p2.dot_limit)
718 clock.p2 = limit->p2.p2_slow;
719 else
720 clock.p2 = limit->p2.p2_fast;
721 }
722
723 memset (best_clock, 0, sizeof (*best_clock));
724
725 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
726 clock.m1++) {
727 for (clock.m2 = limit->m2.min;
728 clock.m2 <= limit->m2.max; clock.m2++) {
729 /* m1 is always 0 in Pineview */
730 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
731 break;
732 for (clock.n = limit->n.min;
733 clock.n <= limit->n.max; clock.n++) {
734 for (clock.p1 = limit->p1.min;
735 clock.p1 <= limit->p1.max; clock.p1++) {
736 int this_err;
737
738 intel_clock(dev, refclk, &clock);
739
740 if (!intel_PLL_is_valid(crtc, &clock))
741 continue;
742
743 this_err = abs(clock.dot - target);
744 if (this_err < err) {
745 *best_clock = clock;
746 err = this_err;
747 }
748 }
749 }
750 }
751 }
752
753 return (err != target);
754 }
755
756 static bool
757 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
758 int target, int refclk, intel_clock_t *best_clock)
759 {
760 struct drm_device *dev = crtc->dev;
761 struct drm_i915_private *dev_priv = dev->dev_private;
762 intel_clock_t clock;
763 int max_n;
764 bool found;
765 /* approximately equals target * 0.00488 */
766 int err_most = (target >> 8) + (target >> 10);
767 found = false;
768
769 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
770 int lvds_reg;
771
772 if (IS_IRONLAKE(dev))
773 lvds_reg = PCH_LVDS;
774 else
775 lvds_reg = LVDS;
776 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
777 LVDS_CLKB_POWER_UP)
778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
790 /* based on hardware requriment prefer smaller n to precision */
791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
792 /* based on hardware requirment prefere larger m1,m2 */
793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
801 intel_clock(dev, refclk, &clock);
802 if (!intel_PLL_is_valid(crtc, &clock))
803 continue;
804 this_err = abs(clock.dot - target) ;
805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
815 return found;
816 }
817
818 static bool
819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
820 int target, int refclk, intel_clock_t *best_clock)
821 {
822 struct drm_device *dev = crtc->dev;
823 intel_clock_t clock;
824
825 /* return directly when it is eDP */
826 if (HAS_eDP)
827 return true;
828
829 if (target < 200000) {
830 clock.n = 1;
831 clock.p1 = 2;
832 clock.p2 = 10;
833 clock.m1 = 12;
834 clock.m2 = 9;
835 } else {
836 clock.n = 2;
837 clock.p1 = 1;
838 clock.p2 = 10;
839 clock.m1 = 14;
840 clock.m2 = 8;
841 }
842 intel_clock(dev, refclk, &clock);
843 memcpy(best_clock, &clock, sizeof(intel_clock_t));
844 return true;
845 }
846
847 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
848 static bool
849 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
850 int target, int refclk, intel_clock_t *best_clock)
851 {
852 intel_clock_t clock;
853 if (target < 200000) {
854 clock.p1 = 2;
855 clock.p2 = 10;
856 clock.n = 2;
857 clock.m1 = 23;
858 clock.m2 = 8;
859 } else {
860 clock.p1 = 1;
861 clock.p2 = 10;
862 clock.n = 1;
863 clock.m1 = 14;
864 clock.m2 = 2;
865 }
866 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
867 clock.p = (clock.p1 * clock.p2);
868 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
869 clock.vco = 0;
870 memcpy(best_clock, &clock, sizeof(intel_clock_t));
871 return true;
872 }
873
874 void
875 intel_wait_for_vblank(struct drm_device *dev)
876 {
877 /* Wait for 20ms, i.e. one cycle at 50hz. */
878 msleep(20);
879 }
880
881 /* Parameters have changed, update FBC info */
882 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
883 {
884 struct drm_device *dev = crtc->dev;
885 struct drm_i915_private *dev_priv = dev->dev_private;
886 struct drm_framebuffer *fb = crtc->fb;
887 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
888 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890 int plane, i;
891 u32 fbc_ctl, fbc_ctl2;
892
893 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
894
895 if (fb->pitch < dev_priv->cfb_pitch)
896 dev_priv->cfb_pitch = fb->pitch;
897
898 /* FBC_CTL wants 64B units */
899 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
900 dev_priv->cfb_fence = obj_priv->fence_reg;
901 dev_priv->cfb_plane = intel_crtc->plane;
902 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
903
904 /* Clear old tags */
905 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
906 I915_WRITE(FBC_TAG + (i * 4), 0);
907
908 /* Set it up... */
909 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
910 if (obj_priv->tiling_mode != I915_TILING_NONE)
911 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
912 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
913 I915_WRITE(FBC_FENCE_OFF, crtc->y);
914
915 /* enable it... */
916 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
917 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
918 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
919 if (obj_priv->tiling_mode != I915_TILING_NONE)
920 fbc_ctl |= dev_priv->cfb_fence;
921 I915_WRITE(FBC_CONTROL, fbc_ctl);
922
923 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
924 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
925 }
926
927 void i8xx_disable_fbc(struct drm_device *dev)
928 {
929 struct drm_i915_private *dev_priv = dev->dev_private;
930 u32 fbc_ctl;
931
932 if (!I915_HAS_FBC(dev))
933 return;
934
935 /* Disable compression */
936 fbc_ctl = I915_READ(FBC_CONTROL);
937 fbc_ctl &= ~FBC_CTL_EN;
938 I915_WRITE(FBC_CONTROL, fbc_ctl);
939
940 /* Wait for compressing bit to clear */
941 while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
942 ; /* nothing */
943
944 intel_wait_for_vblank(dev);
945
946 DRM_DEBUG_KMS("disabled FBC\n");
947 }
948
949 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
950 {
951 struct drm_device *dev = crtc->dev;
952 struct drm_i915_private *dev_priv = dev->dev_private;
953
954 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
955 }
956
957 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
958 {
959 struct drm_device *dev = crtc->dev;
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 struct drm_framebuffer *fb = crtc->fb;
962 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
963 struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
965 int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
966 DPFC_CTL_PLANEB);
967 unsigned long stall_watermark = 200;
968 u32 dpfc_ctl;
969
970 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
971 dev_priv->cfb_fence = obj_priv->fence_reg;
972 dev_priv->cfb_plane = intel_crtc->plane;
973
974 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
975 if (obj_priv->tiling_mode != I915_TILING_NONE) {
976 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
977 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
978 } else {
979 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
980 }
981
982 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
983 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
984 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
985 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
986 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
987
988 /* enable it... */
989 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
990
991 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
992 }
993
994 void g4x_disable_fbc(struct drm_device *dev)
995 {
996 struct drm_i915_private *dev_priv = dev->dev_private;
997 u32 dpfc_ctl;
998
999 /* Disable compression */
1000 dpfc_ctl = I915_READ(DPFC_CONTROL);
1001 dpfc_ctl &= ~DPFC_CTL_EN;
1002 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1003 intel_wait_for_vblank(dev);
1004
1005 DRM_DEBUG_KMS("disabled FBC\n");
1006 }
1007
1008 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1009 {
1010 struct drm_device *dev = crtc->dev;
1011 struct drm_i915_private *dev_priv = dev->dev_private;
1012
1013 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1014 }
1015
1016 /**
1017 * intel_update_fbc - enable/disable FBC as needed
1018 * @crtc: CRTC to point the compressor at
1019 * @mode: mode in use
1020 *
1021 * Set up the framebuffer compression hardware at mode set time. We
1022 * enable it if possible:
1023 * - plane A only (on pre-965)
1024 * - no pixel mulitply/line duplication
1025 * - no alpha buffer discard
1026 * - no dual wide
1027 * - framebuffer <= 2048 in width, 1536 in height
1028 *
1029 * We can't assume that any compression will take place (worst case),
1030 * so the compressed buffer has to be the same size as the uncompressed
1031 * one. It also must reside (along with the line length buffer) in
1032 * stolen memory.
1033 *
1034 * We need to enable/disable FBC on a global basis.
1035 */
1036 static void intel_update_fbc(struct drm_crtc *crtc,
1037 struct drm_display_mode *mode)
1038 {
1039 struct drm_device *dev = crtc->dev;
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1041 struct drm_framebuffer *fb = crtc->fb;
1042 struct intel_framebuffer *intel_fb;
1043 struct drm_i915_gem_object *obj_priv;
1044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1045 int plane = intel_crtc->plane;
1046
1047 if (!i915_powersave)
1048 return;
1049
1050 if (!dev_priv->display.fbc_enabled ||
1051 !dev_priv->display.enable_fbc ||
1052 !dev_priv->display.disable_fbc)
1053 return;
1054
1055 if (!crtc->fb)
1056 return;
1057
1058 intel_fb = to_intel_framebuffer(fb);
1059 obj_priv = intel_fb->obj->driver_private;
1060
1061 /*
1062 * If FBC is already on, we just have to verify that we can
1063 * keep it that way...
1064 * Need to disable if:
1065 * - changing FBC params (stride, fence, mode)
1066 * - new fb is too large to fit in compressed buffer
1067 * - going to an unsupported config (interlace, pixel multiply, etc.)
1068 */
1069 if (intel_fb->obj->size > dev_priv->cfb_size) {
1070 DRM_DEBUG_KMS("framebuffer too large, disabling "
1071 "compression\n");
1072 goto out_disable;
1073 }
1074 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1075 (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1076 DRM_DEBUG_KMS("mode incompatible with compression, "
1077 "disabling\n");
1078 goto out_disable;
1079 }
1080 if ((mode->hdisplay > 2048) ||
1081 (mode->vdisplay > 1536)) {
1082 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1083 goto out_disable;
1084 }
1085 if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1086 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1087 goto out_disable;
1088 }
1089 if (obj_priv->tiling_mode != I915_TILING_X) {
1090 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1091 goto out_disable;
1092 }
1093
1094 if (dev_priv->display.fbc_enabled(crtc)) {
1095 /* We can re-enable it in this case, but need to update pitch */
1096 if (fb->pitch > dev_priv->cfb_pitch)
1097 dev_priv->display.disable_fbc(dev);
1098 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1099 dev_priv->display.disable_fbc(dev);
1100 if (plane != dev_priv->cfb_plane)
1101 dev_priv->display.disable_fbc(dev);
1102 }
1103
1104 if (!dev_priv->display.fbc_enabled(crtc)) {
1105 /* Now try to turn it back on if possible */
1106 dev_priv->display.enable_fbc(crtc, 500);
1107 }
1108
1109 return;
1110
1111 out_disable:
1112 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1113 /* Multiple disables should be harmless */
1114 if (dev_priv->display.fbc_enabled(crtc))
1115 dev_priv->display.disable_fbc(dev);
1116 }
1117
1118 static int
1119 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1120 {
1121 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1122 u32 alignment;
1123 int ret;
1124
1125 switch (obj_priv->tiling_mode) {
1126 case I915_TILING_NONE:
1127 alignment = 64 * 1024;
1128 break;
1129 case I915_TILING_X:
1130 /* pin() will align the object as required by fence */
1131 alignment = 0;
1132 break;
1133 case I915_TILING_Y:
1134 /* FIXME: Is this true? */
1135 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1136 return -EINVAL;
1137 default:
1138 BUG();
1139 }
1140
1141 ret = i915_gem_object_pin(obj, alignment);
1142 if (ret != 0)
1143 return ret;
1144
1145 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1146 * fence, whereas 965+ only requires a fence if using
1147 * framebuffer compression. For simplicity, we always install
1148 * a fence as the cost is not that onerous.
1149 */
1150 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1151 obj_priv->tiling_mode != I915_TILING_NONE) {
1152 ret = i915_gem_object_get_fence_reg(obj);
1153 if (ret != 0) {
1154 i915_gem_object_unpin(obj);
1155 return ret;
1156 }
1157 }
1158
1159 return 0;
1160 }
1161
1162 static int
1163 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1164 struct drm_framebuffer *old_fb)
1165 {
1166 struct drm_device *dev = crtc->dev;
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 struct drm_i915_master_private *master_priv;
1169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1170 struct intel_framebuffer *intel_fb;
1171 struct drm_i915_gem_object *obj_priv;
1172 struct drm_gem_object *obj;
1173 int pipe = intel_crtc->pipe;
1174 int plane = intel_crtc->plane;
1175 unsigned long Start, Offset;
1176 int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1177 int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1178 int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1179 int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1180 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1181 u32 dspcntr;
1182 int ret;
1183
1184 /* no fb bound */
1185 if (!crtc->fb) {
1186 DRM_DEBUG_KMS("No FB bound\n");
1187 return 0;
1188 }
1189
1190 switch (plane) {
1191 case 0:
1192 case 1:
1193 break;
1194 default:
1195 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1196 return -EINVAL;
1197 }
1198
1199 intel_fb = to_intel_framebuffer(crtc->fb);
1200 obj = intel_fb->obj;
1201 obj_priv = obj->driver_private;
1202
1203 mutex_lock(&dev->struct_mutex);
1204 ret = intel_pin_and_fence_fb_obj(dev, obj);
1205 if (ret != 0) {
1206 mutex_unlock(&dev->struct_mutex);
1207 return ret;
1208 }
1209
1210 ret = i915_gem_object_set_to_display_plane(obj);
1211 if (ret != 0) {
1212 i915_gem_object_unpin(obj);
1213 mutex_unlock(&dev->struct_mutex);
1214 return ret;
1215 }
1216
1217 dspcntr = I915_READ(dspcntr_reg);
1218 /* Mask out pixel format bits in case we change it */
1219 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1220 switch (crtc->fb->bits_per_pixel) {
1221 case 8:
1222 dspcntr |= DISPPLANE_8BPP;
1223 break;
1224 case 16:
1225 if (crtc->fb->depth == 15)
1226 dspcntr |= DISPPLANE_15_16BPP;
1227 else
1228 dspcntr |= DISPPLANE_16BPP;
1229 break;
1230 case 24:
1231 case 32:
1232 if (crtc->fb->depth == 30)
1233 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1234 else
1235 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1236 break;
1237 default:
1238 DRM_ERROR("Unknown color depth\n");
1239 i915_gem_object_unpin(obj);
1240 mutex_unlock(&dev->struct_mutex);
1241 return -EINVAL;
1242 }
1243 if (IS_I965G(dev)) {
1244 if (obj_priv->tiling_mode != I915_TILING_NONE)
1245 dspcntr |= DISPPLANE_TILED;
1246 else
1247 dspcntr &= ~DISPPLANE_TILED;
1248 }
1249
1250 if (IS_IRONLAKE(dev))
1251 /* must disable */
1252 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1253
1254 I915_WRITE(dspcntr_reg, dspcntr);
1255
1256 Start = obj_priv->gtt_offset;
1257 Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1258
1259 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1260 I915_WRITE(dspstride, crtc->fb->pitch);
1261 if (IS_I965G(dev)) {
1262 I915_WRITE(dspbase, Offset);
1263 I915_READ(dspbase);
1264 I915_WRITE(dspsurf, Start);
1265 I915_READ(dspsurf);
1266 I915_WRITE(dsptileoff, (y << 16) | x);
1267 } else {
1268 I915_WRITE(dspbase, Start + Offset);
1269 I915_READ(dspbase);
1270 }
1271
1272 if ((IS_I965G(dev) || plane == 0))
1273 intel_update_fbc(crtc, &crtc->mode);
1274
1275 intel_wait_for_vblank(dev);
1276
1277 if (old_fb) {
1278 intel_fb = to_intel_framebuffer(old_fb);
1279 obj_priv = intel_fb->obj->driver_private;
1280 i915_gem_object_unpin(intel_fb->obj);
1281 }
1282 intel_increase_pllclock(crtc, true);
1283
1284 mutex_unlock(&dev->struct_mutex);
1285
1286 if (!dev->primary->master)
1287 return 0;
1288
1289 master_priv = dev->primary->master->driver_priv;
1290 if (!master_priv->sarea_priv)
1291 return 0;
1292
1293 if (pipe) {
1294 master_priv->sarea_priv->pipeB_x = x;
1295 master_priv->sarea_priv->pipeB_y = y;
1296 } else {
1297 master_priv->sarea_priv->pipeA_x = x;
1298 master_priv->sarea_priv->pipeA_y = y;
1299 }
1300
1301 return 0;
1302 }
1303
1304 /* Disable the VGA plane that we never use */
1305 static void i915_disable_vga (struct drm_device *dev)
1306 {
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 u8 sr1;
1309 u32 vga_reg;
1310
1311 if (IS_IRONLAKE(dev))
1312 vga_reg = CPU_VGACNTRL;
1313 else
1314 vga_reg = VGACNTRL;
1315
1316 if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1317 return;
1318
1319 I915_WRITE8(VGA_SR_INDEX, 1);
1320 sr1 = I915_READ8(VGA_SR_DATA);
1321 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1322 udelay(100);
1323
1324 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1325 }
1326
1327 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1328 {
1329 struct drm_device *dev = crtc->dev;
1330 struct drm_i915_private *dev_priv = dev->dev_private;
1331 u32 dpa_ctl;
1332
1333 DRM_DEBUG_KMS("\n");
1334 dpa_ctl = I915_READ(DP_A);
1335 dpa_ctl &= ~DP_PLL_ENABLE;
1336 I915_WRITE(DP_A, dpa_ctl);
1337 }
1338
1339 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1340 {
1341 struct drm_device *dev = crtc->dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 u32 dpa_ctl;
1344
1345 dpa_ctl = I915_READ(DP_A);
1346 dpa_ctl |= DP_PLL_ENABLE;
1347 I915_WRITE(DP_A, dpa_ctl);
1348 udelay(200);
1349 }
1350
1351
1352 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1353 {
1354 struct drm_device *dev = crtc->dev;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 u32 dpa_ctl;
1357
1358 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1359 dpa_ctl = I915_READ(DP_A);
1360 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1361
1362 if (clock < 200000) {
1363 u32 temp;
1364 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1365 /* workaround for 160Mhz:
1366 1) program 0x4600c bits 15:0 = 0x8124
1367 2) program 0x46010 bit 0 = 1
1368 3) program 0x46034 bit 24 = 1
1369 4) program 0x64000 bit 14 = 1
1370 */
1371 temp = I915_READ(0x4600c);
1372 temp &= 0xffff0000;
1373 I915_WRITE(0x4600c, temp | 0x8124);
1374
1375 temp = I915_READ(0x46010);
1376 I915_WRITE(0x46010, temp | 1);
1377
1378 temp = I915_READ(0x46034);
1379 I915_WRITE(0x46034, temp | (1 << 24));
1380 } else {
1381 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1382 }
1383 I915_WRITE(DP_A, dpa_ctl);
1384
1385 udelay(500);
1386 }
1387
1388 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1389 {
1390 struct drm_device *dev = crtc->dev;
1391 struct drm_i915_private *dev_priv = dev->dev_private;
1392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1393 int pipe = intel_crtc->pipe;
1394 int plane = intel_crtc->plane;
1395 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1396 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1397 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1398 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1399 int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1400 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1401 int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1402 int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1403 int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1404 int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1405 int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1406 int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1407 int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1408 int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1409 int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1410 int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1411 int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1412 int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1413 int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1414 int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1415 int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1416 int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1417 int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1418 int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1419 u32 temp;
1420 int tries = 5, j, n;
1421 u32 pipe_bpc;
1422
1423 temp = I915_READ(pipeconf_reg);
1424 pipe_bpc = temp & PIPE_BPC_MASK;
1425
1426 /* XXX: When our outputs are all unaware of DPMS modes other than off
1427 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1428 */
1429 switch (mode) {
1430 case DRM_MODE_DPMS_ON:
1431 case DRM_MODE_DPMS_STANDBY:
1432 case DRM_MODE_DPMS_SUSPEND:
1433 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1434
1435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1436 temp = I915_READ(PCH_LVDS);
1437 if ((temp & LVDS_PORT_EN) == 0) {
1438 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1439 POSTING_READ(PCH_LVDS);
1440 }
1441 }
1442
1443 if (HAS_eDP) {
1444 /* enable eDP PLL */
1445 ironlake_enable_pll_edp(crtc);
1446 } else {
1447 /* enable PCH DPLL */
1448 temp = I915_READ(pch_dpll_reg);
1449 if ((temp & DPLL_VCO_ENABLE) == 0) {
1450 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1451 I915_READ(pch_dpll_reg);
1452 }
1453
1454 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1455 temp = I915_READ(fdi_rx_reg);
1456 /*
1457 * make the BPC in FDI Rx be consistent with that in
1458 * pipeconf reg.
1459 */
1460 temp &= ~(0x7 << 16);
1461 temp |= (pipe_bpc << 11);
1462 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1463 FDI_SEL_PCDCLK |
1464 FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1465 I915_READ(fdi_rx_reg);
1466 udelay(200);
1467
1468 /* Enable CPU FDI TX PLL, always on for Ironlake */
1469 temp = I915_READ(fdi_tx_reg);
1470 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1471 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1472 I915_READ(fdi_tx_reg);
1473 udelay(100);
1474 }
1475 }
1476
1477 /* Enable panel fitting for LVDS */
1478 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1479 temp = I915_READ(pf_ctl_reg);
1480 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1481
1482 /* currently full aspect */
1483 I915_WRITE(pf_win_pos, 0);
1484
1485 I915_WRITE(pf_win_size,
1486 (dev_priv->panel_fixed_mode->hdisplay << 16) |
1487 (dev_priv->panel_fixed_mode->vdisplay));
1488 }
1489
1490 /* Enable CPU pipe */
1491 temp = I915_READ(pipeconf_reg);
1492 if ((temp & PIPEACONF_ENABLE) == 0) {
1493 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1494 I915_READ(pipeconf_reg);
1495 udelay(100);
1496 }
1497
1498 /* configure and enable CPU plane */
1499 temp = I915_READ(dspcntr_reg);
1500 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1501 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1502 /* Flush the plane changes */
1503 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1504 }
1505
1506 if (!HAS_eDP) {
1507 /* enable CPU FDI TX and PCH FDI RX */
1508 temp = I915_READ(fdi_tx_reg);
1509 temp |= FDI_TX_ENABLE;
1510 temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1511 temp &= ~FDI_LINK_TRAIN_NONE;
1512 temp |= FDI_LINK_TRAIN_PATTERN_1;
1513 I915_WRITE(fdi_tx_reg, temp);
1514 I915_READ(fdi_tx_reg);
1515
1516 temp = I915_READ(fdi_rx_reg);
1517 temp &= ~FDI_LINK_TRAIN_NONE;
1518 temp |= FDI_LINK_TRAIN_PATTERN_1;
1519 I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1520 I915_READ(fdi_rx_reg);
1521
1522 udelay(150);
1523
1524 /* Train FDI. */
1525 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1526 for train result */
1527 temp = I915_READ(fdi_rx_imr_reg);
1528 temp &= ~FDI_RX_SYMBOL_LOCK;
1529 temp &= ~FDI_RX_BIT_LOCK;
1530 I915_WRITE(fdi_rx_imr_reg, temp);
1531 I915_READ(fdi_rx_imr_reg);
1532 udelay(150);
1533
1534 temp = I915_READ(fdi_rx_iir_reg);
1535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1536
1537 if ((temp & FDI_RX_BIT_LOCK) == 0) {
1538 for (j = 0; j < tries; j++) {
1539 temp = I915_READ(fdi_rx_iir_reg);
1540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1541 temp);
1542 if (temp & FDI_RX_BIT_LOCK)
1543 break;
1544 udelay(200);
1545 }
1546 if (j != tries)
1547 I915_WRITE(fdi_rx_iir_reg,
1548 temp | FDI_RX_BIT_LOCK);
1549 else
1550 DRM_DEBUG_KMS("train 1 fail\n");
1551 } else {
1552 I915_WRITE(fdi_rx_iir_reg,
1553 temp | FDI_RX_BIT_LOCK);
1554 DRM_DEBUG_KMS("train 1 ok 2!\n");
1555 }
1556 temp = I915_READ(fdi_tx_reg);
1557 temp &= ~FDI_LINK_TRAIN_NONE;
1558 temp |= FDI_LINK_TRAIN_PATTERN_2;
1559 I915_WRITE(fdi_tx_reg, temp);
1560
1561 temp = I915_READ(fdi_rx_reg);
1562 temp &= ~FDI_LINK_TRAIN_NONE;
1563 temp |= FDI_LINK_TRAIN_PATTERN_2;
1564 I915_WRITE(fdi_rx_reg, temp);
1565
1566 udelay(150);
1567
1568 temp = I915_READ(fdi_rx_iir_reg);
1569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1570
1571 if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1572 for (j = 0; j < tries; j++) {
1573 temp = I915_READ(fdi_rx_iir_reg);
1574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1575 temp);
1576 if (temp & FDI_RX_SYMBOL_LOCK)
1577 break;
1578 udelay(200);
1579 }
1580 if (j != tries) {
1581 I915_WRITE(fdi_rx_iir_reg,
1582 temp | FDI_RX_SYMBOL_LOCK);
1583 DRM_DEBUG_KMS("train 2 ok 1!\n");
1584 } else
1585 DRM_DEBUG_KMS("train 2 fail\n");
1586 } else {
1587 I915_WRITE(fdi_rx_iir_reg,
1588 temp | FDI_RX_SYMBOL_LOCK);
1589 DRM_DEBUG_KMS("train 2 ok 2!\n");
1590 }
1591 DRM_DEBUG_KMS("train done\n");
1592
1593 /* set transcoder timing */
1594 I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1595 I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1596 I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1597
1598 I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1599 I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1600 I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1601
1602 /* enable PCH transcoder */
1603 temp = I915_READ(transconf_reg);
1604 /*
1605 * make the BPC in transcoder be consistent with
1606 * that in pipeconf reg.
1607 */
1608 temp &= ~PIPE_BPC_MASK;
1609 temp |= pipe_bpc;
1610 I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1611 I915_READ(transconf_reg);
1612
1613 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1614 ;
1615
1616 /* enable normal */
1617
1618 temp = I915_READ(fdi_tx_reg);
1619 temp &= ~FDI_LINK_TRAIN_NONE;
1620 I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1621 FDI_TX_ENHANCE_FRAME_ENABLE);
1622 I915_READ(fdi_tx_reg);
1623
1624 temp = I915_READ(fdi_rx_reg);
1625 temp &= ~FDI_LINK_TRAIN_NONE;
1626 I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1627 FDI_RX_ENHANCE_FRAME_ENABLE);
1628 I915_READ(fdi_rx_reg);
1629
1630 /* wait one idle pattern time */
1631 udelay(100);
1632
1633 }
1634
1635 intel_crtc_load_lut(crtc);
1636
1637 break;
1638 case DRM_MODE_DPMS_OFF:
1639 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1640
1641 /* Disable display plane */
1642 temp = I915_READ(dspcntr_reg);
1643 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1644 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1645 /* Flush the plane changes */
1646 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1647 I915_READ(dspbase_reg);
1648 }
1649
1650 i915_disable_vga(dev);
1651
1652 /* disable cpu pipe, disable after all planes disabled */
1653 temp = I915_READ(pipeconf_reg);
1654 if ((temp & PIPEACONF_ENABLE) != 0) {
1655 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1656 I915_READ(pipeconf_reg);
1657 n = 0;
1658 /* wait for cpu pipe off, pipe state */
1659 while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1660 n++;
1661 if (n < 60) {
1662 udelay(500);
1663 continue;
1664 } else {
1665 DRM_DEBUG_KMS("pipe %d off delay\n",
1666 pipe);
1667 break;
1668 }
1669 }
1670 } else
1671 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1672
1673 udelay(100);
1674
1675 /* Disable PF */
1676 temp = I915_READ(pf_ctl_reg);
1677 if ((temp & PF_ENABLE) != 0) {
1678 I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1679 I915_READ(pf_ctl_reg);
1680 }
1681 I915_WRITE(pf_win_size, 0);
1682
1683 /* disable CPU FDI tx and PCH FDI rx */
1684 temp = I915_READ(fdi_tx_reg);
1685 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1686 I915_READ(fdi_tx_reg);
1687
1688 temp = I915_READ(fdi_rx_reg);
1689 /* BPC in FDI rx is consistent with that in pipeconf */
1690 temp &= ~(0x07 << 16);
1691 temp |= (pipe_bpc << 11);
1692 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1693 I915_READ(fdi_rx_reg);
1694
1695 udelay(100);
1696
1697 /* still set train pattern 1 */
1698 temp = I915_READ(fdi_tx_reg);
1699 temp &= ~FDI_LINK_TRAIN_NONE;
1700 temp |= FDI_LINK_TRAIN_PATTERN_1;
1701 I915_WRITE(fdi_tx_reg, temp);
1702
1703 temp = I915_READ(fdi_rx_reg);
1704 temp &= ~FDI_LINK_TRAIN_NONE;
1705 temp |= FDI_LINK_TRAIN_PATTERN_1;
1706 I915_WRITE(fdi_rx_reg, temp);
1707
1708 udelay(100);
1709
1710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1711 temp = I915_READ(PCH_LVDS);
1712 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1713 I915_READ(PCH_LVDS);
1714 udelay(100);
1715 }
1716
1717 /* disable PCH transcoder */
1718 temp = I915_READ(transconf_reg);
1719 if ((temp & TRANS_ENABLE) != 0) {
1720 I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1721 I915_READ(transconf_reg);
1722 n = 0;
1723 /* wait for PCH transcoder off, transcoder state */
1724 while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1725 n++;
1726 if (n < 60) {
1727 udelay(500);
1728 continue;
1729 } else {
1730 DRM_DEBUG_KMS("transcoder %d off "
1731 "delay\n", pipe);
1732 break;
1733 }
1734 }
1735 }
1736 temp = I915_READ(transconf_reg);
1737 /* BPC in transcoder is consistent with that in pipeconf */
1738 temp &= ~PIPE_BPC_MASK;
1739 temp |= pipe_bpc;
1740 I915_WRITE(transconf_reg, temp);
1741 I915_READ(transconf_reg);
1742 udelay(100);
1743
1744 /* disable PCH DPLL */
1745 temp = I915_READ(pch_dpll_reg);
1746 if ((temp & DPLL_VCO_ENABLE) != 0) {
1747 I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1748 I915_READ(pch_dpll_reg);
1749 }
1750
1751 if (HAS_eDP) {
1752 ironlake_disable_pll_edp(crtc);
1753 }
1754
1755 temp = I915_READ(fdi_rx_reg);
1756 temp &= ~FDI_SEL_PCDCLK;
1757 I915_WRITE(fdi_rx_reg, temp);
1758 I915_READ(fdi_rx_reg);
1759
1760 temp = I915_READ(fdi_rx_reg);
1761 temp &= ~FDI_RX_PLL_ENABLE;
1762 I915_WRITE(fdi_rx_reg, temp);
1763 I915_READ(fdi_rx_reg);
1764
1765 /* Disable CPU FDI TX PLL */
1766 temp = I915_READ(fdi_tx_reg);
1767 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1768 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1769 I915_READ(fdi_tx_reg);
1770 udelay(100);
1771 }
1772
1773 /* Wait for the clocks to turn off. */
1774 udelay(100);
1775 break;
1776 }
1777 }
1778
1779 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1780 {
1781 struct intel_overlay *overlay;
1782 int ret;
1783
1784 if (!enable && intel_crtc->overlay) {
1785 overlay = intel_crtc->overlay;
1786 mutex_lock(&overlay->dev->struct_mutex);
1787 for (;;) {
1788 ret = intel_overlay_switch_off(overlay);
1789 if (ret == 0)
1790 break;
1791
1792 ret = intel_overlay_recover_from_interrupt(overlay, 0);
1793 if (ret != 0) {
1794 /* overlay doesn't react anymore. Usually
1795 * results in a black screen and an unkillable
1796 * X server. */
1797 BUG();
1798 overlay->hw_wedged = HW_WEDGED;
1799 break;
1800 }
1801 }
1802 mutex_unlock(&overlay->dev->struct_mutex);
1803 }
1804 /* Let userspace switch the overlay on again. In most cases userspace
1805 * has to recompute where to put it anyway. */
1806
1807 return;
1808 }
1809
1810 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1811 {
1812 struct drm_device *dev = crtc->dev;
1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1815 int pipe = intel_crtc->pipe;
1816 int plane = intel_crtc->plane;
1817 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1818 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1819 int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1820 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1821 u32 temp;
1822
1823 /* XXX: When our outputs are all unaware of DPMS modes other than off
1824 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1825 */
1826 switch (mode) {
1827 case DRM_MODE_DPMS_ON:
1828 case DRM_MODE_DPMS_STANDBY:
1829 case DRM_MODE_DPMS_SUSPEND:
1830 intel_update_watermarks(dev);
1831
1832 /* Enable the DPLL */
1833 temp = I915_READ(dpll_reg);
1834 if ((temp & DPLL_VCO_ENABLE) == 0) {
1835 I915_WRITE(dpll_reg, temp);
1836 I915_READ(dpll_reg);
1837 /* Wait for the clocks to stabilize. */
1838 udelay(150);
1839 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1840 I915_READ(dpll_reg);
1841 /* Wait for the clocks to stabilize. */
1842 udelay(150);
1843 I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1844 I915_READ(dpll_reg);
1845 /* Wait for the clocks to stabilize. */
1846 udelay(150);
1847 }
1848
1849 /* Enable the pipe */
1850 temp = I915_READ(pipeconf_reg);
1851 if ((temp & PIPEACONF_ENABLE) == 0)
1852 I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1853
1854 /* Enable the plane */
1855 temp = I915_READ(dspcntr_reg);
1856 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1857 I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1858 /* Flush the plane changes */
1859 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1860 }
1861
1862 intel_crtc_load_lut(crtc);
1863
1864 if ((IS_I965G(dev) || plane == 0))
1865 intel_update_fbc(crtc, &crtc->mode);
1866
1867 /* Give the overlay scaler a chance to enable if it's on this pipe */
1868 intel_crtc_dpms_overlay(intel_crtc, true);
1869 break;
1870 case DRM_MODE_DPMS_OFF:
1871 intel_update_watermarks(dev);
1872
1873 /* Give the overlay scaler a chance to disable if it's on this pipe */
1874 intel_crtc_dpms_overlay(intel_crtc, false);
1875 drm_vblank_off(dev, pipe);
1876
1877 if (dev_priv->cfb_plane == plane &&
1878 dev_priv->display.disable_fbc)
1879 dev_priv->display.disable_fbc(dev);
1880
1881 /* Disable the VGA plane that we never use */
1882 i915_disable_vga(dev);
1883
1884 /* Disable display plane */
1885 temp = I915_READ(dspcntr_reg);
1886 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1887 I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1888 /* Flush the plane changes */
1889 I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1890 I915_READ(dspbase_reg);
1891 }
1892
1893 if (!IS_I9XX(dev)) {
1894 /* Wait for vblank for the disable to take effect */
1895 intel_wait_for_vblank(dev);
1896 }
1897
1898 /* Next, disable display pipes */
1899 temp = I915_READ(pipeconf_reg);
1900 if ((temp & PIPEACONF_ENABLE) != 0) {
1901 I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1902 I915_READ(pipeconf_reg);
1903 }
1904
1905 /* Wait for vblank for the disable to take effect. */
1906 intel_wait_for_vblank(dev);
1907
1908 temp = I915_READ(dpll_reg);
1909 if ((temp & DPLL_VCO_ENABLE) != 0) {
1910 I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
1911 I915_READ(dpll_reg);
1912 }
1913
1914 /* Wait for the clocks to turn off. */
1915 udelay(150);
1916 break;
1917 }
1918 }
1919
1920 /**
1921 * Sets the power management mode of the pipe and plane.
1922 *
1923 * This code should probably grow support for turning the cursor off and back
1924 * on appropriately at the same time as we're turning the pipe off/on.
1925 */
1926 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
1927 {
1928 struct drm_device *dev = crtc->dev;
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930 struct drm_i915_master_private *master_priv;
1931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1932 int pipe = intel_crtc->pipe;
1933 bool enabled;
1934
1935 dev_priv->display.dpms(crtc, mode);
1936
1937 intel_crtc->dpms_mode = mode;
1938
1939 if (!dev->primary->master)
1940 return;
1941
1942 master_priv = dev->primary->master->driver_priv;
1943 if (!master_priv->sarea_priv)
1944 return;
1945
1946 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
1947
1948 switch (pipe) {
1949 case 0:
1950 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
1951 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
1952 break;
1953 case 1:
1954 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
1955 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
1956 break;
1957 default:
1958 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
1959 break;
1960 }
1961 }
1962
1963 static void intel_crtc_prepare (struct drm_crtc *crtc)
1964 {
1965 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1966 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1967 }
1968
1969 static void intel_crtc_commit (struct drm_crtc *crtc)
1970 {
1971 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1972 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1973 }
1974
1975 void intel_encoder_prepare (struct drm_encoder *encoder)
1976 {
1977 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1978 /* lvds has its own version of prepare see intel_lvds_prepare */
1979 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
1980 }
1981
1982 void intel_encoder_commit (struct drm_encoder *encoder)
1983 {
1984 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
1985 /* lvds has its own version of commit see intel_lvds_commit */
1986 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
1987 }
1988
1989 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
1990 struct drm_display_mode *mode,
1991 struct drm_display_mode *adjusted_mode)
1992 {
1993 struct drm_device *dev = crtc->dev;
1994 if (IS_IRONLAKE(dev)) {
1995 /* FDI link clock is fixed at 2.7G */
1996 if (mode->clock * 3 > 27000 * 4)
1997 return MODE_CLOCK_HIGH;
1998 }
1999 return true;
2000 }
2001
2002 static int i945_get_display_clock_speed(struct drm_device *dev)
2003 {
2004 return 400000;
2005 }
2006
2007 static int i915_get_display_clock_speed(struct drm_device *dev)
2008 {
2009 return 333000;
2010 }
2011
2012 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2013 {
2014 return 200000;
2015 }
2016
2017 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2018 {
2019 u16 gcfgc = 0;
2020
2021 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2022
2023 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2024 return 133000;
2025 else {
2026 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2027 case GC_DISPLAY_CLOCK_333_MHZ:
2028 return 333000;
2029 default:
2030 case GC_DISPLAY_CLOCK_190_200_MHZ:
2031 return 190000;
2032 }
2033 }
2034 }
2035
2036 static int i865_get_display_clock_speed(struct drm_device *dev)
2037 {
2038 return 266000;
2039 }
2040
2041 static int i855_get_display_clock_speed(struct drm_device *dev)
2042 {
2043 u16 hpllcc = 0;
2044 /* Assume that the hardware is in the high speed state. This
2045 * should be the default.
2046 */
2047 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2048 case GC_CLOCK_133_200:
2049 case GC_CLOCK_100_200:
2050 return 200000;
2051 case GC_CLOCK_166_250:
2052 return 250000;
2053 case GC_CLOCK_100_133:
2054 return 133000;
2055 }
2056
2057 /* Shouldn't happen */
2058 return 0;
2059 }
2060
2061 static int i830_get_display_clock_speed(struct drm_device *dev)
2062 {
2063 return 133000;
2064 }
2065
2066 /**
2067 * Return the pipe currently connected to the panel fitter,
2068 * or -1 if the panel fitter is not present or not in use
2069 */
2070 int intel_panel_fitter_pipe (struct drm_device *dev)
2071 {
2072 struct drm_i915_private *dev_priv = dev->dev_private;
2073 u32 pfit_control;
2074
2075 /* i830 doesn't have a panel fitter */
2076 if (IS_I830(dev))
2077 return -1;
2078
2079 pfit_control = I915_READ(PFIT_CONTROL);
2080
2081 /* See if the panel fitter is in use */
2082 if ((pfit_control & PFIT_ENABLE) == 0)
2083 return -1;
2084
2085 /* 965 can place panel fitter on either pipe */
2086 if (IS_I965G(dev))
2087 return (pfit_control >> 29) & 0x3;
2088
2089 /* older chips can only use pipe 1 */
2090 return 1;
2091 }
2092
2093 struct fdi_m_n {
2094 u32 tu;
2095 u32 gmch_m;
2096 u32 gmch_n;
2097 u32 link_m;
2098 u32 link_n;
2099 };
2100
2101 static void
2102 fdi_reduce_ratio(u32 *num, u32 *den)
2103 {
2104 while (*num > 0xffffff || *den > 0xffffff) {
2105 *num >>= 1;
2106 *den >>= 1;
2107 }
2108 }
2109
2110 #define DATA_N 0x800000
2111 #define LINK_N 0x80000
2112
2113 static void
2114 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2115 int link_clock, struct fdi_m_n *m_n)
2116 {
2117 u64 temp;
2118
2119 m_n->tu = 64; /* default size */
2120
2121 temp = (u64) DATA_N * pixel_clock;
2122 temp = div_u64(temp, link_clock);
2123 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2124 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2125 m_n->gmch_n = DATA_N;
2126 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2127
2128 temp = (u64) LINK_N * pixel_clock;
2129 m_n->link_m = div_u64(temp, link_clock);
2130 m_n->link_n = LINK_N;
2131 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2132 }
2133
2134
2135 struct intel_watermark_params {
2136 unsigned long fifo_size;
2137 unsigned long max_wm;
2138 unsigned long default_wm;
2139 unsigned long guard_size;
2140 unsigned long cacheline_size;
2141 };
2142
2143 /* Pineview has different values for various configs */
2144 static struct intel_watermark_params pineview_display_wm = {
2145 PINEVIEW_DISPLAY_FIFO,
2146 PINEVIEW_MAX_WM,
2147 PINEVIEW_DFT_WM,
2148 PINEVIEW_GUARD_WM,
2149 PINEVIEW_FIFO_LINE_SIZE
2150 };
2151 static struct intel_watermark_params pineview_display_hplloff_wm = {
2152 PINEVIEW_DISPLAY_FIFO,
2153 PINEVIEW_MAX_WM,
2154 PINEVIEW_DFT_HPLLOFF_WM,
2155 PINEVIEW_GUARD_WM,
2156 PINEVIEW_FIFO_LINE_SIZE
2157 };
2158 static struct intel_watermark_params pineview_cursor_wm = {
2159 PINEVIEW_CURSOR_FIFO,
2160 PINEVIEW_CURSOR_MAX_WM,
2161 PINEVIEW_CURSOR_DFT_WM,
2162 PINEVIEW_CURSOR_GUARD_WM,
2163 PINEVIEW_FIFO_LINE_SIZE,
2164 };
2165 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2166 PINEVIEW_CURSOR_FIFO,
2167 PINEVIEW_CURSOR_MAX_WM,
2168 PINEVIEW_CURSOR_DFT_WM,
2169 PINEVIEW_CURSOR_GUARD_WM,
2170 PINEVIEW_FIFO_LINE_SIZE
2171 };
2172 static struct intel_watermark_params g4x_wm_info = {
2173 G4X_FIFO_SIZE,
2174 G4X_MAX_WM,
2175 G4X_MAX_WM,
2176 2,
2177 G4X_FIFO_LINE_SIZE,
2178 };
2179 static struct intel_watermark_params i945_wm_info = {
2180 I945_FIFO_SIZE,
2181 I915_MAX_WM,
2182 1,
2183 2,
2184 I915_FIFO_LINE_SIZE
2185 };
2186 static struct intel_watermark_params i915_wm_info = {
2187 I915_FIFO_SIZE,
2188 I915_MAX_WM,
2189 1,
2190 2,
2191 I915_FIFO_LINE_SIZE
2192 };
2193 static struct intel_watermark_params i855_wm_info = {
2194 I855GM_FIFO_SIZE,
2195 I915_MAX_WM,
2196 1,
2197 2,
2198 I830_FIFO_LINE_SIZE
2199 };
2200 static struct intel_watermark_params i830_wm_info = {
2201 I830_FIFO_SIZE,
2202 I915_MAX_WM,
2203 1,
2204 2,
2205 I830_FIFO_LINE_SIZE
2206 };
2207
2208 /**
2209 * intel_calculate_wm - calculate watermark level
2210 * @clock_in_khz: pixel clock
2211 * @wm: chip FIFO params
2212 * @pixel_size: display pixel size
2213 * @latency_ns: memory latency for the platform
2214 *
2215 * Calculate the watermark level (the level at which the display plane will
2216 * start fetching from memory again). Each chip has a different display
2217 * FIFO size and allocation, so the caller needs to figure that out and pass
2218 * in the correct intel_watermark_params structure.
2219 *
2220 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2221 * on the pixel size. When it reaches the watermark level, it'll start
2222 * fetching FIFO line sized based chunks from memory until the FIFO fills
2223 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2224 * will occur, and a display engine hang could result.
2225 */
2226 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2227 struct intel_watermark_params *wm,
2228 int pixel_size,
2229 unsigned long latency_ns)
2230 {
2231 long entries_required, wm_size;
2232
2233 /*
2234 * Note: we need to make sure we don't overflow for various clock &
2235 * latency values.
2236 * clocks go from a few thousand to several hundred thousand.
2237 * latency is usually a few thousand
2238 */
2239 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2240 1000;
2241 entries_required /= wm->cacheline_size;
2242
2243 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2244
2245 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2246
2247 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2248
2249 /* Don't promote wm_size to unsigned... */
2250 if (wm_size > (long)wm->max_wm)
2251 wm_size = wm->max_wm;
2252 if (wm_size <= 0)
2253 wm_size = wm->default_wm;
2254 return wm_size;
2255 }
2256
2257 struct cxsr_latency {
2258 int is_desktop;
2259 unsigned long fsb_freq;
2260 unsigned long mem_freq;
2261 unsigned long display_sr;
2262 unsigned long display_hpll_disable;
2263 unsigned long cursor_sr;
2264 unsigned long cursor_hpll_disable;
2265 };
2266
2267 static struct cxsr_latency cxsr_latency_table[] = {
2268 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2269 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2270 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2271
2272 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2273 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2274 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2275
2276 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2277 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2278 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2279
2280 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2281 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2282 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2283
2284 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2285 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2286 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2287
2288 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2289 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2290 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2291 };
2292
2293 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2294 int mem)
2295 {
2296 int i;
2297 struct cxsr_latency *latency;
2298
2299 if (fsb == 0 || mem == 0)
2300 return NULL;
2301
2302 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2303 latency = &cxsr_latency_table[i];
2304 if (is_desktop == latency->is_desktop &&
2305 fsb == latency->fsb_freq && mem == latency->mem_freq)
2306 return latency;
2307 }
2308
2309 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2310
2311 return NULL;
2312 }
2313
2314 static void pineview_disable_cxsr(struct drm_device *dev)
2315 {
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317 u32 reg;
2318
2319 /* deactivate cxsr */
2320 reg = I915_READ(DSPFW3);
2321 reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2322 I915_WRITE(DSPFW3, reg);
2323 DRM_INFO("Big FIFO is disabled\n");
2324 }
2325
2326 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2327 int pixel_size)
2328 {
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 u32 reg;
2331 unsigned long wm;
2332 struct cxsr_latency *latency;
2333
2334 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2335 dev_priv->mem_freq);
2336 if (!latency) {
2337 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2338 pineview_disable_cxsr(dev);
2339 return;
2340 }
2341
2342 /* Display SR */
2343 wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2344 latency->display_sr);
2345 reg = I915_READ(DSPFW1);
2346 reg &= 0x7fffff;
2347 reg |= wm << 23;
2348 I915_WRITE(DSPFW1, reg);
2349 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2350
2351 /* cursor SR */
2352 wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2353 latency->cursor_sr);
2354 reg = I915_READ(DSPFW3);
2355 reg &= ~(0x3f << 24);
2356 reg |= (wm & 0x3f) << 24;
2357 I915_WRITE(DSPFW3, reg);
2358
2359 /* Display HPLL off SR */
2360 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2361 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2362 reg = I915_READ(DSPFW3);
2363 reg &= 0xfffffe00;
2364 reg |= wm & 0x1ff;
2365 I915_WRITE(DSPFW3, reg);
2366
2367 /* cursor HPLL off SR */
2368 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2369 latency->cursor_hpll_disable);
2370 reg = I915_READ(DSPFW3);
2371 reg &= ~(0x3f << 16);
2372 reg |= (wm & 0x3f) << 16;
2373 I915_WRITE(DSPFW3, reg);
2374 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2375
2376 /* activate cxsr */
2377 reg = I915_READ(DSPFW3);
2378 reg |= PINEVIEW_SELF_REFRESH_EN;
2379 I915_WRITE(DSPFW3, reg);
2380
2381 DRM_INFO("Big FIFO is enabled\n");
2382
2383 return;
2384 }
2385
2386 /*
2387 * Latency for FIFO fetches is dependent on several factors:
2388 * - memory configuration (speed, channels)
2389 * - chipset
2390 * - current MCH state
2391 * It can be fairly high in some situations, so here we assume a fairly
2392 * pessimal value. It's a tradeoff between extra memory fetches (if we
2393 * set this value too high, the FIFO will fetch frequently to stay full)
2394 * and power consumption (set it too low to save power and we might see
2395 * FIFO underruns and display "flicker").
2396 *
2397 * A value of 5us seems to be a good balance; safe for very low end
2398 * platforms but not overly aggressive on lower latency configs.
2399 */
2400 static const int latency_ns = 5000;
2401
2402 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2403 {
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405 uint32_t dsparb = I915_READ(DSPARB);
2406 int size;
2407
2408 if (plane == 0)
2409 size = dsparb & 0x7f;
2410 else
2411 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2412 (dsparb & 0x7f);
2413
2414 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2415 plane ? "B" : "A", size);
2416
2417 return size;
2418 }
2419
2420 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2421 {
2422 struct drm_i915_private *dev_priv = dev->dev_private;
2423 uint32_t dsparb = I915_READ(DSPARB);
2424 int size;
2425
2426 if (plane == 0)
2427 size = dsparb & 0x1ff;
2428 else
2429 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2430 (dsparb & 0x1ff);
2431 size >>= 1; /* Convert to cachelines */
2432
2433 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2434 plane ? "B" : "A", size);
2435
2436 return size;
2437 }
2438
2439 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2440 {
2441 struct drm_i915_private *dev_priv = dev->dev_private;
2442 uint32_t dsparb = I915_READ(DSPARB);
2443 int size;
2444
2445 size = dsparb & 0x7f;
2446 size >>= 2; /* Convert to cachelines */
2447
2448 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2449 plane ? "B" : "A",
2450 size);
2451
2452 return size;
2453 }
2454
2455 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2456 {
2457 struct drm_i915_private *dev_priv = dev->dev_private;
2458 uint32_t dsparb = I915_READ(DSPARB);
2459 int size;
2460
2461 size = dsparb & 0x7f;
2462 size >>= 1; /* Convert to cachelines */
2463
2464 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2465 plane ? "B" : "A", size);
2466
2467 return size;
2468 }
2469
2470 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2471 int planeb_clock, int sr_hdisplay, int pixel_size)
2472 {
2473 struct drm_i915_private *dev_priv = dev->dev_private;
2474 int total_size, cacheline_size;
2475 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2476 struct intel_watermark_params planea_params, planeb_params;
2477 unsigned long line_time_us;
2478 int sr_clock, sr_entries = 0, entries_required;
2479
2480 /* Create copies of the base settings for each pipe */
2481 planea_params = planeb_params = g4x_wm_info;
2482
2483 /* Grab a couple of global values before we overwrite them */
2484 total_size = planea_params.fifo_size;
2485 cacheline_size = planea_params.cacheline_size;
2486
2487 /*
2488 * Note: we need to make sure we don't overflow for various clock &
2489 * latency values.
2490 * clocks go from a few thousand to several hundred thousand.
2491 * latency is usually a few thousand
2492 */
2493 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2494 1000;
2495 entries_required /= G4X_FIFO_LINE_SIZE;
2496 planea_wm = entries_required + planea_params.guard_size;
2497
2498 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2499 1000;
2500 entries_required /= G4X_FIFO_LINE_SIZE;
2501 planeb_wm = entries_required + planeb_params.guard_size;
2502
2503 cursora_wm = cursorb_wm = 16;
2504 cursor_sr = 32;
2505
2506 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2507
2508 /* Calc sr entries for one plane configs */
2509 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2510 /* self-refresh has much higher latency */
2511 static const int sr_latency_ns = 12000;
2512
2513 sr_clock = planea_clock ? planea_clock : planeb_clock;
2514 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2515
2516 /* Use ns/us then divide to preserve precision */
2517 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2518 pixel_size * sr_hdisplay) / 1000;
2519 sr_entries = roundup(sr_entries / cacheline_size, 1);
2520 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2521 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2522 }
2523
2524 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2525 planea_wm, planeb_wm, sr_entries);
2526
2527 planea_wm &= 0x3f;
2528 planeb_wm &= 0x3f;
2529
2530 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2531 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2532 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2533 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2534 (cursora_wm << DSPFW_CURSORA_SHIFT));
2535 /* HPLL off in SR has some issues on G4x... disable it */
2536 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2537 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2538 }
2539
2540 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2541 int planeb_clock, int sr_hdisplay, int pixel_size)
2542 {
2543 struct drm_i915_private *dev_priv = dev->dev_private;
2544 unsigned long line_time_us;
2545 int sr_clock, sr_entries, srwm = 1;
2546
2547 /* Calc sr entries for one plane configs */
2548 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2549 /* self-refresh has much higher latency */
2550 static const int sr_latency_ns = 12000;
2551
2552 sr_clock = planea_clock ? planea_clock : planeb_clock;
2553 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2554
2555 /* Use ns/us then divide to preserve precision */
2556 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2557 pixel_size * sr_hdisplay) / 1000;
2558 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2559 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2560 srwm = I945_FIFO_SIZE - sr_entries;
2561 if (srwm < 0)
2562 srwm = 1;
2563 srwm &= 0x3f;
2564 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2565 }
2566
2567 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2568 srwm);
2569
2570 /* 965 has limitations... */
2571 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2572 (8 << 0));
2573 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2574 }
2575
2576 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2577 int planeb_clock, int sr_hdisplay, int pixel_size)
2578 {
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 uint32_t fwater_lo;
2581 uint32_t fwater_hi;
2582 int total_size, cacheline_size, cwm, srwm = 1;
2583 int planea_wm, planeb_wm;
2584 struct intel_watermark_params planea_params, planeb_params;
2585 unsigned long line_time_us;
2586 int sr_clock, sr_entries = 0;
2587
2588 /* Create copies of the base settings for each pipe */
2589 if (IS_I965GM(dev) || IS_I945GM(dev))
2590 planea_params = planeb_params = i945_wm_info;
2591 else if (IS_I9XX(dev))
2592 planea_params = planeb_params = i915_wm_info;
2593 else
2594 planea_params = planeb_params = i855_wm_info;
2595
2596 /* Grab a couple of global values before we overwrite them */
2597 total_size = planea_params.fifo_size;
2598 cacheline_size = planea_params.cacheline_size;
2599
2600 /* Update per-plane FIFO sizes */
2601 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2602 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2603
2604 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2605 pixel_size, latency_ns);
2606 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2607 pixel_size, latency_ns);
2608 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2609
2610 /*
2611 * Overlay gets an aggressive default since video jitter is bad.
2612 */
2613 cwm = 2;
2614
2615 /* Calc sr entries for one plane configs */
2616 if (HAS_FW_BLC(dev) && sr_hdisplay &&
2617 (!planea_clock || !planeb_clock)) {
2618 /* self-refresh has much higher latency */
2619 static const int sr_latency_ns = 6000;
2620
2621 sr_clock = planea_clock ? planea_clock : planeb_clock;
2622 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2623
2624 /* Use ns/us then divide to preserve precision */
2625 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2626 pixel_size * sr_hdisplay) / 1000;
2627 sr_entries = roundup(sr_entries / cacheline_size, 1);
2628 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2629 srwm = total_size - sr_entries;
2630 if (srwm < 0)
2631 srwm = 1;
2632 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2633 }
2634
2635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2636 planea_wm, planeb_wm, cwm, srwm);
2637
2638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2639 fwater_hi = (cwm & 0x1f);
2640
2641 /* Set request length to 8 cachelines per fetch */
2642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2643 fwater_hi = fwater_hi | (1 << 8);
2644
2645 I915_WRITE(FW_BLC, fwater_lo);
2646 I915_WRITE(FW_BLC2, fwater_hi);
2647 }
2648
2649 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2650 int unused2, int pixel_size)
2651 {
2652 struct drm_i915_private *dev_priv = dev->dev_private;
2653 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2654 int planea_wm;
2655
2656 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2657
2658 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2659 pixel_size, latency_ns);
2660 fwater_lo |= (3<<8) | planea_wm;
2661
2662 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2663
2664 I915_WRITE(FW_BLC, fwater_lo);
2665 }
2666
2667 /**
2668 * intel_update_watermarks - update FIFO watermark values based on current modes
2669 *
2670 * Calculate watermark values for the various WM regs based on current mode
2671 * and plane configuration.
2672 *
2673 * There are several cases to deal with here:
2674 * - normal (i.e. non-self-refresh)
2675 * - self-refresh (SR) mode
2676 * - lines are large relative to FIFO size (buffer can hold up to 2)
2677 * - lines are small relative to FIFO size (buffer can hold more than 2
2678 * lines), so need to account for TLB latency
2679 *
2680 * The normal calculation is:
2681 * watermark = dotclock * bytes per pixel * latency
2682 * where latency is platform & configuration dependent (we assume pessimal
2683 * values here).
2684 *
2685 * The SR calculation is:
2686 * watermark = (trunc(latency/line time)+1) * surface width *
2687 * bytes per pixel
2688 * where
2689 * line time = htotal / dotclock
2690 * and latency is assumed to be high, as above.
2691 *
2692 * The final value programmed to the register should always be rounded up,
2693 * and include an extra 2 entries to account for clock crossings.
2694 *
2695 * We don't use the sprite, so we can ignore that. And on Crestline we have
2696 * to set the non-SR watermarks to 8.
2697 */
2698 static void intel_update_watermarks(struct drm_device *dev)
2699 {
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 struct drm_crtc *crtc;
2702 struct intel_crtc *intel_crtc;
2703 int sr_hdisplay = 0;
2704 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2705 int enabled = 0, pixel_size = 0;
2706
2707 if (!dev_priv->display.update_wm)
2708 return;
2709
2710 /* Get the clock config from both planes */
2711 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2712 intel_crtc = to_intel_crtc(crtc);
2713 if (crtc->enabled) {
2714 enabled++;
2715 if (intel_crtc->plane == 0) {
2716 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2717 intel_crtc->pipe, crtc->mode.clock);
2718 planea_clock = crtc->mode.clock;
2719 } else {
2720 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2721 intel_crtc->pipe, crtc->mode.clock);
2722 planeb_clock = crtc->mode.clock;
2723 }
2724 sr_hdisplay = crtc->mode.hdisplay;
2725 sr_clock = crtc->mode.clock;
2726 if (crtc->fb)
2727 pixel_size = crtc->fb->bits_per_pixel / 8;
2728 else
2729 pixel_size = 4; /* by default */
2730 }
2731 }
2732
2733 if (enabled <= 0)
2734 return;
2735
2736 /* Single plane configs can enable self refresh */
2737 if (enabled == 1 && IS_PINEVIEW(dev))
2738 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2739 else if (IS_PINEVIEW(dev))
2740 pineview_disable_cxsr(dev);
2741
2742 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2743 sr_hdisplay, pixel_size);
2744 }
2745
2746 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2747 struct drm_display_mode *mode,
2748 struct drm_display_mode *adjusted_mode,
2749 int x, int y,
2750 struct drm_framebuffer *old_fb)
2751 {
2752 struct drm_device *dev = crtc->dev;
2753 struct drm_i915_private *dev_priv = dev->dev_private;
2754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2755 int pipe = intel_crtc->pipe;
2756 int plane = intel_crtc->plane;
2757 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2758 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2759 int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2760 int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2761 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2762 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2763 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2764 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2765 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2766 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2767 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2768 int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2769 int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2770 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2771 int refclk, num_outputs = 0;
2772 intel_clock_t clock, reduced_clock;
2773 u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2774 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2775 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2776 bool is_edp = false;
2777 struct drm_mode_config *mode_config = &dev->mode_config;
2778 struct drm_connector *connector;
2779 const intel_limit_t *limit;
2780 int ret;
2781 struct fdi_m_n m_n = {0};
2782 int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2783 int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2784 int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2785 int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2786 int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2787 int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2788 int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2789 int lvds_reg = LVDS;
2790 u32 temp;
2791 int sdvo_pixel_multiply;
2792 int target_clock;
2793
2794 drm_vblank_pre_modeset(dev, pipe);
2795
2796 list_for_each_entry(connector, &mode_config->connector_list, head) {
2797 struct intel_output *intel_output = to_intel_output(connector);
2798
2799 if (!connector->encoder || connector->encoder->crtc != crtc)
2800 continue;
2801
2802 switch (intel_output->type) {
2803 case INTEL_OUTPUT_LVDS:
2804 is_lvds = true;
2805 break;
2806 case INTEL_OUTPUT_SDVO:
2807 case INTEL_OUTPUT_HDMI:
2808 is_sdvo = true;
2809 if (intel_output->needs_tv_clock)
2810 is_tv = true;
2811 break;
2812 case INTEL_OUTPUT_DVO:
2813 is_dvo = true;
2814 break;
2815 case INTEL_OUTPUT_TVOUT:
2816 is_tv = true;
2817 break;
2818 case INTEL_OUTPUT_ANALOG:
2819 is_crt = true;
2820 break;
2821 case INTEL_OUTPUT_DISPLAYPORT:
2822 is_dp = true;
2823 break;
2824 case INTEL_OUTPUT_EDP:
2825 is_edp = true;
2826 break;
2827 }
2828
2829 num_outputs++;
2830 }
2831
2832 if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2833 refclk = dev_priv->lvds_ssc_freq * 1000;
2834 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2835 refclk / 1000);
2836 } else if (IS_I9XX(dev)) {
2837 refclk = 96000;
2838 if (IS_IRONLAKE(dev))
2839 refclk = 120000; /* 120Mhz refclk */
2840 } else {
2841 refclk = 48000;
2842 }
2843
2844
2845 /*
2846 * Returns a set of divisors for the desired target clock with the given
2847 * refclk, or FALSE. The returned values represent the clock equation:
2848 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2849 */
2850 limit = intel_limit(crtc);
2851 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2852 if (!ok) {
2853 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2854 drm_vblank_post_modeset(dev, pipe);
2855 return -EINVAL;
2856 }
2857
2858 if (is_lvds && dev_priv->lvds_downclock_avail) {
2859 has_reduced_clock = limit->find_pll(limit, crtc,
2860 dev_priv->lvds_downclock,
2861 refclk,
2862 &reduced_clock);
2863 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2864 /*
2865 * If the different P is found, it means that we can't
2866 * switch the display clock by using the FP0/FP1.
2867 * In such case we will disable the LVDS downclock
2868 * feature.
2869 */
2870 DRM_DEBUG_KMS("Different P is found for "
2871 "LVDS clock/downclock\n");
2872 has_reduced_clock = 0;
2873 }
2874 }
2875 /* SDVO TV has fixed PLL values depend on its clock range,
2876 this mirrors vbios setting. */
2877 if (is_sdvo && is_tv) {
2878 if (adjusted_mode->clock >= 100000
2879 && adjusted_mode->clock < 140500) {
2880 clock.p1 = 2;
2881 clock.p2 = 10;
2882 clock.n = 3;
2883 clock.m1 = 16;
2884 clock.m2 = 8;
2885 } else if (adjusted_mode->clock >= 140500
2886 && adjusted_mode->clock <= 200000) {
2887 clock.p1 = 1;
2888 clock.p2 = 10;
2889 clock.n = 6;
2890 clock.m1 = 12;
2891 clock.m2 = 8;
2892 }
2893 }
2894
2895 /* FDI link */
2896 if (IS_IRONLAKE(dev)) {
2897 int lane, link_bw, bpp;
2898 /* eDP doesn't require FDI link, so just set DP M/N
2899 according to current link config */
2900 if (is_edp) {
2901 struct drm_connector *edp;
2902 target_clock = mode->clock;
2903 edp = intel_pipe_get_output(crtc);
2904 intel_edp_link_config(to_intel_output(edp),
2905 &lane, &link_bw);
2906 } else {
2907 /* DP over FDI requires target mode clock
2908 instead of link clock */
2909 if (is_dp)
2910 target_clock = mode->clock;
2911 else
2912 target_clock = adjusted_mode->clock;
2913 lane = 4;
2914 link_bw = 270000;
2915 }
2916
2917 /* determine panel color depth */
2918 temp = I915_READ(pipeconf_reg);
2919 temp &= ~PIPE_BPC_MASK;
2920 if (is_lvds) {
2921 int lvds_reg = I915_READ(PCH_LVDS);
2922 /* the BPC will be 6 if it is 18-bit LVDS panel */
2923 if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
2924 temp |= PIPE_8BPC;
2925 else
2926 temp |= PIPE_6BPC;
2927 } else if (is_edp) {
2928 switch (dev_priv->edp_bpp/3) {
2929 case 8:
2930 temp |= PIPE_8BPC;
2931 break;
2932 case 10:
2933 temp |= PIPE_10BPC;
2934 break;
2935 case 6:
2936 temp |= PIPE_6BPC;
2937 break;
2938 case 12:
2939 temp |= PIPE_12BPC;
2940 break;
2941 }
2942 } else
2943 temp |= PIPE_8BPC;
2944 I915_WRITE(pipeconf_reg, temp);
2945 I915_READ(pipeconf_reg);
2946
2947 switch (temp & PIPE_BPC_MASK) {
2948 case PIPE_8BPC:
2949 bpp = 24;
2950 break;
2951 case PIPE_10BPC:
2952 bpp = 30;
2953 break;
2954 case PIPE_6BPC:
2955 bpp = 18;
2956 break;
2957 case PIPE_12BPC:
2958 bpp = 36;
2959 break;
2960 default:
2961 DRM_ERROR("unknown pipe bpc value\n");
2962 bpp = 24;
2963 }
2964
2965 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
2966 }
2967
2968 /* Ironlake: try to setup display ref clock before DPLL
2969 * enabling. This is only under driver's control after
2970 * PCH B stepping, previous chipset stepping should be
2971 * ignoring this setting.
2972 */
2973 if (IS_IRONLAKE(dev)) {
2974 temp = I915_READ(PCH_DREF_CONTROL);
2975 /* Always enable nonspread source */
2976 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2977 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2978 I915_WRITE(PCH_DREF_CONTROL, temp);
2979 POSTING_READ(PCH_DREF_CONTROL);
2980
2981 temp &= ~DREF_SSC_SOURCE_MASK;
2982 temp |= DREF_SSC_SOURCE_ENABLE;
2983 I915_WRITE(PCH_DREF_CONTROL, temp);
2984 POSTING_READ(PCH_DREF_CONTROL);
2985
2986 udelay(200);
2987
2988 if (is_edp) {
2989 if (dev_priv->lvds_use_ssc) {
2990 temp |= DREF_SSC1_ENABLE;
2991 I915_WRITE(PCH_DREF_CONTROL, temp);
2992 POSTING_READ(PCH_DREF_CONTROL);
2993
2994 udelay(200);
2995
2996 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2997 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2998 I915_WRITE(PCH_DREF_CONTROL, temp);
2999 POSTING_READ(PCH_DREF_CONTROL);
3000 } else {
3001 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3002 I915_WRITE(PCH_DREF_CONTROL, temp);
3003 POSTING_READ(PCH_DREF_CONTROL);
3004 }
3005 }
3006 }
3007
3008 if (IS_PINEVIEW(dev)) {
3009 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3010 if (has_reduced_clock)
3011 fp2 = (1 << reduced_clock.n) << 16 |
3012 reduced_clock.m1 << 8 | reduced_clock.m2;
3013 } else {
3014 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3015 if (has_reduced_clock)
3016 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3017 reduced_clock.m2;
3018 }
3019
3020 if (!IS_IRONLAKE(dev))
3021 dpll = DPLL_VGA_MODE_DIS;
3022
3023 if (IS_I9XX(dev)) {
3024 if (is_lvds)
3025 dpll |= DPLLB_MODE_LVDS;
3026 else
3027 dpll |= DPLLB_MODE_DAC_SERIAL;
3028 if (is_sdvo) {
3029 dpll |= DPLL_DVO_HIGH_SPEED;
3030 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3031 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3032 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3033 else if (IS_IRONLAKE(dev))
3034 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3035 }
3036 if (is_dp)
3037 dpll |= DPLL_DVO_HIGH_SPEED;
3038
3039 /* compute bitmask from p1 value */
3040 if (IS_PINEVIEW(dev))
3041 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3042 else {
3043 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3044 /* also FPA1 */
3045 if (IS_IRONLAKE(dev))
3046 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3047 if (IS_G4X(dev) && has_reduced_clock)
3048 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3049 }
3050 switch (clock.p2) {
3051 case 5:
3052 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3053 break;
3054 case 7:
3055 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3056 break;
3057 case 10:
3058 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3059 break;
3060 case 14:
3061 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3062 break;
3063 }
3064 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3065 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3066 } else {
3067 if (is_lvds) {
3068 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3069 } else {
3070 if (clock.p1 == 2)
3071 dpll |= PLL_P1_DIVIDE_BY_TWO;
3072 else
3073 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3074 if (clock.p2 == 4)
3075 dpll |= PLL_P2_DIVIDE_BY_4;
3076 }
3077 }
3078
3079 if (is_sdvo && is_tv)
3080 dpll |= PLL_REF_INPUT_TVCLKINBC;
3081 else if (is_tv)
3082 /* XXX: just matching BIOS for now */
3083 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3084 dpll |= 3;
3085 else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3086 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3087 else
3088 dpll |= PLL_REF_INPUT_DREFCLK;
3089
3090 /* setup pipeconf */
3091 pipeconf = I915_READ(pipeconf_reg);
3092
3093 /* Set up the display plane register */
3094 dspcntr = DISPPLANE_GAMMA_ENABLE;
3095
3096 /* Ironlake's plane is forced to pipe, bit 24 is to
3097 enable color space conversion */
3098 if (!IS_IRONLAKE(dev)) {
3099 if (pipe == 0)
3100 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3101 else
3102 dspcntr |= DISPPLANE_SEL_PIPE_B;
3103 }
3104
3105 if (pipe == 0 && !IS_I965G(dev)) {
3106 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3107 * core speed.
3108 *
3109 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3110 * pipe == 0 check?
3111 */
3112 if (mode->clock >
3113 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3114 pipeconf |= PIPEACONF_DOUBLE_WIDE;
3115 else
3116 pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3117 }
3118
3119 dspcntr |= DISPLAY_PLANE_ENABLE;
3120 pipeconf |= PIPEACONF_ENABLE;
3121 dpll |= DPLL_VCO_ENABLE;
3122
3123
3124 /* Disable the panel fitter if it was on our pipe */
3125 if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3126 I915_WRITE(PFIT_CONTROL, 0);
3127
3128 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3129 drm_mode_debug_printmodeline(mode);
3130
3131 /* assign to Ironlake registers */
3132 if (IS_IRONLAKE(dev)) {
3133 fp_reg = pch_fp_reg;
3134 dpll_reg = pch_dpll_reg;
3135 }
3136
3137 if (is_edp) {
3138 ironlake_disable_pll_edp(crtc);
3139 } else if ((dpll & DPLL_VCO_ENABLE)) {
3140 I915_WRITE(fp_reg, fp);
3141 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3142 I915_READ(dpll_reg);
3143 udelay(150);
3144 }
3145
3146 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3147 * This is an exception to the general rule that mode_set doesn't turn
3148 * things on.
3149 */
3150 if (is_lvds) {
3151 u32 lvds;
3152
3153 if (IS_IRONLAKE(dev))
3154 lvds_reg = PCH_LVDS;
3155
3156 lvds = I915_READ(lvds_reg);
3157 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3158 /* set the corresponsding LVDS_BORDER bit */
3159 lvds |= dev_priv->lvds_border_bits;
3160 /* Set the B0-B3 data pairs corresponding to whether we're going to
3161 * set the DPLLs for dual-channel mode or not.
3162 */
3163 if (clock.p2 == 7)
3164 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3165 else
3166 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3167
3168 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3169 * appropriately here, but we need to look more thoroughly into how
3170 * panels behave in the two modes.
3171 */
3172 /* set the dithering flag */
3173 if (IS_I965G(dev)) {
3174 if (dev_priv->lvds_dither) {
3175 if (IS_IRONLAKE(dev))
3176 pipeconf |= PIPE_ENABLE_DITHER;
3177 else
3178 lvds |= LVDS_ENABLE_DITHER;
3179 } else {
3180 if (IS_IRONLAKE(dev))
3181 pipeconf &= ~PIPE_ENABLE_DITHER;
3182 else
3183 lvds &= ~LVDS_ENABLE_DITHER;
3184 }
3185 }
3186 I915_WRITE(lvds_reg, lvds);
3187 I915_READ(lvds_reg);
3188 }
3189 if (is_dp)
3190 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3191
3192 if (!is_edp) {
3193 I915_WRITE(fp_reg, fp);
3194 I915_WRITE(dpll_reg, dpll);
3195 I915_READ(dpll_reg);
3196 /* Wait for the clocks to stabilize. */
3197 udelay(150);
3198
3199 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3200 if (is_sdvo) {
3201 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3202 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3203 ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3204 } else
3205 I915_WRITE(dpll_md_reg, 0);
3206 } else {
3207 /* write it again -- the BIOS does, after all */
3208 I915_WRITE(dpll_reg, dpll);
3209 }
3210 I915_READ(dpll_reg);
3211 /* Wait for the clocks to stabilize. */
3212 udelay(150);
3213 }
3214
3215 if (is_lvds && has_reduced_clock && i915_powersave) {
3216 I915_WRITE(fp_reg + 4, fp2);
3217 intel_crtc->lowfreq_avail = true;
3218 if (HAS_PIPE_CXSR(dev)) {
3219 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3220 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3221 }
3222 } else {
3223 I915_WRITE(fp_reg + 4, fp);
3224 intel_crtc->lowfreq_avail = false;
3225 if (HAS_PIPE_CXSR(dev)) {
3226 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3227 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3228 }
3229 }
3230
3231 I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3232 ((adjusted_mode->crtc_htotal - 1) << 16));
3233 I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3234 ((adjusted_mode->crtc_hblank_end - 1) << 16));
3235 I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3236 ((adjusted_mode->crtc_hsync_end - 1) << 16));
3237 I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3238 ((adjusted_mode->crtc_vtotal - 1) << 16));
3239 I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3240 ((adjusted_mode->crtc_vblank_end - 1) << 16));
3241 I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3242 ((adjusted_mode->crtc_vsync_end - 1) << 16));
3243 /* pipesrc and dspsize control the size that is scaled from, which should
3244 * always be the user's requested size.
3245 */
3246 if (!IS_IRONLAKE(dev)) {
3247 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3248 (mode->hdisplay - 1));
3249 I915_WRITE(dsppos_reg, 0);
3250 }
3251 I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3252
3253 if (IS_IRONLAKE(dev)) {
3254 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3255 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3256 I915_WRITE(link_m1_reg, m_n.link_m);
3257 I915_WRITE(link_n1_reg, m_n.link_n);
3258
3259 if (is_edp) {
3260 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3261 } else {
3262 /* enable FDI RX PLL too */
3263 temp = I915_READ(fdi_rx_reg);
3264 I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3265 udelay(200);
3266 }
3267 }
3268
3269 I915_WRITE(pipeconf_reg, pipeconf);
3270 I915_READ(pipeconf_reg);
3271
3272 intel_wait_for_vblank(dev);
3273
3274 if (IS_IRONLAKE(dev)) {
3275 /* enable address swizzle for tiling buffer */
3276 temp = I915_READ(DISP_ARB_CTL);
3277 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3278 }
3279
3280 I915_WRITE(dspcntr_reg, dspcntr);
3281
3282 /* Flush the plane changes */
3283 ret = intel_pipe_set_base(crtc, x, y, old_fb);
3284
3285 if ((IS_I965G(dev) || plane == 0))
3286 intel_update_fbc(crtc, &crtc->mode);
3287
3288 intel_update_watermarks(dev);
3289
3290 drm_vblank_post_modeset(dev, pipe);
3291
3292 return ret;
3293 }
3294
3295 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3296 void intel_crtc_load_lut(struct drm_crtc *crtc)
3297 {
3298 struct drm_device *dev = crtc->dev;
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3301 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3302 int i;
3303
3304 /* The clocks have to be on to load the palette. */
3305 if (!crtc->enabled)
3306 return;
3307
3308 /* use legacy palette for Ironlake */
3309 if (IS_IRONLAKE(dev))
3310 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3311 LGC_PALETTE_B;
3312
3313 for (i = 0; i < 256; i++) {
3314 I915_WRITE(palreg + 4 * i,
3315 (intel_crtc->lut_r[i] << 16) |
3316 (intel_crtc->lut_g[i] << 8) |
3317 intel_crtc->lut_b[i]);
3318 }
3319 }
3320
3321 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3322 struct drm_file *file_priv,
3323 uint32_t handle,
3324 uint32_t width, uint32_t height)
3325 {
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329 struct drm_gem_object *bo;
3330 struct drm_i915_gem_object *obj_priv;
3331 int pipe = intel_crtc->pipe;
3332 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3333 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3334 uint32_t temp = I915_READ(control);
3335 size_t addr;
3336 int ret;
3337
3338 DRM_DEBUG_KMS("\n");
3339
3340 /* if we want to turn off the cursor ignore width and height */
3341 if (!handle) {
3342 DRM_DEBUG_KMS("cursor off\n");
3343 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3344 temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3345 temp |= CURSOR_MODE_DISABLE;
3346 } else {
3347 temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3348 }
3349 addr = 0;
3350 bo = NULL;
3351 mutex_lock(&dev->struct_mutex);
3352 goto finish;
3353 }
3354
3355 /* Currently we only support 64x64 cursors */
3356 if (width != 64 || height != 64) {
3357 DRM_ERROR("we currently only support 64x64 cursors\n");
3358 return -EINVAL;
3359 }
3360
3361 bo = drm_gem_object_lookup(dev, file_priv, handle);
3362 if (!bo)
3363 return -ENOENT;
3364
3365 obj_priv = bo->driver_private;
3366
3367 if (bo->size < width * height * 4) {
3368 DRM_ERROR("buffer is to small\n");
3369 ret = -ENOMEM;
3370 goto fail;
3371 }
3372
3373 /* we only need to pin inside GTT if cursor is non-phy */
3374 mutex_lock(&dev->struct_mutex);
3375 if (!dev_priv->info->cursor_needs_physical) {
3376 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3377 if (ret) {
3378 DRM_ERROR("failed to pin cursor bo\n");
3379 goto fail_locked;
3380 }
3381 addr = obj_priv->gtt_offset;
3382 } else {
3383 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3384 if (ret) {
3385 DRM_ERROR("failed to attach phys object\n");
3386 goto fail_locked;
3387 }
3388 addr = obj_priv->phys_obj->handle->busaddr;
3389 }
3390
3391 if (!IS_I9XX(dev))
3392 I915_WRITE(CURSIZE, (height << 12) | width);
3393
3394 /* Hooray for CUR*CNTR differences */
3395 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3396 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3397 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3398 temp |= (pipe << 28); /* Connect to correct pipe */
3399 } else {
3400 temp &= ~(CURSOR_FORMAT_MASK);
3401 temp |= CURSOR_ENABLE;
3402 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3403 }
3404
3405 finish:
3406 I915_WRITE(control, temp);
3407 I915_WRITE(base, addr);
3408
3409 if (intel_crtc->cursor_bo) {
3410 if (dev_priv->info->cursor_needs_physical) {
3411 if (intel_crtc->cursor_bo != bo)
3412 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3413 } else
3414 i915_gem_object_unpin(intel_crtc->cursor_bo);
3415 drm_gem_object_unreference(intel_crtc->cursor_bo);
3416 }
3417
3418 mutex_unlock(&dev->struct_mutex);
3419
3420 intel_crtc->cursor_addr = addr;
3421 intel_crtc->cursor_bo = bo;
3422
3423 return 0;
3424 fail:
3425 mutex_lock(&dev->struct_mutex);
3426 fail_locked:
3427 drm_gem_object_unreference(bo);
3428 mutex_unlock(&dev->struct_mutex);
3429 return ret;
3430 }
3431
3432 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3433 {
3434 struct drm_device *dev = crtc->dev;
3435 struct drm_i915_private *dev_priv = dev->dev_private;
3436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3437 struct intel_framebuffer *intel_fb;
3438 int pipe = intel_crtc->pipe;
3439 uint32_t temp = 0;
3440 uint32_t adder;
3441
3442 if (crtc->fb) {
3443 intel_fb = to_intel_framebuffer(crtc->fb);
3444 intel_mark_busy(dev, intel_fb->obj);
3445 }
3446
3447 if (x < 0) {
3448 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3449 x = -x;
3450 }
3451 if (y < 0) {
3452 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3453 y = -y;
3454 }
3455
3456 temp |= x << CURSOR_X_SHIFT;
3457 temp |= y << CURSOR_Y_SHIFT;
3458
3459 adder = intel_crtc->cursor_addr;
3460 I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3461 I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3462
3463 return 0;
3464 }
3465
3466 /** Sets the color ramps on behalf of RandR */
3467 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3468 u16 blue, int regno)
3469 {
3470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3471
3472 intel_crtc->lut_r[regno] = red >> 8;
3473 intel_crtc->lut_g[regno] = green >> 8;
3474 intel_crtc->lut_b[regno] = blue >> 8;
3475 }
3476
3477 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3478 u16 *blue, int regno)
3479 {
3480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3481
3482 *red = intel_crtc->lut_r[regno] << 8;
3483 *green = intel_crtc->lut_g[regno] << 8;
3484 *blue = intel_crtc->lut_b[regno] << 8;
3485 }
3486
3487 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3488 u16 *blue, uint32_t size)
3489 {
3490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3491 int i;
3492
3493 if (size != 256)
3494 return;
3495
3496 for (i = 0; i < 256; i++) {
3497 intel_crtc->lut_r[i] = red[i] >> 8;
3498 intel_crtc->lut_g[i] = green[i] >> 8;
3499 intel_crtc->lut_b[i] = blue[i] >> 8;
3500 }
3501
3502 intel_crtc_load_lut(crtc);
3503 }
3504
3505 /**
3506 * Get a pipe with a simple mode set on it for doing load-based monitor
3507 * detection.
3508 *
3509 * It will be up to the load-detect code to adjust the pipe as appropriate for
3510 * its requirements. The pipe will be connected to no other outputs.
3511 *
3512 * Currently this code will only succeed if there is a pipe with no outputs
3513 * configured for it. In the future, it could choose to temporarily disable
3514 * some outputs to free up a pipe for its use.
3515 *
3516 * \return crtc, or NULL if no pipes are available.
3517 */
3518
3519 /* VESA 640x480x72Hz mode to set on the pipe */
3520 static struct drm_display_mode load_detect_mode = {
3521 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3522 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3523 };
3524
3525 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3526 struct drm_display_mode *mode,
3527 int *dpms_mode)
3528 {
3529 struct intel_crtc *intel_crtc;
3530 struct drm_crtc *possible_crtc;
3531 struct drm_crtc *supported_crtc =NULL;
3532 struct drm_encoder *encoder = &intel_output->enc;
3533 struct drm_crtc *crtc = NULL;
3534 struct drm_device *dev = encoder->dev;
3535 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3536 struct drm_crtc_helper_funcs *crtc_funcs;
3537 int i = -1;
3538
3539 /*
3540 * Algorithm gets a little messy:
3541 * - if the connector already has an assigned crtc, use it (but make
3542 * sure it's on first)
3543 * - try to find the first unused crtc that can drive this connector,
3544 * and use that if we find one
3545 * - if there are no unused crtcs available, try to use the first
3546 * one we found that supports the connector
3547 */
3548
3549 /* See if we already have a CRTC for this connector */
3550 if (encoder->crtc) {
3551 crtc = encoder->crtc;
3552 /* Make sure the crtc and connector are running */
3553 intel_crtc = to_intel_crtc(crtc);
3554 *dpms_mode = intel_crtc->dpms_mode;
3555 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3556 crtc_funcs = crtc->helper_private;
3557 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3558 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3559 }
3560 return crtc;
3561 }
3562
3563 /* Find an unused one (if possible) */
3564 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3565 i++;
3566 if (!(encoder->possible_crtcs & (1 << i)))
3567 continue;
3568 if (!possible_crtc->enabled) {
3569 crtc = possible_crtc;
3570 break;
3571 }
3572 if (!supported_crtc)
3573 supported_crtc = possible_crtc;
3574 }
3575
3576 /*
3577 * If we didn't find an unused CRTC, don't use any.
3578 */
3579 if (!crtc) {
3580 return NULL;
3581 }
3582
3583 encoder->crtc = crtc;
3584 intel_output->base.encoder = encoder;
3585 intel_output->load_detect_temp = true;
3586
3587 intel_crtc = to_intel_crtc(crtc);
3588 *dpms_mode = intel_crtc->dpms_mode;
3589
3590 if (!crtc->enabled) {
3591 if (!mode)
3592 mode = &load_detect_mode;
3593 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3594 } else {
3595 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3596 crtc_funcs = crtc->helper_private;
3597 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3598 }
3599
3600 /* Add this connector to the crtc */
3601 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3602 encoder_funcs->commit(encoder);
3603 }
3604 /* let the connector get through one full cycle before testing */
3605 intel_wait_for_vblank(dev);
3606
3607 return crtc;
3608 }
3609
3610 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3611 {
3612 struct drm_encoder *encoder = &intel_output->enc;
3613 struct drm_device *dev = encoder->dev;
3614 struct drm_crtc *crtc = encoder->crtc;
3615 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3616 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3617
3618 if (intel_output->load_detect_temp) {
3619 encoder->crtc = NULL;
3620 intel_output->base.encoder = NULL;
3621 intel_output->load_detect_temp = false;
3622 crtc->enabled = drm_helper_crtc_in_use(crtc);
3623 drm_helper_disable_unused_functions(dev);
3624 }
3625
3626 /* Switch crtc and output back off if necessary */
3627 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3628 if (encoder->crtc == crtc)
3629 encoder_funcs->dpms(encoder, dpms_mode);
3630 crtc_funcs->dpms(crtc, dpms_mode);
3631 }
3632 }
3633
3634 /* Returns the clock of the currently programmed mode of the given pipe. */
3635 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3636 {
3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639 int pipe = intel_crtc->pipe;
3640 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3641 u32 fp;
3642 intel_clock_t clock;
3643
3644 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3645 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3646 else
3647 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3648
3649 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3650 if (IS_PINEVIEW(dev)) {
3651 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3652 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3653 } else {
3654 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3655 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3656 }
3657
3658 if (IS_I9XX(dev)) {
3659 if (IS_PINEVIEW(dev))
3660 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3661 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3662 else
3663 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3664 DPLL_FPA01_P1_POST_DIV_SHIFT);
3665
3666 switch (dpll & DPLL_MODE_MASK) {
3667 case DPLLB_MODE_DAC_SERIAL:
3668 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3669 5 : 10;
3670 break;
3671 case DPLLB_MODE_LVDS:
3672 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3673 7 : 14;
3674 break;
3675 default:
3676 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3677 "mode\n", (int)(dpll & DPLL_MODE_MASK));
3678 return 0;
3679 }
3680
3681 /* XXX: Handle the 100Mhz refclk */
3682 intel_clock(dev, 96000, &clock);
3683 } else {
3684 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3685
3686 if (is_lvds) {
3687 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3688 DPLL_FPA01_P1_POST_DIV_SHIFT);
3689 clock.p2 = 14;
3690
3691 if ((dpll & PLL_REF_INPUT_MASK) ==
3692 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3693 /* XXX: might not be 66MHz */
3694 intel_clock(dev, 66000, &clock);
3695 } else
3696 intel_clock(dev, 48000, &clock);
3697 } else {
3698 if (dpll & PLL_P1_DIVIDE_BY_TWO)
3699 clock.p1 = 2;
3700 else {
3701 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3702 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3703 }
3704 if (dpll & PLL_P2_DIVIDE_BY_4)
3705 clock.p2 = 4;
3706 else
3707 clock.p2 = 2;
3708
3709 intel_clock(dev, 48000, &clock);
3710 }
3711 }
3712
3713 /* XXX: It would be nice to validate the clocks, but we can't reuse
3714 * i830PllIsValid() because it relies on the xf86_config connector
3715 * configuration being accurate, which it isn't necessarily.
3716 */
3717
3718 return clock.dot;
3719 }
3720
3721 /** Returns the currently programmed mode of the given pipe. */
3722 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3723 struct drm_crtc *crtc)
3724 {
3725 struct drm_i915_private *dev_priv = dev->dev_private;
3726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3727 int pipe = intel_crtc->pipe;
3728 struct drm_display_mode *mode;
3729 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3730 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3731 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3732 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3733
3734 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3735 if (!mode)
3736 return NULL;
3737
3738 mode->clock = intel_crtc_clock_get(dev, crtc);
3739 mode->hdisplay = (htot & 0xffff) + 1;
3740 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3741 mode->hsync_start = (hsync & 0xffff) + 1;
3742 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3743 mode->vdisplay = (vtot & 0xffff) + 1;
3744 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3745 mode->vsync_start = (vsync & 0xffff) + 1;
3746 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3747
3748 drm_mode_set_name(mode);
3749 drm_mode_set_crtcinfo(mode, 0);
3750
3751 return mode;
3752 }
3753
3754 #define GPU_IDLE_TIMEOUT 500 /* ms */
3755
3756 /* When this timer fires, we've been idle for awhile */
3757 static void intel_gpu_idle_timer(unsigned long arg)
3758 {
3759 struct drm_device *dev = (struct drm_device *)arg;
3760 drm_i915_private_t *dev_priv = dev->dev_private;
3761
3762 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3763
3764 dev_priv->busy = false;
3765
3766 queue_work(dev_priv->wq, &dev_priv->idle_work);
3767 }
3768
3769 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3770
3771 static void intel_crtc_idle_timer(unsigned long arg)
3772 {
3773 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3774 struct drm_crtc *crtc = &intel_crtc->base;
3775 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3776
3777 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3778
3779 intel_crtc->busy = false;
3780
3781 queue_work(dev_priv->wq, &dev_priv->idle_work);
3782 }
3783
3784 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3785 {
3786 struct drm_device *dev = crtc->dev;
3787 drm_i915_private_t *dev_priv = dev->dev_private;
3788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3789 int pipe = intel_crtc->pipe;
3790 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3791 int dpll = I915_READ(dpll_reg);
3792
3793 if (IS_IRONLAKE(dev))
3794 return;
3795
3796 if (!dev_priv->lvds_downclock_avail)
3797 return;
3798
3799 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3800 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3801
3802 /* Unlock panel regs */
3803 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3804
3805 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3806 I915_WRITE(dpll_reg, dpll);
3807 dpll = I915_READ(dpll_reg);
3808 intel_wait_for_vblank(dev);
3809 dpll = I915_READ(dpll_reg);
3810 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3811 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3812
3813 /* ...and lock them again */
3814 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3815 }
3816
3817 /* Schedule downclock */
3818 if (schedule)
3819 mod_timer(&intel_crtc->idle_timer, jiffies +
3820 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3821 }
3822
3823 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3824 {
3825 struct drm_device *dev = crtc->dev;
3826 drm_i915_private_t *dev_priv = dev->dev_private;
3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828 int pipe = intel_crtc->pipe;
3829 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3830 int dpll = I915_READ(dpll_reg);
3831
3832 if (IS_IRONLAKE(dev))
3833 return;
3834
3835 if (!dev_priv->lvds_downclock_avail)
3836 return;
3837
3838 /*
3839 * Since this is called by a timer, we should never get here in
3840 * the manual case.
3841 */
3842 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3843 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3844
3845 /* Unlock panel regs */
3846 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3847
3848 dpll |= DISPLAY_RATE_SELECT_FPA1;
3849 I915_WRITE(dpll_reg, dpll);
3850 dpll = I915_READ(dpll_reg);
3851 intel_wait_for_vblank(dev);
3852 dpll = I915_READ(dpll_reg);
3853 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3854 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3855
3856 /* ...and lock them again */
3857 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3858 }
3859
3860 }
3861
3862 /**
3863 * intel_idle_update - adjust clocks for idleness
3864 * @work: work struct
3865 *
3866 * Either the GPU or display (or both) went idle. Check the busy status
3867 * here and adjust the CRTC and GPU clocks as necessary.
3868 */
3869 static void intel_idle_update(struct work_struct *work)
3870 {
3871 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3872 idle_work);
3873 struct drm_device *dev = dev_priv->dev;
3874 struct drm_crtc *crtc;
3875 struct intel_crtc *intel_crtc;
3876
3877 if (!i915_powersave)
3878 return;
3879
3880 mutex_lock(&dev->struct_mutex);
3881
3882 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3883 /* Skip inactive CRTCs */
3884 if (!crtc->fb)
3885 continue;
3886
3887 intel_crtc = to_intel_crtc(crtc);
3888 if (!intel_crtc->busy)
3889 intel_decrease_pllclock(crtc);
3890 }
3891
3892 mutex_unlock(&dev->struct_mutex);
3893 }
3894
3895 /**
3896 * intel_mark_busy - mark the GPU and possibly the display busy
3897 * @dev: drm device
3898 * @obj: object we're operating on
3899 *
3900 * Callers can use this function to indicate that the GPU is busy processing
3901 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3902 * buffer), we'll also mark the display as busy, so we know to increase its
3903 * clock frequency.
3904 */
3905 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
3906 {
3907 drm_i915_private_t *dev_priv = dev->dev_private;
3908 struct drm_crtc *crtc = NULL;
3909 struct intel_framebuffer *intel_fb;
3910 struct intel_crtc *intel_crtc;
3911
3912 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3913 return;
3914
3915 if (!dev_priv->busy)
3916 dev_priv->busy = true;
3917 else
3918 mod_timer(&dev_priv->idle_timer, jiffies +
3919 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
3920
3921 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3922 if (!crtc->fb)
3923 continue;
3924
3925 intel_crtc = to_intel_crtc(crtc);
3926 intel_fb = to_intel_framebuffer(crtc->fb);
3927 if (intel_fb->obj == obj) {
3928 if (!intel_crtc->busy) {
3929 /* Non-busy -> busy, upclock */
3930 intel_increase_pllclock(crtc, true);
3931 intel_crtc->busy = true;
3932 } else {
3933 /* Busy -> busy, put off timer */
3934 mod_timer(&intel_crtc->idle_timer, jiffies +
3935 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3936 }
3937 }
3938 }
3939 }
3940
3941 static void intel_crtc_destroy(struct drm_crtc *crtc)
3942 {
3943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3944
3945 drm_crtc_cleanup(crtc);
3946 kfree(intel_crtc);
3947 }
3948
3949 struct intel_unpin_work {
3950 struct work_struct work;
3951 struct drm_device *dev;
3952 struct drm_gem_object *obj;
3953 struct drm_pending_vblank_event *event;
3954 int pending;
3955 };
3956
3957 static void intel_unpin_work_fn(struct work_struct *__work)
3958 {
3959 struct intel_unpin_work *work =
3960 container_of(__work, struct intel_unpin_work, work);
3961
3962 mutex_lock(&work->dev->struct_mutex);
3963 i915_gem_object_unpin(work->obj);
3964 drm_gem_object_unreference(work->obj);
3965 mutex_unlock(&work->dev->struct_mutex);
3966 kfree(work);
3967 }
3968
3969 void intel_finish_page_flip(struct drm_device *dev, int pipe)
3970 {
3971 drm_i915_private_t *dev_priv = dev->dev_private;
3972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3974 struct intel_unpin_work *work;
3975 struct drm_i915_gem_object *obj_priv;
3976 struct drm_pending_vblank_event *e;
3977 struct timeval now;
3978 unsigned long flags;
3979
3980 /* Ignore early vblank irqs */
3981 if (intel_crtc == NULL)
3982 return;
3983
3984 spin_lock_irqsave(&dev->event_lock, flags);
3985 work = intel_crtc->unpin_work;
3986 if (work == NULL || !work->pending) {
3987 spin_unlock_irqrestore(&dev->event_lock, flags);
3988 return;
3989 }
3990
3991 intel_crtc->unpin_work = NULL;
3992 drm_vblank_put(dev, intel_crtc->pipe);
3993
3994 if (work->event) {
3995 e = work->event;
3996 do_gettimeofday(&now);
3997 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
3998 e->event.tv_sec = now.tv_sec;
3999 e->event.tv_usec = now.tv_usec;
4000 list_add_tail(&e->base.link,
4001 &e->base.file_priv->event_list);
4002 wake_up_interruptible(&e->base.file_priv->event_wait);
4003 }
4004
4005 spin_unlock_irqrestore(&dev->event_lock, flags);
4006
4007 obj_priv = work->obj->driver_private;
4008 if (atomic_dec_and_test(&obj_priv->pending_flip))
4009 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4010 schedule_work(&work->work);
4011 }
4012
4013 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4014 {
4015 drm_i915_private_t *dev_priv = dev->dev_private;
4016 struct intel_crtc *intel_crtc =
4017 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4018 unsigned long flags;
4019
4020 spin_lock_irqsave(&dev->event_lock, flags);
4021 if (intel_crtc->unpin_work)
4022 intel_crtc->unpin_work->pending = 1;
4023 spin_unlock_irqrestore(&dev->event_lock, flags);
4024 }
4025
4026 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4027 struct drm_framebuffer *fb,
4028 struct drm_pending_vblank_event *event)
4029 {
4030 struct drm_device *dev = crtc->dev;
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 struct intel_framebuffer *intel_fb;
4033 struct drm_i915_gem_object *obj_priv;
4034 struct drm_gem_object *obj;
4035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4036 struct intel_unpin_work *work;
4037 unsigned long flags;
4038 int ret;
4039 RING_LOCALS;
4040
4041 work = kzalloc(sizeof *work, GFP_KERNEL);
4042 if (work == NULL)
4043 return -ENOMEM;
4044
4045 mutex_lock(&dev->struct_mutex);
4046
4047 work->event = event;
4048 work->dev = crtc->dev;
4049 intel_fb = to_intel_framebuffer(crtc->fb);
4050 work->obj = intel_fb->obj;
4051 INIT_WORK(&work->work, intel_unpin_work_fn);
4052
4053 /* We borrow the event spin lock for protecting unpin_work */
4054 spin_lock_irqsave(&dev->event_lock, flags);
4055 if (intel_crtc->unpin_work) {
4056 spin_unlock_irqrestore(&dev->event_lock, flags);
4057 kfree(work);
4058 mutex_unlock(&dev->struct_mutex);
4059 return -EBUSY;
4060 }
4061 intel_crtc->unpin_work = work;
4062 spin_unlock_irqrestore(&dev->event_lock, flags);
4063
4064 intel_fb = to_intel_framebuffer(fb);
4065 obj = intel_fb->obj;
4066
4067 ret = intel_pin_and_fence_fb_obj(dev, obj);
4068 if (ret != 0) {
4069 kfree(work);
4070 mutex_unlock(&dev->struct_mutex);
4071 return ret;
4072 }
4073
4074 /* Reference the old fb object for the scheduled work. */
4075 drm_gem_object_reference(work->obj);
4076
4077 crtc->fb = fb;
4078 i915_gem_object_flush_write_domain(obj);
4079 drm_vblank_get(dev, intel_crtc->pipe);
4080 obj_priv = obj->driver_private;
4081 atomic_inc(&obj_priv->pending_flip);
4082
4083 BEGIN_LP_RING(4);
4084 OUT_RING(MI_DISPLAY_FLIP |
4085 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4086 OUT_RING(fb->pitch);
4087 if (IS_I965G(dev)) {
4088 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4089 OUT_RING((fb->width << 16) | fb->height);
4090 } else {
4091 OUT_RING(obj_priv->gtt_offset);
4092 OUT_RING(MI_NOOP);
4093 }
4094 ADVANCE_LP_RING();
4095
4096 mutex_unlock(&dev->struct_mutex);
4097
4098 return 0;
4099 }
4100
4101 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4102 .dpms = intel_crtc_dpms,
4103 .mode_fixup = intel_crtc_mode_fixup,
4104 .mode_set = intel_crtc_mode_set,
4105 .mode_set_base = intel_pipe_set_base,
4106 .prepare = intel_crtc_prepare,
4107 .commit = intel_crtc_commit,
4108 .load_lut = intel_crtc_load_lut,
4109 };
4110
4111 static const struct drm_crtc_funcs intel_crtc_funcs = {
4112 .cursor_set = intel_crtc_cursor_set,
4113 .cursor_move = intel_crtc_cursor_move,
4114 .gamma_set = intel_crtc_gamma_set,
4115 .set_config = drm_crtc_helper_set_config,
4116 .destroy = intel_crtc_destroy,
4117 .page_flip = intel_crtc_page_flip,
4118 };
4119
4120
4121 static void intel_crtc_init(struct drm_device *dev, int pipe)
4122 {
4123 drm_i915_private_t *dev_priv = dev->dev_private;
4124 struct intel_crtc *intel_crtc;
4125 int i;
4126
4127 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4128 if (intel_crtc == NULL)
4129 return;
4130
4131 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4132
4133 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4134 intel_crtc->pipe = pipe;
4135 intel_crtc->plane = pipe;
4136 for (i = 0; i < 256; i++) {
4137 intel_crtc->lut_r[i] = i;
4138 intel_crtc->lut_g[i] = i;
4139 intel_crtc->lut_b[i] = i;
4140 }
4141
4142 /* Swap pipes & planes for FBC on pre-965 */
4143 intel_crtc->pipe = pipe;
4144 intel_crtc->plane = pipe;
4145 if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4146 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4147 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4148 }
4149
4150 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4151 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4152 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4153 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4154
4155 intel_crtc->cursor_addr = 0;
4156 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4157 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4158
4159 intel_crtc->busy = false;
4160
4161 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4162 (unsigned long)intel_crtc);
4163 }
4164
4165 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4166 struct drm_file *file_priv)
4167 {
4168 drm_i915_private_t *dev_priv = dev->dev_private;
4169 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4170 struct drm_mode_object *drmmode_obj;
4171 struct intel_crtc *crtc;
4172
4173 if (!dev_priv) {
4174 DRM_ERROR("called with no initialization\n");
4175 return -EINVAL;
4176 }
4177
4178 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4179 DRM_MODE_OBJECT_CRTC);
4180
4181 if (!drmmode_obj) {
4182 DRM_ERROR("no such CRTC id\n");
4183 return -EINVAL;
4184 }
4185
4186 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4187 pipe_from_crtc_id->pipe = crtc->pipe;
4188
4189 return 0;
4190 }
4191
4192 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4193 {
4194 struct drm_crtc *crtc = NULL;
4195
4196 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4198 if (intel_crtc->pipe == pipe)
4199 break;
4200 }
4201 return crtc;
4202 }
4203
4204 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4205 {
4206 int index_mask = 0;
4207 struct drm_connector *connector;
4208 int entry = 0;
4209
4210 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4211 struct intel_output *intel_output = to_intel_output(connector);
4212 if (type_mask & intel_output->clone_mask)
4213 index_mask |= (1 << entry);
4214 entry++;
4215 }
4216 return index_mask;
4217 }
4218
4219
4220 static void intel_setup_outputs(struct drm_device *dev)
4221 {
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 struct drm_connector *connector;
4224
4225 intel_crt_init(dev);
4226
4227 /* Set up integrated LVDS */
4228 if (IS_MOBILE(dev) && !IS_I830(dev))
4229 intel_lvds_init(dev);
4230
4231 if (IS_IRONLAKE(dev)) {
4232 int found;
4233
4234 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4235 intel_dp_init(dev, DP_A);
4236
4237 if (I915_READ(HDMIB) & PORT_DETECTED) {
4238 /* check SDVOB */
4239 /* found = intel_sdvo_init(dev, HDMIB); */
4240 found = 0;
4241 if (!found)
4242 intel_hdmi_init(dev, HDMIB);
4243 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4244 intel_dp_init(dev, PCH_DP_B);
4245 }
4246
4247 if (I915_READ(HDMIC) & PORT_DETECTED)
4248 intel_hdmi_init(dev, HDMIC);
4249
4250 if (I915_READ(HDMID) & PORT_DETECTED)
4251 intel_hdmi_init(dev, HDMID);
4252
4253 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4254 intel_dp_init(dev, PCH_DP_C);
4255
4256 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4257 intel_dp_init(dev, PCH_DP_D);
4258
4259 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4260 bool found = false;
4261
4262 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4263 DRM_DEBUG_KMS("probing SDVOB\n");
4264 found = intel_sdvo_init(dev, SDVOB);
4265 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4266 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4267 intel_hdmi_init(dev, SDVOB);
4268 }
4269
4270 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4271 DRM_DEBUG_KMS("probing DP_B\n");
4272 intel_dp_init(dev, DP_B);
4273 }
4274 }
4275
4276 /* Before G4X SDVOC doesn't have its own detect register */
4277
4278 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4279 DRM_DEBUG_KMS("probing SDVOC\n");
4280 found = intel_sdvo_init(dev, SDVOC);
4281 }
4282
4283 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4284
4285 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4286 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4287 intel_hdmi_init(dev, SDVOC);
4288 }
4289 if (SUPPORTS_INTEGRATED_DP(dev)) {
4290 DRM_DEBUG_KMS("probing DP_C\n");
4291 intel_dp_init(dev, DP_C);
4292 }
4293 }
4294
4295 if (SUPPORTS_INTEGRATED_DP(dev) &&
4296 (I915_READ(DP_D) & DP_DETECTED)) {
4297 DRM_DEBUG_KMS("probing DP_D\n");
4298 intel_dp_init(dev, DP_D);
4299 }
4300 } else if (IS_I8XX(dev))
4301 intel_dvo_init(dev);
4302
4303 if (SUPPORTS_TV(dev))
4304 intel_tv_init(dev);
4305
4306 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4307 struct intel_output *intel_output = to_intel_output(connector);
4308 struct drm_encoder *encoder = &intel_output->enc;
4309
4310 encoder->possible_crtcs = intel_output->crtc_mask;
4311 encoder->possible_clones = intel_connector_clones(dev,
4312 intel_output->clone_mask);
4313 }
4314 }
4315
4316 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4317 {
4318 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4319 struct drm_device *dev = fb->dev;
4320
4321 if (fb->fbdev)
4322 intelfb_remove(dev, fb);
4323
4324 drm_framebuffer_cleanup(fb);
4325 mutex_lock(&dev->struct_mutex);
4326 drm_gem_object_unreference(intel_fb->obj);
4327 mutex_unlock(&dev->struct_mutex);
4328
4329 kfree(intel_fb);
4330 }
4331
4332 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4333 struct drm_file *file_priv,
4334 unsigned int *handle)
4335 {
4336 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4337 struct drm_gem_object *object = intel_fb->obj;
4338
4339 return drm_gem_handle_create(file_priv, object, handle);
4340 }
4341
4342 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4343 .destroy = intel_user_framebuffer_destroy,
4344 .create_handle = intel_user_framebuffer_create_handle,
4345 };
4346
4347 int intel_framebuffer_create(struct drm_device *dev,
4348 struct drm_mode_fb_cmd *mode_cmd,
4349 struct drm_framebuffer **fb,
4350 struct drm_gem_object *obj)
4351 {
4352 struct intel_framebuffer *intel_fb;
4353 int ret;
4354
4355 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4356 if (!intel_fb)
4357 return -ENOMEM;
4358
4359 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4360 if (ret) {
4361 DRM_ERROR("framebuffer init failed %d\n", ret);
4362 return ret;
4363 }
4364
4365 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4366
4367 intel_fb->obj = obj;
4368
4369 *fb = &intel_fb->base;
4370
4371 return 0;
4372 }
4373
4374
4375 static struct drm_framebuffer *
4376 intel_user_framebuffer_create(struct drm_device *dev,
4377 struct drm_file *filp,
4378 struct drm_mode_fb_cmd *mode_cmd)
4379 {
4380 struct drm_gem_object *obj;
4381 struct drm_framebuffer *fb;
4382 int ret;
4383
4384 obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4385 if (!obj)
4386 return NULL;
4387
4388 ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4389 if (ret) {
4390 mutex_lock(&dev->struct_mutex);
4391 drm_gem_object_unreference(obj);
4392 mutex_unlock(&dev->struct_mutex);
4393 return NULL;
4394 }
4395
4396 return fb;
4397 }
4398
4399 static const struct drm_mode_config_funcs intel_mode_funcs = {
4400 .fb_create = intel_user_framebuffer_create,
4401 .fb_changed = intelfb_probe,
4402 };
4403
4404 static struct drm_gem_object *
4405 intel_alloc_power_context(struct drm_device *dev)
4406 {
4407 struct drm_gem_object *pwrctx;
4408 int ret;
4409
4410 pwrctx = drm_gem_object_alloc(dev, 4096);
4411 if (!pwrctx) {
4412 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4413 return NULL;
4414 }
4415
4416 mutex_lock(&dev->struct_mutex);
4417 ret = i915_gem_object_pin(pwrctx, 4096);
4418 if (ret) {
4419 DRM_ERROR("failed to pin power context: %d\n", ret);
4420 goto err_unref;
4421 }
4422
4423 ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4424 if (ret) {
4425 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4426 goto err_unpin;
4427 }
4428 mutex_unlock(&dev->struct_mutex);
4429
4430 return pwrctx;
4431
4432 err_unpin:
4433 i915_gem_object_unpin(pwrctx);
4434 err_unref:
4435 drm_gem_object_unreference(pwrctx);
4436 mutex_unlock(&dev->struct_mutex);
4437 return NULL;
4438 }
4439
4440 void intel_init_clock_gating(struct drm_device *dev)
4441 {
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443
4444 /*
4445 * Disable clock gating reported to work incorrectly according to the
4446 * specs, but enable as much else as we can.
4447 */
4448 if (IS_IRONLAKE(dev)) {
4449 return;
4450 } else if (IS_G4X(dev)) {
4451 uint32_t dspclk_gate;
4452 I915_WRITE(RENCLK_GATE_D1, 0);
4453 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4454 GS_UNIT_CLOCK_GATE_DISABLE |
4455 CL_UNIT_CLOCK_GATE_DISABLE);
4456 I915_WRITE(RAMCLK_GATE_D, 0);
4457 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4458 OVRUNIT_CLOCK_GATE_DISABLE |
4459 OVCUNIT_CLOCK_GATE_DISABLE;
4460 if (IS_GM45(dev))
4461 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4462 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4463 } else if (IS_I965GM(dev)) {
4464 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4465 I915_WRITE(RENCLK_GATE_D2, 0);
4466 I915_WRITE(DSPCLK_GATE_D, 0);
4467 I915_WRITE(RAMCLK_GATE_D, 0);
4468 I915_WRITE16(DEUC, 0);
4469 } else if (IS_I965G(dev)) {
4470 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4471 I965_RCC_CLOCK_GATE_DISABLE |
4472 I965_RCPB_CLOCK_GATE_DISABLE |
4473 I965_ISC_CLOCK_GATE_DISABLE |
4474 I965_FBC_CLOCK_GATE_DISABLE);
4475 I915_WRITE(RENCLK_GATE_D2, 0);
4476 } else if (IS_I9XX(dev)) {
4477 u32 dstate = I915_READ(D_STATE);
4478
4479 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4480 DSTATE_DOT_CLOCK_GATING;
4481 I915_WRITE(D_STATE, dstate);
4482 } else if (IS_I85X(dev) || IS_I865G(dev)) {
4483 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4484 } else if (IS_I830(dev)) {
4485 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4486 }
4487
4488 /*
4489 * GPU can automatically power down the render unit if given a page
4490 * to save state.
4491 */
4492 if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4493 struct drm_i915_gem_object *obj_priv = NULL;
4494
4495 if (dev_priv->pwrctx) {
4496 obj_priv = dev_priv->pwrctx->driver_private;
4497 } else {
4498 struct drm_gem_object *pwrctx;
4499
4500 pwrctx = intel_alloc_power_context(dev);
4501 if (pwrctx) {
4502 dev_priv->pwrctx = pwrctx;
4503 obj_priv = pwrctx->driver_private;
4504 }
4505 }
4506
4507 if (obj_priv) {
4508 I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4509 I915_WRITE(MCHBAR_RENDER_STANDBY,
4510 I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4511 }
4512 }
4513 }
4514
4515 /* Set up chip specific display functions */
4516 static void intel_init_display(struct drm_device *dev)
4517 {
4518 struct drm_i915_private *dev_priv = dev->dev_private;
4519
4520 /* We always want a DPMS function */
4521 if (IS_IRONLAKE(dev))
4522 dev_priv->display.dpms = ironlake_crtc_dpms;
4523 else
4524 dev_priv->display.dpms = i9xx_crtc_dpms;
4525
4526 /* Only mobile has FBC, leave pointers NULL for other chips */
4527 if (IS_MOBILE(dev)) {
4528 if (IS_GM45(dev)) {
4529 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4530 dev_priv->display.enable_fbc = g4x_enable_fbc;
4531 dev_priv->display.disable_fbc = g4x_disable_fbc;
4532 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4533 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4534 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4535 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4536 }
4537 /* 855GM needs testing */
4538 }
4539
4540 /* Returns the core display clock speed */
4541 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4542 dev_priv->display.get_display_clock_speed =
4543 i945_get_display_clock_speed;
4544 else if (IS_I915G(dev))
4545 dev_priv->display.get_display_clock_speed =
4546 i915_get_display_clock_speed;
4547 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4548 dev_priv->display.get_display_clock_speed =
4549 i9xx_misc_get_display_clock_speed;
4550 else if (IS_I915GM(dev))
4551 dev_priv->display.get_display_clock_speed =
4552 i915gm_get_display_clock_speed;
4553 else if (IS_I865G(dev))
4554 dev_priv->display.get_display_clock_speed =
4555 i865_get_display_clock_speed;
4556 else if (IS_I85X(dev))
4557 dev_priv->display.get_display_clock_speed =
4558 i855_get_display_clock_speed;
4559 else /* 852, 830 */
4560 dev_priv->display.get_display_clock_speed =
4561 i830_get_display_clock_speed;
4562
4563 /* For FIFO watermark updates */
4564 if (IS_IRONLAKE(dev))
4565 dev_priv->display.update_wm = NULL;
4566 else if (IS_G4X(dev))
4567 dev_priv->display.update_wm = g4x_update_wm;
4568 else if (IS_I965G(dev))
4569 dev_priv->display.update_wm = i965_update_wm;
4570 else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4571 dev_priv->display.update_wm = i9xx_update_wm;
4572 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4573 } else {
4574 if (IS_I85X(dev))
4575 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4576 else if (IS_845G(dev))
4577 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4578 else
4579 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4580 dev_priv->display.update_wm = i830_update_wm;
4581 }
4582 }
4583
4584 void intel_modeset_init(struct drm_device *dev)
4585 {
4586 struct drm_i915_private *dev_priv = dev->dev_private;
4587 int num_pipe;
4588 int i;
4589
4590 drm_mode_config_init(dev);
4591
4592 dev->mode_config.min_width = 0;
4593 dev->mode_config.min_height = 0;
4594
4595 dev->mode_config.funcs = (void *)&intel_mode_funcs;
4596
4597 intel_init_display(dev);
4598
4599 if (IS_I965G(dev)) {
4600 dev->mode_config.max_width = 8192;
4601 dev->mode_config.max_height = 8192;
4602 } else if (IS_I9XX(dev)) {
4603 dev->mode_config.max_width = 4096;
4604 dev->mode_config.max_height = 4096;
4605 } else {
4606 dev->mode_config.max_width = 2048;
4607 dev->mode_config.max_height = 2048;
4608 }
4609
4610 /* set memory base */
4611 if (IS_I9XX(dev))
4612 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4613 else
4614 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4615
4616 if (IS_MOBILE(dev) || IS_I9XX(dev))
4617 num_pipe = 2;
4618 else
4619 num_pipe = 1;
4620 DRM_DEBUG_KMS("%d display pipe%s available.\n",
4621 num_pipe, num_pipe > 1 ? "s" : "");
4622
4623 if (IS_I85X(dev))
4624 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4625 else if (IS_I9XX(dev) || IS_G4X(dev))
4626 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4627
4628 for (i = 0; i < num_pipe; i++) {
4629 intel_crtc_init(dev, i);
4630 }
4631
4632 intel_setup_outputs(dev);
4633
4634 intel_init_clock_gating(dev);
4635
4636 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4637 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4638 (unsigned long)dev);
4639
4640 intel_setup_overlay(dev);
4641
4642 if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4643 dev_priv->fsb_freq,
4644 dev_priv->mem_freq))
4645 DRM_INFO("failed to find known CxSR latency "
4646 "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4647 dev_priv->fsb_freq, dev_priv->mem_freq);
4648 }
4649
4650 void intel_modeset_cleanup(struct drm_device *dev)
4651 {
4652 struct drm_i915_private *dev_priv = dev->dev_private;
4653 struct drm_crtc *crtc;
4654 struct intel_crtc *intel_crtc;
4655
4656 mutex_lock(&dev->struct_mutex);
4657
4658 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4659 /* Skip inactive CRTCs */
4660 if (!crtc->fb)
4661 continue;
4662
4663 intel_crtc = to_intel_crtc(crtc);
4664 intel_increase_pllclock(crtc, false);
4665 del_timer_sync(&intel_crtc->idle_timer);
4666 }
4667
4668 del_timer_sync(&dev_priv->idle_timer);
4669
4670 if (dev_priv->display.disable_fbc)
4671 dev_priv->display.disable_fbc(dev);
4672
4673 if (dev_priv->pwrctx) {
4674 struct drm_i915_gem_object *obj_priv;
4675
4676 obj_priv = dev_priv->pwrctx->driver_private;
4677 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4678 I915_READ(PWRCTXA);
4679 i915_gem_object_unpin(dev_priv->pwrctx);
4680 drm_gem_object_unreference(dev_priv->pwrctx);
4681 }
4682
4683 mutex_unlock(&dev->struct_mutex);
4684
4685 drm_mode_config_cleanup(dev);
4686 }
4687
4688
4689 /* current intel driver doesn't take advantage of encoders
4690 always give back the encoder for the connector
4691 */
4692 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4693 {
4694 struct intel_output *intel_output = to_intel_output(connector);
4695
4696 return &intel_output->enc;
4697 }
4698
4699 /*
4700 * set vga decode state - true == enable VGA decode
4701 */
4702 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4703 {
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 u16 gmch_ctrl;
4706
4707 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4708 if (state)
4709 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4710 else
4711 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4712 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4713 return 0;
4714 }
CRIS linux kernel tree