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Linux 2.6.33-rc6
[cris-mirror.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
blob6b9690418bc73bbf580b4f54f60bdc838be81fce
1 /*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #ifndef __NOUVEAU_DRV_H__
26 #define __NOUVEAU_DRV_H__
27
28 #define DRIVER_AUTHOR "Stephane Marchesin"
29 #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31 #define DRIVER_NAME "nouveau"
32 #define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33 #define DRIVER_DATE "20090420"
34
35 #define DRIVER_MAJOR 0
36 #define DRIVER_MINOR 0
37 #define DRIVER_PATCHLEVEL 15
38
39 #define NOUVEAU_FAMILY 0x0000FFFF
40 #define NOUVEAU_FLAGS 0xFFFF0000
41
42 #include "ttm/ttm_bo_api.h"
43 #include "ttm/ttm_bo_driver.h"
44 #include "ttm/ttm_placement.h"
45 #include "ttm/ttm_memory.h"
46 #include "ttm/ttm_module.h"
47
48 struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50 };
51
52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54 #include "nouveau_drm.h"
55 #include "nouveau_reg.h"
56 #include "nouveau_bios.h"
57 struct nouveau_grctx;
58
59 #define MAX_NUM_DCB_ENTRIES 16
60
61 #define NOUVEAU_MAX_CHANNEL_NR 128
62 #define NOUVEAU_MAX_TILE_NR 15
63
64 #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65 #define NV50_VM_BLOCK (512*1024*1024ULL)
66 #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
68 struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73 };
74
75 struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
79 struct ttm_bo_kmap_obj kmap;
80 struct list_head head;
81
82 /* protected by ttm_bo_reserve() */
83 struct drm_file *reserved_by;
84 struct list_head entry;
85 int pbbo_index;
86
87 struct nouveau_channel *channel;
88
89 bool mappable;
90 bool no_vm;
91
92 uint32_t tile_mode;
93 uint32_t tile_flags;
94 struct nouveau_tile_reg *tile;
95
96 struct drm_gem_object *gem;
97 struct drm_file *cpu_filp;
98 int pin_refcnt;
99 };
100
101 static inline struct nouveau_bo *
102 nouveau_bo(struct ttm_buffer_object *bo)
103 {
104 return container_of(bo, struct nouveau_bo, bo);
105 }
106
107 static inline struct nouveau_bo *
108 nouveau_gem_object(struct drm_gem_object *gem)
109 {
110 return gem ? gem->driver_private : NULL;
111 }
112
113 /* TODO: submit equivalent to TTM generic API upstream? */
114 static inline void __iomem *
115 nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
116 {
117 bool is_iomem;
118 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
119 &nvbo->kmap, &is_iomem);
120 WARN_ON_ONCE(ioptr && !is_iomem);
121 return ioptr;
122 }
123
124 struct mem_block {
125 struct mem_block *next;
126 struct mem_block *prev;
127 uint64_t start;
128 uint64_t size;
129 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
130 };
131
132 enum nouveau_flags {
133 NV_NFORCE = 0x10000000,
134 NV_NFORCE2 = 0x20000000
135 };
136
137 #define NVOBJ_ENGINE_SW 0
138 #define NVOBJ_ENGINE_GR 1
139 #define NVOBJ_ENGINE_DISPLAY 2
140 #define NVOBJ_ENGINE_INT 0xdeadbeef
141
142 #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0)
143 #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
144 #define NVOBJ_FLAG_ZERO_FREE (1 << 2)
145 #define NVOBJ_FLAG_FAKE (1 << 3)
146 struct nouveau_gpuobj {
147 struct list_head list;
148
149 struct nouveau_channel *im_channel;
150 struct mem_block *im_pramin;
151 struct nouveau_bo *im_backing;
152 uint32_t im_backing_start;
153 uint32_t *im_backing_suspend;
154 int im_bound;
155
156 uint32_t flags;
157 int refcount;
158
159 uint32_t engine;
160 uint32_t class;
161
162 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
163 void *priv;
164 };
165
166 struct nouveau_gpuobj_ref {
167 struct list_head list;
168
169 struct nouveau_gpuobj *gpuobj;
170 uint32_t instance;
171
172 struct nouveau_channel *channel;
173 int handle;
174 };
175
176 struct nouveau_channel {
177 struct drm_device *dev;
178 int id;
179
180 /* owner of this fifo */
181 struct drm_file *file_priv;
182 /* mapping of the fifo itself */
183 struct drm_local_map *map;
184
185 /* mapping of the regs controling the fifo */
186 void __iomem *user;
187 uint32_t user_get;
188 uint32_t user_put;
189
190 /* Fencing */
191 struct {
192 /* lock protects the pending list only */
193 spinlock_t lock;
194 struct list_head pending;
195 uint32_t sequence;
196 uint32_t sequence_ack;
197 uint32_t last_sequence_irq;
198 } fence;
199
200 /* DMA push buffer */
201 struct nouveau_gpuobj_ref *pushbuf;
202 struct nouveau_bo *pushbuf_bo;
203 uint32_t pushbuf_base;
204
205 /* Notifier memory */
206 struct nouveau_bo *notifier_bo;
207 struct mem_block *notifier_heap;
208
209 /* PFIFO context */
210 struct nouveau_gpuobj_ref *ramfc;
211 struct nouveau_gpuobj_ref *cache;
212
213 /* PGRAPH context */
214 /* XXX may be merge 2 pointers as private data ??? */
215 struct nouveau_gpuobj_ref *ramin_grctx;
216 void *pgraph_ctx;
217
218 /* NV50 VM */
219 struct nouveau_gpuobj *vm_pd;
220 struct nouveau_gpuobj_ref *vm_gart_pt;
221 struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR];
222
223 /* Objects */
224 struct nouveau_gpuobj_ref *ramin; /* Private instmem */
225 struct mem_block *ramin_heap; /* Private PRAMIN heap */
226 struct nouveau_gpuobj_ref *ramht; /* Hash table */
227 struct list_head ramht_refs; /* Objects referenced by RAMHT */
228
229 /* GPU object info for stuff used in-kernel (mm_enabled) */
230 uint32_t m2mf_ntfy;
231 uint32_t vram_handle;
232 uint32_t gart_handle;
233 bool accel_done;
234
235 /* Push buffer state (only for drm's channel on !mm_enabled) */
236 struct {
237 int max;
238 int free;
239 int cur;
240 int put;
241 /* access via pushbuf_bo */
242 } dma;
243
244 uint32_t sw_subchannel[8];
245
246 struct {
247 struct nouveau_gpuobj *vblsem;
248 uint32_t vblsem_offset;
249 uint32_t vblsem_rval;
250 struct list_head vbl_wait;
251 } nvsw;
252
253 struct {
254 bool active;
255 char name[32];
256 struct drm_info_list info;
257 } debugfs;
258 };
259
260 struct nouveau_instmem_engine {
261 void *priv;
262
263 int (*init)(struct drm_device *dev);
264 void (*takedown)(struct drm_device *dev);
265 int (*suspend)(struct drm_device *dev);
266 void (*resume)(struct drm_device *dev);
267
268 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
269 uint32_t *size);
270 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
271 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
272 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
273 void (*prepare_access)(struct drm_device *, bool write);
274 void (*finish_access)(struct drm_device *);
275 };
276
277 struct nouveau_mc_engine {
278 int (*init)(struct drm_device *dev);
279 void (*takedown)(struct drm_device *dev);
280 };
281
282 struct nouveau_timer_engine {
283 int (*init)(struct drm_device *dev);
284 void (*takedown)(struct drm_device *dev);
285 uint64_t (*read)(struct drm_device *dev);
286 };
287
288 struct nouveau_fb_engine {
289 int num_tiles;
290
291 int (*init)(struct drm_device *dev);
292 void (*takedown)(struct drm_device *dev);
293
294 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
295 uint32_t size, uint32_t pitch);
296 };
297
298 struct nouveau_fifo_engine {
299 void *priv;
300
301 int channels;
302
303 int (*init)(struct drm_device *);
304 void (*takedown)(struct drm_device *);
305
306 void (*disable)(struct drm_device *);
307 void (*enable)(struct drm_device *);
308 bool (*reassign)(struct drm_device *, bool enable);
309 bool (*cache_flush)(struct drm_device *dev);
310 bool (*cache_pull)(struct drm_device *dev, bool enable);
311
312 int (*channel_id)(struct drm_device *);
313
314 int (*create_context)(struct nouveau_channel *);
315 void (*destroy_context)(struct nouveau_channel *);
316 int (*load_context)(struct nouveau_channel *);
317 int (*unload_context)(struct drm_device *);
318 };
319
320 struct nouveau_pgraph_object_method {
321 int id;
322 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
323 uint32_t data);
324 };
325
326 struct nouveau_pgraph_object_class {
327 int id;
328 bool software;
329 struct nouveau_pgraph_object_method *methods;
330 };
331
332 struct nouveau_pgraph_engine {
333 struct nouveau_pgraph_object_class *grclass;
334 bool accel_blocked;
335 void *ctxprog;
336 void *ctxvals;
337 int grctx_size;
338
339 int (*init)(struct drm_device *);
340 void (*takedown)(struct drm_device *);
341
342 void (*fifo_access)(struct drm_device *, bool);
343
344 struct nouveau_channel *(*channel)(struct drm_device *);
345 int (*create_context)(struct nouveau_channel *);
346 void (*destroy_context)(struct nouveau_channel *);
347 int (*load_context)(struct nouveau_channel *);
348 int (*unload_context)(struct drm_device *);
349
350 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
351 uint32_t size, uint32_t pitch);
352 };
353
354 struct nouveau_engine {
355 struct nouveau_instmem_engine instmem;
356 struct nouveau_mc_engine mc;
357 struct nouveau_timer_engine timer;
358 struct nouveau_fb_engine fb;
359 struct nouveau_pgraph_engine graph;
360 struct nouveau_fifo_engine fifo;
361 };
362
363 struct nouveau_pll_vals {
364 union {
365 struct {
366 #ifdef __BIG_ENDIAN
367 uint8_t N1, M1, N2, M2;
368 #else
369 uint8_t M1, N1, M2, N2;
370 #endif
371 };
372 struct {
373 uint16_t NM1, NM2;
374 } __attribute__((packed));
375 };
376 int log2P;
377
378 int refclk;
379 };
380
381 enum nv04_fp_display_regs {
382 FP_DISPLAY_END,
383 FP_TOTAL,
384 FP_CRTC,
385 FP_SYNC_START,
386 FP_SYNC_END,
387 FP_VALID_START,
388 FP_VALID_END
389 };
390
391 struct nv04_crtc_reg {
392 unsigned char MiscOutReg; /* */
393 uint8_t CRTC[0x9f];
394 uint8_t CR58[0x10];
395 uint8_t Sequencer[5];
396 uint8_t Graphics[9];
397 uint8_t Attribute[21];
398 unsigned char DAC[768]; /* Internal Colorlookuptable */
399
400 /* PCRTC regs */
401 uint32_t fb_start;
402 uint32_t crtc_cfg;
403 uint32_t cursor_cfg;
404 uint32_t gpio_ext;
405 uint32_t crtc_830;
406 uint32_t crtc_834;
407 uint32_t crtc_850;
408 uint32_t crtc_eng_ctrl;
409
410 /* PRAMDAC regs */
411 uint32_t nv10_cursync;
412 struct nouveau_pll_vals pllvals;
413 uint32_t ramdac_gen_ctrl;
414 uint32_t ramdac_630;
415 uint32_t ramdac_634;
416 uint32_t tv_setup;
417 uint32_t tv_vtotal;
418 uint32_t tv_vskew;
419 uint32_t tv_vsync_delay;
420 uint32_t tv_htotal;
421 uint32_t tv_hskew;
422 uint32_t tv_hsync_delay;
423 uint32_t tv_hsync_delay2;
424 uint32_t fp_horiz_regs[7];
425 uint32_t fp_vert_regs[7];
426 uint32_t dither;
427 uint32_t fp_control;
428 uint32_t dither_regs[6];
429 uint32_t fp_debug_0;
430 uint32_t fp_debug_1;
431 uint32_t fp_debug_2;
432 uint32_t fp_margin_color;
433 uint32_t ramdac_8c0;
434 uint32_t ramdac_a20;
435 uint32_t ramdac_a24;
436 uint32_t ramdac_a34;
437 uint32_t ctv_regs[38];
438 };
439
440 struct nv04_output_reg {
441 uint32_t output;
442 int head;
443 };
444
445 struct nv04_mode_state {
446 uint32_t bpp;
447 uint32_t width;
448 uint32_t height;
449 uint32_t interlace;
450 uint32_t repaint0;
451 uint32_t repaint1;
452 uint32_t screen;
453 uint32_t scale;
454 uint32_t dither;
455 uint32_t extra;
456 uint32_t fifo;
457 uint32_t pixel;
458 uint32_t horiz;
459 int arbitration0;
460 int arbitration1;
461 uint32_t pll;
462 uint32_t pllB;
463 uint32_t vpll;
464 uint32_t vpll2;
465 uint32_t vpllB;
466 uint32_t vpll2B;
467 uint32_t pllsel;
468 uint32_t sel_clk;
469 uint32_t general;
470 uint32_t crtcOwner;
471 uint32_t head;
472 uint32_t head2;
473 uint32_t cursorConfig;
474 uint32_t cursor0;
475 uint32_t cursor1;
476 uint32_t cursor2;
477 uint32_t timingH;
478 uint32_t timingV;
479 uint32_t displayV;
480 uint32_t crtcSync;
481
482 struct nv04_crtc_reg crtc_reg[2];
483 };
484
485 enum nouveau_card_type {
486 NV_04 = 0x00,
487 NV_10 = 0x10,
488 NV_20 = 0x20,
489 NV_30 = 0x30,
490 NV_40 = 0x40,
491 NV_50 = 0x50,
492 };
493
494 struct drm_nouveau_private {
495 struct drm_device *dev;
496 enum {
497 NOUVEAU_CARD_INIT_DOWN,
498 NOUVEAU_CARD_INIT_DONE,
499 NOUVEAU_CARD_INIT_FAILED
500 } init_state;
501
502 /* the card type, takes NV_* as values */
503 enum nouveau_card_type card_type;
504 /* exact chipset, derived from NV_PMC_BOOT_0 */
505 int chipset;
506 int flags;
507
508 void __iomem *mmio;
509 void __iomem *ramin;
510 uint32_t ramin_size;
511
512 struct nouveau_bo *vga_ram;
513
514 struct workqueue_struct *wq;
515 struct work_struct irq_work;
516
517 struct list_head vbl_waiting;
518
519 struct {
520 struct ttm_global_reference mem_global_ref;
521 struct ttm_bo_global_ref bo_global_ref;
522 struct ttm_bo_device bdev;
523 spinlock_t bo_list_lock;
524 struct list_head bo_list;
525 atomic_t validate_sequence;
526 } ttm;
527
528 struct fb_info *fbdev_info;
529
530 int fifo_alloc_count;
531 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
532
533 struct nouveau_engine engine;
534 struct nouveau_channel *channel;
535
536 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
537 struct nouveau_gpuobj *ramht;
538 uint32_t ramin_rsvd_vram;
539 uint32_t ramht_offset;
540 uint32_t ramht_size;
541 uint32_t ramht_bits;
542 uint32_t ramfc_offset;
543 uint32_t ramfc_size;
544 uint32_t ramro_offset;
545 uint32_t ramro_size;
546
547 /* base physical adresses */
548 uint64_t fb_phys;
549 uint64_t fb_available_size;
550 uint64_t fb_mappable_pages;
551 uint64_t fb_aper_free;
552
553 struct {
554 enum {
555 NOUVEAU_GART_NONE = 0,
556 NOUVEAU_GART_AGP,
557 NOUVEAU_GART_SGDMA
558 } type;
559 uint64_t aper_base;
560 uint64_t aper_size;
561 uint64_t aper_free;
562
563 struct nouveau_gpuobj *sg_ctxdma;
564 struct page *sg_dummy_page;
565 dma_addr_t sg_dummy_bus;
566
567 /* nottm hack */
568 struct drm_ttm_backend *sg_be;
569 unsigned long sg_handle;
570 } gart_info;
571
572 /* nv10-nv40 tiling regions */
573 struct {
574 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
575 spinlock_t lock;
576 } tile;
577
578 /* G8x/G9x virtual address space */
579 uint64_t vm_gart_base;
580 uint64_t vm_gart_size;
581 uint64_t vm_vram_base;
582 uint64_t vm_vram_size;
583 uint64_t vm_end;
584 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
585 int vm_vram_pt_nr;
586
587 /* the mtrr covering the FB */
588 int fb_mtrr;
589
590 struct mem_block *ramin_heap;
591
592 /* context table pointed to be NV_PGRAPH_CHANNEL_CTX_TABLE (0x400780) */
593 uint32_t ctx_table_size;
594 struct nouveau_gpuobj_ref *ctx_table;
595
596 struct list_head gpuobj_list;
597
598 struct nvbios VBIOS;
599 struct nouveau_bios_info *vbios;
600
601 struct nv04_mode_state mode_reg;
602 struct nv04_mode_state saved_reg;
603 uint32_t saved_vga_font[4][16384];
604 uint32_t crtc_owner;
605 uint32_t dac_users[4];
606
607 struct nouveau_suspend_resume {
608 uint32_t fifo_mode;
609 uint32_t graph_ctx_control;
610 uint32_t graph_state;
611 uint32_t *ramin_copy;
612 uint64_t ramin_size;
613 } susres;
614
615 struct backlight_device *backlight;
616 bool acpi_dsm;
617
618 struct nouveau_channel *evo;
619
620 struct {
621 struct dentry *channel_root;
622 } debugfs;
623 };
624
625 static inline struct drm_nouveau_private *
626 nouveau_bdev(struct ttm_bo_device *bd)
627 {
628 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
629 }
630
631 static inline int
632 nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
633 {
634 struct nouveau_bo *prev;
635
636 if (!pnvbo)
637 return -EINVAL;
638 prev = *pnvbo;
639
640 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
641 if (prev) {
642 struct ttm_buffer_object *bo = &prev->bo;
643
644 ttm_bo_unref(&bo);
645 }
646
647 return 0;
648 }
649
650 #define NOUVEAU_CHECK_INITIALISED_WITH_RETURN do { \
651 struct drm_nouveau_private *nv = dev->dev_private; \
652 if (nv->init_state != NOUVEAU_CARD_INIT_DONE) { \
653 NV_ERROR(dev, "called without init\n"); \
654 return -EINVAL; \
655 } \
656 } while (0)
657
658 #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
659 struct drm_nouveau_private *nv = dev->dev_private; \
660 if (!nouveau_channel_owner(dev, (cl), (id))) { \
661 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
662 DRM_CURRENTPID, (id)); \
663 return -EPERM; \
664 } \
665 (ch) = nv->fifos[(id)]; \
666 } while (0)
667
668 /* nouveau_drv.c */
669 extern int nouveau_noagp;
670 extern int nouveau_duallink;
671 extern int nouveau_uscript_lvds;
672 extern int nouveau_uscript_tmds;
673 extern int nouveau_vram_pushbuf;
674 extern int nouveau_vram_notify;
675 extern int nouveau_fbpercrtc;
676 extern char *nouveau_tv_norm;
677 extern int nouveau_reg_debug;
678 extern char *nouveau_vbios;
679 extern int nouveau_ctxfw;
680 extern int nouveau_ignorelid;
681
682 /* nouveau_state.c */
683 extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
684 extern int nouveau_load(struct drm_device *, unsigned long flags);
685 extern int nouveau_firstopen(struct drm_device *);
686 extern void nouveau_lastclose(struct drm_device *);
687 extern int nouveau_unload(struct drm_device *);
688 extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
689 struct drm_file *);
690 extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
691 struct drm_file *);
692 extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
693 uint32_t reg, uint32_t mask, uint32_t val);
694 extern bool nouveau_wait_for_idle(struct drm_device *);
695 extern int nouveau_card_init(struct drm_device *);
696 extern int nouveau_ioctl_card_init(struct drm_device *, void *data,
697 struct drm_file *);
698 extern int nouveau_ioctl_suspend(struct drm_device *, void *data,
699 struct drm_file *);
700 extern int nouveau_ioctl_resume(struct drm_device *, void *data,
701 struct drm_file *);
702
703 /* nouveau_mem.c */
704 extern int nouveau_mem_init_heap(struct mem_block **, uint64_t start,
705 uint64_t size);
706 extern struct mem_block *nouveau_mem_alloc_block(struct mem_block *,
707 uint64_t size, int align2,
708 struct drm_file *, int tail);
709 extern void nouveau_mem_takedown(struct mem_block **heap);
710 extern void nouveau_mem_free_block(struct mem_block *);
711 extern uint64_t nouveau_mem_fb_amount(struct drm_device *);
712 extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap);
713 extern int nouveau_mem_init(struct drm_device *);
714 extern int nouveau_mem_init_agp(struct drm_device *);
715 extern void nouveau_mem_close(struct drm_device *);
716 extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
717 uint32_t addr,
718 uint32_t size,
719 uint32_t pitch);
720 extern void nv10_mem_expire_tiling(struct drm_device *dev,
721 struct nouveau_tile_reg *tile,
722 struct nouveau_fence *fence);
723 extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
724 uint32_t size, uint32_t flags,
725 uint64_t phys);
726 extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
727 uint32_t size);
728
729 /* nouveau_notifier.c */
730 extern int nouveau_notifier_init_channel(struct nouveau_channel *);
731 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
732 extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
733 int cout, uint32_t *offset);
734 extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
735 extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
736 struct drm_file *);
737 extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
738 struct drm_file *);
739
740 /* nouveau_channel.c */
741 extern struct drm_ioctl_desc nouveau_ioctls[];
742 extern int nouveau_max_ioctl;
743 extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
744 extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
745 int channel);
746 extern int nouveau_channel_alloc(struct drm_device *dev,
747 struct nouveau_channel **chan,
748 struct drm_file *file_priv,
749 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
750 extern void nouveau_channel_free(struct nouveau_channel *);
751
752 /* nouveau_object.c */
753 extern int nouveau_gpuobj_early_init(struct drm_device *);
754 extern int nouveau_gpuobj_init(struct drm_device *);
755 extern void nouveau_gpuobj_takedown(struct drm_device *);
756 extern void nouveau_gpuobj_late_takedown(struct drm_device *);
757 extern int nouveau_gpuobj_suspend(struct drm_device *dev);
758 extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
759 extern void nouveau_gpuobj_resume(struct drm_device *dev);
760 extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
761 uint32_t vram_h, uint32_t tt_h);
762 extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
763 extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
764 uint32_t size, int align, uint32_t flags,
765 struct nouveau_gpuobj **);
766 extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **);
767 extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *,
768 uint32_t handle, struct nouveau_gpuobj *,
769 struct nouveau_gpuobj_ref **);
770 extern int nouveau_gpuobj_ref_del(struct drm_device *,
771 struct nouveau_gpuobj_ref **);
772 extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle,
773 struct nouveau_gpuobj_ref **ref_ret);
774 extern int nouveau_gpuobj_new_ref(struct drm_device *,
775 struct nouveau_channel *alloc_chan,
776 struct nouveau_channel *ref_chan,
777 uint32_t handle, uint32_t size, int align,
778 uint32_t flags, struct nouveau_gpuobj_ref **);
779 extern int nouveau_gpuobj_new_fake(struct drm_device *,
780 uint32_t p_offset, uint32_t b_offset,
781 uint32_t size, uint32_t flags,
782 struct nouveau_gpuobj **,
783 struct nouveau_gpuobj_ref**);
784 extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
785 uint64_t offset, uint64_t size, int access,
786 int target, struct nouveau_gpuobj **);
787 extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
788 uint64_t offset, uint64_t size,
789 int access, struct nouveau_gpuobj **,
790 uint32_t *o_ret);
791 extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
792 struct nouveau_gpuobj **);
793 extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
794 struct nouveau_gpuobj **);
795 extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
796 struct drm_file *);
797 extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
798 struct drm_file *);
799
800 /* nouveau_irq.c */
801 extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
802 extern void nouveau_irq_preinstall(struct drm_device *);
803 extern int nouveau_irq_postinstall(struct drm_device *);
804 extern void nouveau_irq_uninstall(struct drm_device *);
805
806 /* nouveau_sgdma.c */
807 extern int nouveau_sgdma_init(struct drm_device *);
808 extern void nouveau_sgdma_takedown(struct drm_device *);
809 extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
810 uint32_t *page);
811 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
812
813 /* nouveau_debugfs.c */
814 #if defined(CONFIG_DRM_NOUVEAU_DEBUG)
815 extern int nouveau_debugfs_init(struct drm_minor *);
816 extern void nouveau_debugfs_takedown(struct drm_minor *);
817 extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
818 extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
819 #else
820 static inline int
821 nouveau_debugfs_init(struct drm_minor *minor)
822 {
823 return 0;
824 }
825
826 static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
827 {
828 }
829
830 static inline int
831 nouveau_debugfs_channel_init(struct nouveau_channel *chan)
832 {
833 return 0;
834 }
835
836 static inline void
837 nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
838 {
839 }
840 #endif
841
842 /* nouveau_dma.c */
843 extern void nouveau_dma_pre_init(struct nouveau_channel *);
844 extern int nouveau_dma_init(struct nouveau_channel *);
845 extern int nouveau_dma_wait(struct nouveau_channel *, int size);
846
847 /* nouveau_acpi.c */
848 #ifdef CONFIG_ACPI
849 extern int nouveau_hybrid_setup(struct drm_device *dev);
850 extern bool nouveau_dsm_probe(struct drm_device *dev);
851 #else
852 static inline int nouveau_hybrid_setup(struct drm_device *dev)
853 {
854 return 0;
855 }
856 static inline bool nouveau_dsm_probe(struct drm_device *dev)
857 {
858 return false;
859 }
860 #endif
861
862 /* nouveau_backlight.c */
863 #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
864 extern int nouveau_backlight_init(struct drm_device *);
865 extern void nouveau_backlight_exit(struct drm_device *);
866 #else
867 static inline int nouveau_backlight_init(struct drm_device *dev)
868 {
869 return 0;
870 }
871
872 static inline void nouveau_backlight_exit(struct drm_device *dev) { }
873 #endif
874
875 /* nouveau_bios.c */
876 extern int nouveau_bios_init(struct drm_device *);
877 extern void nouveau_bios_takedown(struct drm_device *dev);
878 extern int nouveau_run_vbios_init(struct drm_device *);
879 extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
880 struct dcb_entry *);
881 extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
882 enum dcb_gpio_tag);
883 extern struct dcb_connector_table_entry *
884 nouveau_bios_connector_entry(struct drm_device *, int index);
885 extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
886 struct pll_lims *);
887 extern int nouveau_bios_run_display_table(struct drm_device *,
888 struct dcb_entry *,
889 uint32_t script, int pxclk);
890 extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
891 int *length);
892 extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
893 extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
894 extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
895 bool *dl, bool *if_is_24bit);
896 extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
897 int head, int pxclk);
898 extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
899 enum LVDS_script, int pxclk);
900
901 /* nouveau_ttm.c */
902 int nouveau_ttm_global_init(struct drm_nouveau_private *);
903 void nouveau_ttm_global_release(struct drm_nouveau_private *);
904 int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
905
906 /* nouveau_dp.c */
907 int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
908 uint8_t *data, int data_nr);
909 bool nouveau_dp_detect(struct drm_encoder *);
910 bool nouveau_dp_link_train(struct drm_encoder *);
911
912 /* nv04_fb.c */
913 extern int nv04_fb_init(struct drm_device *);
914 extern void nv04_fb_takedown(struct drm_device *);
915
916 /* nv10_fb.c */
917 extern int nv10_fb_init(struct drm_device *);
918 extern void nv10_fb_takedown(struct drm_device *);
919 extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
920 uint32_t, uint32_t);
921
922 /* nv40_fb.c */
923 extern int nv40_fb_init(struct drm_device *);
924 extern void nv40_fb_takedown(struct drm_device *);
925 extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
926 uint32_t, uint32_t);
927
928 /* nv04_fifo.c */
929 extern int nv04_fifo_init(struct drm_device *);
930 extern void nv04_fifo_disable(struct drm_device *);
931 extern void nv04_fifo_enable(struct drm_device *);
932 extern bool nv04_fifo_reassign(struct drm_device *, bool);
933 extern bool nv04_fifo_cache_flush(struct drm_device *);
934 extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
935 extern int nv04_fifo_channel_id(struct drm_device *);
936 extern int nv04_fifo_create_context(struct nouveau_channel *);
937 extern void nv04_fifo_destroy_context(struct nouveau_channel *);
938 extern int nv04_fifo_load_context(struct nouveau_channel *);
939 extern int nv04_fifo_unload_context(struct drm_device *);
940
941 /* nv10_fifo.c */
942 extern int nv10_fifo_init(struct drm_device *);
943 extern int nv10_fifo_channel_id(struct drm_device *);
944 extern int nv10_fifo_create_context(struct nouveau_channel *);
945 extern void nv10_fifo_destroy_context(struct nouveau_channel *);
946 extern int nv10_fifo_load_context(struct nouveau_channel *);
947 extern int nv10_fifo_unload_context(struct drm_device *);
948
949 /* nv40_fifo.c */
950 extern int nv40_fifo_init(struct drm_device *);
951 extern int nv40_fifo_create_context(struct nouveau_channel *);
952 extern void nv40_fifo_destroy_context(struct nouveau_channel *);
953 extern int nv40_fifo_load_context(struct nouveau_channel *);
954 extern int nv40_fifo_unload_context(struct drm_device *);
955
956 /* nv50_fifo.c */
957 extern int nv50_fifo_init(struct drm_device *);
958 extern void nv50_fifo_takedown(struct drm_device *);
959 extern int nv50_fifo_channel_id(struct drm_device *);
960 extern int nv50_fifo_create_context(struct nouveau_channel *);
961 extern void nv50_fifo_destroy_context(struct nouveau_channel *);
962 extern int nv50_fifo_load_context(struct nouveau_channel *);
963 extern int nv50_fifo_unload_context(struct drm_device *);
964
965 /* nv04_graph.c */
966 extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
967 extern int nv04_graph_init(struct drm_device *);
968 extern void nv04_graph_takedown(struct drm_device *);
969 extern void nv04_graph_fifo_access(struct drm_device *, bool);
970 extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
971 extern int nv04_graph_create_context(struct nouveau_channel *);
972 extern void nv04_graph_destroy_context(struct nouveau_channel *);
973 extern int nv04_graph_load_context(struct nouveau_channel *);
974 extern int nv04_graph_unload_context(struct drm_device *);
975 extern void nv04_graph_context_switch(struct drm_device *);
976
977 /* nv10_graph.c */
978 extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
979 extern int nv10_graph_init(struct drm_device *);
980 extern void nv10_graph_takedown(struct drm_device *);
981 extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
982 extern int nv10_graph_create_context(struct nouveau_channel *);
983 extern void nv10_graph_destroy_context(struct nouveau_channel *);
984 extern int nv10_graph_load_context(struct nouveau_channel *);
985 extern int nv10_graph_unload_context(struct drm_device *);
986 extern void nv10_graph_context_switch(struct drm_device *);
987 extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
988 uint32_t, uint32_t);
989
990 /* nv20_graph.c */
991 extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
992 extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
993 extern int nv20_graph_create_context(struct nouveau_channel *);
994 extern void nv20_graph_destroy_context(struct nouveau_channel *);
995 extern int nv20_graph_load_context(struct nouveau_channel *);
996 extern int nv20_graph_unload_context(struct drm_device *);
997 extern int nv20_graph_init(struct drm_device *);
998 extern void nv20_graph_takedown(struct drm_device *);
999 extern int nv30_graph_init(struct drm_device *);
1000 extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1001 uint32_t, uint32_t);
1002
1003 /* nv40_graph.c */
1004 extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1005 extern int nv40_graph_init(struct drm_device *);
1006 extern void nv40_graph_takedown(struct drm_device *);
1007 extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1008 extern int nv40_graph_create_context(struct nouveau_channel *);
1009 extern void nv40_graph_destroy_context(struct nouveau_channel *);
1010 extern int nv40_graph_load_context(struct nouveau_channel *);
1011 extern int nv40_graph_unload_context(struct drm_device *);
1012 extern void nv40_grctx_init(struct nouveau_grctx *);
1013 extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1014 uint32_t, uint32_t);
1015
1016 /* nv50_graph.c */
1017 extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1018 extern int nv50_graph_init(struct drm_device *);
1019 extern void nv50_graph_takedown(struct drm_device *);
1020 extern void nv50_graph_fifo_access(struct drm_device *, bool);
1021 extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1022 extern int nv50_graph_create_context(struct nouveau_channel *);
1023 extern void nv50_graph_destroy_context(struct nouveau_channel *);
1024 extern int nv50_graph_load_context(struct nouveau_channel *);
1025 extern int nv50_graph_unload_context(struct drm_device *);
1026 extern void nv50_graph_context_switch(struct drm_device *);
1027
1028 /* nouveau_grctx.c */
1029 extern int nouveau_grctx_prog_load(struct drm_device *);
1030 extern void nouveau_grctx_vals_load(struct drm_device *,
1031 struct nouveau_gpuobj *);
1032 extern void nouveau_grctx_fini(struct drm_device *);
1033
1034 /* nv04_instmem.c */
1035 extern int nv04_instmem_init(struct drm_device *);
1036 extern void nv04_instmem_takedown(struct drm_device *);
1037 extern int nv04_instmem_suspend(struct drm_device *);
1038 extern void nv04_instmem_resume(struct drm_device *);
1039 extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1040 uint32_t *size);
1041 extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1042 extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1043 extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1044 extern void nv04_instmem_prepare_access(struct drm_device *, bool write);
1045 extern void nv04_instmem_finish_access(struct drm_device *);
1046
1047 /* nv50_instmem.c */
1048 extern int nv50_instmem_init(struct drm_device *);
1049 extern void nv50_instmem_takedown(struct drm_device *);
1050 extern int nv50_instmem_suspend(struct drm_device *);
1051 extern void nv50_instmem_resume(struct drm_device *);
1052 extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1053 uint32_t *size);
1054 extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1055 extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1056 extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1057 extern void nv50_instmem_prepare_access(struct drm_device *, bool write);
1058 extern void nv50_instmem_finish_access(struct drm_device *);
1059
1060 /* nv04_mc.c */
1061 extern int nv04_mc_init(struct drm_device *);
1062 extern void nv04_mc_takedown(struct drm_device *);
1063
1064 /* nv40_mc.c */
1065 extern int nv40_mc_init(struct drm_device *);
1066 extern void nv40_mc_takedown(struct drm_device *);
1067
1068 /* nv50_mc.c */
1069 extern int nv50_mc_init(struct drm_device *);
1070 extern void nv50_mc_takedown(struct drm_device *);
1071
1072 /* nv04_timer.c */
1073 extern int nv04_timer_init(struct drm_device *);
1074 extern uint64_t nv04_timer_read(struct drm_device *);
1075 extern void nv04_timer_takedown(struct drm_device *);
1076
1077 extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1078 unsigned long arg);
1079
1080 /* nv04_dac.c */
1081 extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry);
1082 extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
1083 extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1084 extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
1085
1086 /* nv04_dfp.c */
1087 extern int nv04_dfp_create(struct drm_device *dev, struct dcb_entry *entry);
1088 extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1089 extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1090 int head, bool dl);
1091 extern void nv04_dfp_disable(struct drm_device *dev, int head);
1092 extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1093
1094 /* nv04_tv.c */
1095 extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
1096 extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1097
1098 /* nv17_tv.c */
1099 extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry);
1100
1101 /* nv04_display.c */
1102 extern int nv04_display_create(struct drm_device *);
1103 extern void nv04_display_destroy(struct drm_device *);
1104 extern void nv04_display_restore(struct drm_device *);
1105
1106 /* nv04_crtc.c */
1107 extern int nv04_crtc_create(struct drm_device *, int index);
1108
1109 /* nouveau_bo.c */
1110 extern struct ttm_bo_driver nouveau_bo_driver;
1111 extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1112 int size, int align, uint32_t flags,
1113 uint32_t tile_mode, uint32_t tile_flags,
1114 bool no_vm, bool mappable, struct nouveau_bo **);
1115 extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1116 extern int nouveau_bo_unpin(struct nouveau_bo *);
1117 extern int nouveau_bo_map(struct nouveau_bo *);
1118 extern void nouveau_bo_unmap(struct nouveau_bo *);
1119 extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t memtype);
1120 extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1121 extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1122 extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1123 extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1124
1125 /* nouveau_fence.c */
1126 struct nouveau_fence;
1127 extern int nouveau_fence_init(struct nouveau_channel *);
1128 extern void nouveau_fence_fini(struct nouveau_channel *);
1129 extern void nouveau_fence_update(struct nouveau_channel *);
1130 extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1131 bool emit);
1132 extern int nouveau_fence_emit(struct nouveau_fence *);
1133 struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1134 extern bool nouveau_fence_signalled(void *obj, void *arg);
1135 extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1136 extern int nouveau_fence_flush(void *obj, void *arg);
1137 extern void nouveau_fence_unref(void **obj);
1138 extern void *nouveau_fence_ref(void *obj);
1139 extern void nouveau_fence_handler(struct drm_device *dev, int channel);
1140
1141 /* nouveau_gem.c */
1142 extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1143 int size, int align, uint32_t flags,
1144 uint32_t tile_mode, uint32_t tile_flags,
1145 bool no_vm, bool mappable, struct nouveau_bo **);
1146 extern int nouveau_gem_object_new(struct drm_gem_object *);
1147 extern void nouveau_gem_object_del(struct drm_gem_object *);
1148 extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1149 struct drm_file *);
1150 extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1151 struct drm_file *);
1152 extern int nouveau_gem_ioctl_pushbuf_call(struct drm_device *, void *,
1153 struct drm_file *);
1154 extern int nouveau_gem_ioctl_pushbuf_call2(struct drm_device *, void *,
1155 struct drm_file *);
1156 extern int nouveau_gem_ioctl_pin(struct drm_device *, void *,
1157 struct drm_file *);
1158 extern int nouveau_gem_ioctl_unpin(struct drm_device *, void *,
1159 struct drm_file *);
1160 extern int nouveau_gem_ioctl_tile(struct drm_device *, void *,
1161 struct drm_file *);
1162 extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1163 struct drm_file *);
1164 extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1165 struct drm_file *);
1166 extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1167 struct drm_file *);
1168
1169 /* nv17_gpio.c */
1170 int nv17_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1171 int nv17_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
1172
1173 #ifndef ioread32_native
1174 #ifdef __BIG_ENDIAN
1175 #define ioread16_native ioread16be
1176 #define iowrite16_native iowrite16be
1177 #define ioread32_native ioread32be
1178 #define iowrite32_native iowrite32be
1179 #else /* def __BIG_ENDIAN */
1180 #define ioread16_native ioread16
1181 #define iowrite16_native iowrite16
1182 #define ioread32_native ioread32
1183 #define iowrite32_native iowrite32
1184 #endif /* def __BIG_ENDIAN else */
1185 #endif /* !ioread32_native */
1186
1187 /* channel control reg access */
1188 static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1189 {
1190 return ioread32_native(chan->user + reg);
1191 }
1192
1193 static inline void nvchan_wr32(struct nouveau_channel *chan,
1194 unsigned reg, u32 val)
1195 {
1196 iowrite32_native(val, chan->user + reg);
1197 }
1198
1199 /* register access */
1200 static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1201 {
1202 struct drm_nouveau_private *dev_priv = dev->dev_private;
1203 return ioread32_native(dev_priv->mmio + reg);
1204 }
1205
1206 static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1207 {
1208 struct drm_nouveau_private *dev_priv = dev->dev_private;
1209 iowrite32_native(val, dev_priv->mmio + reg);
1210 }
1211
1212 static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1213 {
1214 struct drm_nouveau_private *dev_priv = dev->dev_private;
1215 return ioread8(dev_priv->mmio + reg);
1216 }
1217
1218 static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1219 {
1220 struct drm_nouveau_private *dev_priv = dev->dev_private;
1221 iowrite8(val, dev_priv->mmio + reg);
1222 }
1223
1224 #define nv_wait(reg, mask, val) \
1225 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1226
1227 /* PRAMIN access */
1228 static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1229 {
1230 struct drm_nouveau_private *dev_priv = dev->dev_private;
1231 return ioread32_native(dev_priv->ramin + offset);
1232 }
1233
1234 static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1235 {
1236 struct drm_nouveau_private *dev_priv = dev->dev_private;
1237 iowrite32_native(val, dev_priv->ramin + offset);
1238 }
1239
1240 /* object access */
1241 static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1242 unsigned index)
1243 {
1244 return nv_ri32(dev, obj->im_pramin->start + index * 4);
1245 }
1246
1247 static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj,
1248 unsigned index, u32 val)
1249 {
1250 nv_wi32(dev, obj->im_pramin->start + index * 4, val);
1251 }
1252
1253 /*
1254 * Logging
1255 * Argument d is (struct drm_device *).
1256 */
1257 #define NV_PRINTK(level, d, fmt, arg...) \
1258 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1259 pci_name(d->pdev), ##arg)
1260 #ifndef NV_DEBUG_NOTRACE
1261 #define NV_DEBUG(d, fmt, arg...) do { \
1262 if (drm_debug & DRM_UT_DRIVER) { \
1263 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1264 __LINE__, ##arg); \
1265 } \
1266 } while (0)
1267 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1268 if (drm_debug & DRM_UT_KMS) { \
1269 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1270 __LINE__, ##arg); \
1271 } \
1272 } while (0)
1273 #else
1274 #define NV_DEBUG(d, fmt, arg...) do { \
1275 if (drm_debug & DRM_UT_DRIVER) \
1276 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1277 } while (0)
1278 #define NV_DEBUG_KMS(d, fmt, arg...) do { \
1279 if (drm_debug & DRM_UT_KMS) \
1280 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1281 } while (0)
1282 #endif
1283 #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1284 #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1285 #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1286 #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1287 #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1288
1289 /* nouveau_reg_debug bitmask */
1290 enum {
1291 NOUVEAU_REG_DEBUG_MC = 0x1,
1292 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1293 NOUVEAU_REG_DEBUG_FB = 0x4,
1294 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1295 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1296 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1297 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1298 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1299 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1300 NOUVEAU_REG_DEBUG_EVO = 0x200,
1301 };
1302
1303 #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1304 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1305 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1306 } while (0)
1307
1308 static inline bool
1309 nv_two_heads(struct drm_device *dev)
1310 {
1311 struct drm_nouveau_private *dev_priv = dev->dev_private;
1312 const int impl = dev->pci_device & 0x0ff0;
1313
1314 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1315 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1316 return true;
1317
1318 return false;
1319 }
1320
1321 static inline bool
1322 nv_gf4_disp_arch(struct drm_device *dev)
1323 {
1324 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1325 }
1326
1327 static inline bool
1328 nv_two_reg_pll(struct drm_device *dev)
1329 {
1330 struct drm_nouveau_private *dev_priv = dev->dev_private;
1331 const int impl = dev->pci_device & 0x0ff0;
1332
1333 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1334 return true;
1335 return false;
1336 }
1337
1338 #define NV_SW 0x0000506e
1339 #define NV_SW_DMA_SEMAPHORE 0x00000060
1340 #define NV_SW_SEMAPHORE_OFFSET 0x00000064
1341 #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1342 #define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1343 #define NV_SW_DMA_VBLSEM 0x0000018c
1344 #define NV_SW_VBLSEM_OFFSET 0x00000400
1345 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1346 #define NV_SW_VBLSEM_RELEASE 0x00000408
1347
1348 #endif /* __NOUVEAU_DRV_H__ */
CRIS linux kernel tree