drivers/gpu/drm/nouveau/nv40_fb.c

   1 #include "drmP.h"
   2 #include "drm.h"
   3 #include "nouveau_drv.h"
   4 #include "nouveau_drm.h"
   5
   6 void
   7 nv40_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
   8                           uint32_t size, uint32_t pitch)
   9 {
  10         struct drm_nouveau_private *dev_priv = dev->dev_private;
  11         uint32_t limit = max(1u, addr + size) - 1;
  12
  13         if (pitch)
  14                 addr |= 1;
  15
  16         switch (dev_priv->chipset) {
  17         case 0x40:
  18                 nv_wr32(dev, NV10_PFB_TLIMIT(i), limit);
  19                 nv_wr32(dev, NV10_PFB_TSIZE(i), pitch);
  20                 nv_wr32(dev, NV10_PFB_TILE(i), addr);
  21                 break;
  22
  23         default:
  24                 nv_wr32(dev, NV40_PFB_TLIMIT(i), limit);
  25                 nv_wr32(dev, NV40_PFB_TSIZE(i), pitch);
  26                 nv_wr32(dev, NV40_PFB_TILE(i), addr);
  27                 break;
  28         }
  29 }
  30
  31 int
  32 nv40_fb_init(struct drm_device *dev)
  33 {
  34         struct drm_nouveau_private *dev_priv = dev->dev_private;
  35         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  36         uint32_t tmp;
  37         int i;
  38
  39         /* This is strictly a NV4x register (don't know about NV5x). */
  40         /* The blob sets these to all kinds of values, and they mess up our setup. */
  41         /* I got value 0x52802 instead. For some cards the blob even sets it back to 0x1. */
  42         /* Note: the blob doesn't read this value, so i'm pretty sure this is safe for all cards. */
  43         /* Any idea what this is? */
  44         nv_wr32(dev, NV40_PFB_UNK_800, 0x1);
  45
  46         switch (dev_priv->chipset) {
  47         case 0x40:
  48         case 0x45:
  49                 tmp = nv_rd32(dev, NV10_PFB_CLOSE_PAGE2);
  50                 nv_wr32(dev, NV10_PFB_CLOSE_PAGE2, tmp & ~(1 << 15));
  51                 pfb->num_tiles = NV10_PFB_TILE__SIZE;
  52                 break;
  53         case 0x46: /* G72 */
  54         case 0x47: /* G70 */
  55         case 0x49: /* G71 */
  56         case 0x4b: /* G73 */
  57         case 0x4c: /* C51 (G7X version) */
  58                 pfb->num_tiles = NV40_PFB_TILE__SIZE_1;
  59                 break;
  60         default:
  61                 pfb->num_tiles = NV40_PFB_TILE__SIZE_0;
  62                 break;
  63         }
  64
  65         /* Turn all the tiling regions off. */
  66         for (i = 0; i < pfb->num_tiles; i++)
  67                 pfb->set_region_tiling(dev, i, 0, 0, 0);
  68
  69         return 0;
  70 }
  71
  72 void
  73 nv40_fb_takedown(struct drm_device *dev)
  74 {
  75 }