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Linux 2.6.33-rc6
[cris-mirror.git] / drivers / gpu / drm / radeon / rs690.c
blobcd31da913771d898c3d68946f0f8f3399becf382
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "atom.h"
31 #include "rs690d.h"
32
33 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
34 {
35 unsigned i;
36 uint32_t tmp;
37
38 for (i = 0; i < rdev->usec_timeout; i++) {
39 /* read MC_STATUS */
40 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
41 if (G_000090_MC_SYSTEM_IDLE(tmp))
42 return 0;
43 udelay(1);
44 }
45 return -1;
46 }
47
48 static void rs690_gpu_init(struct radeon_device *rdev)
49 {
50 /* FIXME: HDP same place on rs690 ? */
51 r100_hdp_reset(rdev);
52 /* FIXME: is this correct ? */
53 r420_pipes_init(rdev);
54 if (rs690_mc_wait_for_idle(rdev)) {
55 printk(KERN_WARNING "Failed to wait MC idle while "
56 "programming pipes. Bad things might happen.\n");
57 }
58 }
59
60 void rs690_pm_info(struct radeon_device *rdev)
61 {
62 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
63 struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
64 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
65 void *ptr;
66 uint16_t data_offset;
67 uint8_t frev, crev;
68 fixed20_12 tmp;
69
70 atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
71 &frev, &crev, &data_offset);
72 ptr = rdev->mode_info.atom_context->bios + data_offset;
73 info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
74 info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
75 /* Get various system informations from bios */
76 switch (crev) {
77 case 1:
78 tmp.full = rfixed_const(100);
79 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
80 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
81 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
82 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
83 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
84 break;
85 case 2:
86 tmp.full = rfixed_const(100);
87 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
88 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
89 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
90 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
91 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
92 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
93 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
94 break;
95 default:
96 tmp.full = rfixed_const(100);
97 /* We assume the slower possible clock ie worst case */
98 /* DDR 333Mhz */
99 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
100 /* FIXME: system clock ? */
101 rdev->pm.igp_system_mclk.full = rfixed_const(100);
102 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
103 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
104 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
105 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
106 break;
107 }
108 /* Compute various bandwidth */
109 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
110 tmp.full = rfixed_const(4);
111 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
112 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
113 * = ht_clk * ht_width / 5
114 */
115 tmp.full = rfixed_const(5);
116 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
117 rdev->pm.igp_ht_link_width);
118 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
119 if (tmp.full < rdev->pm.max_bandwidth.full) {
120 /* HT link is a limiting factor */
121 rdev->pm.max_bandwidth.full = tmp.full;
122 }
123 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
124 * = (sideport_clk * 14) / 10
125 */
126 tmp.full = rfixed_const(14);
127 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
128 tmp.full = rfixed_const(10);
129 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
130 }
131
132 void rs690_vram_info(struct radeon_device *rdev)
133 {
134 fixed20_12 a;
135
136 rs400_gart_adjust_size(rdev);
137
138 rdev->mc.vram_is_ddr = true;
139 rdev->mc.vram_width = 128;
140
141 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
142 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
143
144 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
145 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
146
147 if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
148 rdev->mc.mc_vram_size = rdev->mc.aper_size;
149
150 if (rdev->mc.real_vram_size > rdev->mc.aper_size)
151 rdev->mc.real_vram_size = rdev->mc.aper_size;
152
153 rs690_pm_info(rdev);
154 /* FIXME: we should enforce default clock in case GPU is not in
155 * default setup
156 */
157 a.full = rfixed_const(100);
158 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
159 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
160 a.full = rfixed_const(16);
161 /* core_bandwidth = sclk(Mhz) * 16 */
162 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
163 }
164
165 static int rs690_mc_init(struct radeon_device *rdev)
166 {
167 int r;
168 u32 tmp;
169
170 /* Setup GPU memory space */
171 tmp = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
172 rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
173 rdev->mc.gtt_location = 0xFFFFFFFFUL;
174 r = radeon_mc_setup(rdev);
175 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
176 if (r)
177 return r;
178 return 0;
179 }
180
181 void rs690_line_buffer_adjust(struct radeon_device *rdev,
182 struct drm_display_mode *mode1,
183 struct drm_display_mode *mode2)
184 {
185 u32 tmp;
186
187 /*
188 * Line Buffer Setup
189 * There is a single line buffer shared by both display controllers.
190 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
191 * the display controllers. The paritioning can either be done
192 * manually or via one of four preset allocations specified in bits 1:0:
193 * 0 - line buffer is divided in half and shared between crtc
194 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
195 * 2 - D1 gets the whole buffer
196 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
197 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
198 * allocation mode. In manual allocation mode, D1 always starts at 0,
199 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
200 */
201 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
202 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
203 /* auto */
204 if (mode1 && mode2) {
205 if (mode1->hdisplay > mode2->hdisplay) {
206 if (mode1->hdisplay > 2560)
207 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
208 else
209 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
210 } else if (mode2->hdisplay > mode1->hdisplay) {
211 if (mode2->hdisplay > 2560)
212 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
213 else
214 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
215 } else
216 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
217 } else if (mode1) {
218 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
219 } else if (mode2) {
220 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
221 }
222 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
223 }
224
225 struct rs690_watermark {
226 u32 lb_request_fifo_depth;
227 fixed20_12 num_line_pair;
228 fixed20_12 estimated_width;
229 fixed20_12 worst_case_latency;
230 fixed20_12 consumption_rate;
231 fixed20_12 active_time;
232 fixed20_12 dbpp;
233 fixed20_12 priority_mark_max;
234 fixed20_12 priority_mark;
235 fixed20_12 sclk;
236 };
237
238 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
239 struct radeon_crtc *crtc,
240 struct rs690_watermark *wm)
241 {
242 struct drm_display_mode *mode = &crtc->base.mode;
243 fixed20_12 a, b, c;
244 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
245 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
246 /* FIXME: detect IGP with sideport memory, i don't think there is any
247 * such product available
248 */
249 bool sideport = false;
250
251 if (!crtc->base.enabled) {
252 /* FIXME: wouldn't it better to set priority mark to maximum */
253 wm->lb_request_fifo_depth = 4;
254 return;
255 }
256
257 if (crtc->vsc.full > rfixed_const(2))
258 wm->num_line_pair.full = rfixed_const(2);
259 else
260 wm->num_line_pair.full = rfixed_const(1);
261
262 b.full = rfixed_const(mode->crtc_hdisplay);
263 c.full = rfixed_const(256);
264 a.full = rfixed_div(b, c);
265 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
266 request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
267 if (a.full < rfixed_const(4)) {
268 wm->lb_request_fifo_depth = 4;
269 } else {
270 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
271 }
272
273 /* Determine consumption rate
274 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
275 * vtaps = number of vertical taps,
276 * vsc = vertical scaling ratio, defined as source/destination
277 * hsc = horizontal scaling ration, defined as source/destination
278 */
279 a.full = rfixed_const(mode->clock);
280 b.full = rfixed_const(1000);
281 a.full = rfixed_div(a, b);
282 pclk.full = rfixed_div(b, a);
283 if (crtc->rmx_type != RMX_OFF) {
284 b.full = rfixed_const(2);
285 if (crtc->vsc.full > b.full)
286 b.full = crtc->vsc.full;
287 b.full = rfixed_mul(b, crtc->hsc);
288 c.full = rfixed_const(2);
289 b.full = rfixed_div(b, c);
290 consumption_time.full = rfixed_div(pclk, b);
291 } else {
292 consumption_time.full = pclk.full;
293 }
294 a.full = rfixed_const(1);
295 wm->consumption_rate.full = rfixed_div(a, consumption_time);
296
297
298 /* Determine line time
299 * LineTime = total time for one line of displayhtotal
300 * LineTime = total number of horizontal pixels
301 * pclk = pixel clock period(ns)
302 */
303 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
304 line_time.full = rfixed_mul(a, pclk);
305
306 /* Determine active time
307 * ActiveTime = time of active region of display within one line,
308 * hactive = total number of horizontal active pixels
309 * htotal = total number of horizontal pixels
310 */
311 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
312 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
313 wm->active_time.full = rfixed_mul(line_time, b);
314 wm->active_time.full = rfixed_div(wm->active_time, a);
315
316 /* Maximun bandwidth is the minimun bandwidth of all component */
317 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
318 if (sideport) {
319 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
320 rdev->pm.sideport_bandwidth.full)
321 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
322 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
323 read_delay_latency.full = rfixed_div(read_delay_latency,
324 rdev->pm.igp_sideport_mclk);
325 } else {
326 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
327 rdev->pm.k8_bandwidth.full)
328 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
329 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
330 rdev->pm.ht_bandwidth.full)
331 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
332 read_delay_latency.full = rfixed_const(5000);
333 }
334
335 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
336 a.full = rfixed_const(16);
337 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
338 a.full = rfixed_const(1000);
339 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
340 /* Determine chunk time
341 * ChunkTime = the time it takes the DCP to send one chunk of data
342 * to the LB which consists of pipeline delay and inter chunk gap
343 * sclk = system clock(ns)
344 */
345 a.full = rfixed_const(256 * 13);
346 chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
347 a.full = rfixed_const(10);
348 chunk_time.full = rfixed_div(chunk_time, a);
349
350 /* Determine the worst case latency
351 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
352 * WorstCaseLatency = worst case time from urgent to when the MC starts
353 * to return data
354 * READ_DELAY_IDLE_MAX = constant of 1us
355 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
356 * which consists of pipeline delay and inter chunk gap
357 */
358 if (rfixed_trunc(wm->num_line_pair) > 1) {
359 a.full = rfixed_const(3);
360 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
361 wm->worst_case_latency.full += read_delay_latency.full;
362 } else {
363 a.full = rfixed_const(2);
364 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
365 wm->worst_case_latency.full += read_delay_latency.full;
366 }
367
368 /* Determine the tolerable latency
369 * TolerableLatency = Any given request has only 1 line time
370 * for the data to be returned
371 * LBRequestFifoDepth = Number of chunk requests the LB can
372 * put into the request FIFO for a display
373 * LineTime = total time for one line of display
374 * ChunkTime = the time it takes the DCP to send one chunk
375 * of data to the LB which consists of
376 * pipeline delay and inter chunk gap
377 */
378 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
379 tolerable_latency.full = line_time.full;
380 } else {
381 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
382 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
383 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
384 tolerable_latency.full = line_time.full - tolerable_latency.full;
385 }
386 /* We assume worst case 32bits (4 bytes) */
387 wm->dbpp.full = rfixed_const(4 * 8);
388
389 /* Determine the maximum priority mark
390 * width = viewport width in pixels
391 */
392 a.full = rfixed_const(16);
393 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
394 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
395 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
396
397 /* Determine estimated width */
398 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
399 estimated_width.full = rfixed_div(estimated_width, consumption_time);
400 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
401 wm->priority_mark.full = rfixed_const(10);
402 } else {
403 a.full = rfixed_const(16);
404 wm->priority_mark.full = rfixed_div(estimated_width, a);
405 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
406 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
407 }
408 }
409
410 void rs690_bandwidth_update(struct radeon_device *rdev)
411 {
412 struct drm_display_mode *mode0 = NULL;
413 struct drm_display_mode *mode1 = NULL;
414 struct rs690_watermark wm0;
415 struct rs690_watermark wm1;
416 u32 tmp;
417 fixed20_12 priority_mark02, priority_mark12, fill_rate;
418 fixed20_12 a, b;
419
420 if (rdev->mode_info.crtcs[0]->base.enabled)
421 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
422 if (rdev->mode_info.crtcs[1]->base.enabled)
423 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
424 /*
425 * Set display0/1 priority up in the memory controller for
426 * modes if the user specifies HIGH for displaypriority
427 * option.
428 */
429 if (rdev->disp_priority == 2) {
430 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
431 tmp &= C_000104_MC_DISP0R_INIT_LAT;
432 tmp &= C_000104_MC_DISP1R_INIT_LAT;
433 if (mode0)
434 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
435 if (mode1)
436 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
437 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
438 }
439 rs690_line_buffer_adjust(rdev, mode0, mode1);
440
441 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
442 WREG32(R_006C9C_DCP_CONTROL, 0);
443 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
444 WREG32(R_006C9C_DCP_CONTROL, 2);
445
446 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
447 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
448
449 tmp = (wm0.lb_request_fifo_depth - 1);
450 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
451 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
452
453 if (mode0 && mode1) {
454 if (rfixed_trunc(wm0.dbpp) > 64)
455 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
456 else
457 a.full = wm0.num_line_pair.full;
458 if (rfixed_trunc(wm1.dbpp) > 64)
459 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
460 else
461 b.full = wm1.num_line_pair.full;
462 a.full += b.full;
463 fill_rate.full = rfixed_div(wm0.sclk, a);
464 if (wm0.consumption_rate.full > fill_rate.full) {
465 b.full = wm0.consumption_rate.full - fill_rate.full;
466 b.full = rfixed_mul(b, wm0.active_time);
467 a.full = rfixed_mul(wm0.worst_case_latency,
468 wm0.consumption_rate);
469 a.full = a.full + b.full;
470 b.full = rfixed_const(16 * 1000);
471 priority_mark02.full = rfixed_div(a, b);
472 } else {
473 a.full = rfixed_mul(wm0.worst_case_latency,
474 wm0.consumption_rate);
475 b.full = rfixed_const(16 * 1000);
476 priority_mark02.full = rfixed_div(a, b);
477 }
478 if (wm1.consumption_rate.full > fill_rate.full) {
479 b.full = wm1.consumption_rate.full - fill_rate.full;
480 b.full = rfixed_mul(b, wm1.active_time);
481 a.full = rfixed_mul(wm1.worst_case_latency,
482 wm1.consumption_rate);
483 a.full = a.full + b.full;
484 b.full = rfixed_const(16 * 1000);
485 priority_mark12.full = rfixed_div(a, b);
486 } else {
487 a.full = rfixed_mul(wm1.worst_case_latency,
488 wm1.consumption_rate);
489 b.full = rfixed_const(16 * 1000);
490 priority_mark12.full = rfixed_div(a, b);
491 }
492 if (wm0.priority_mark.full > priority_mark02.full)
493 priority_mark02.full = wm0.priority_mark.full;
494 if (rfixed_trunc(priority_mark02) < 0)
495 priority_mark02.full = 0;
496 if (wm0.priority_mark_max.full > priority_mark02.full)
497 priority_mark02.full = wm0.priority_mark_max.full;
498 if (wm1.priority_mark.full > priority_mark12.full)
499 priority_mark12.full = wm1.priority_mark.full;
500 if (rfixed_trunc(priority_mark12) < 0)
501 priority_mark12.full = 0;
502 if (wm1.priority_mark_max.full > priority_mark12.full)
503 priority_mark12.full = wm1.priority_mark_max.full;
504 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
505 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
506 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
507 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
508 } else if (mode0) {
509 if (rfixed_trunc(wm0.dbpp) > 64)
510 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
511 else
512 a.full = wm0.num_line_pair.full;
513 fill_rate.full = rfixed_div(wm0.sclk, a);
514 if (wm0.consumption_rate.full > fill_rate.full) {
515 b.full = wm0.consumption_rate.full - fill_rate.full;
516 b.full = rfixed_mul(b, wm0.active_time);
517 a.full = rfixed_mul(wm0.worst_case_latency,
518 wm0.consumption_rate);
519 a.full = a.full + b.full;
520 b.full = rfixed_const(16 * 1000);
521 priority_mark02.full = rfixed_div(a, b);
522 } else {
523 a.full = rfixed_mul(wm0.worst_case_latency,
524 wm0.consumption_rate);
525 b.full = rfixed_const(16 * 1000);
526 priority_mark02.full = rfixed_div(a, b);
527 }
528 if (wm0.priority_mark.full > priority_mark02.full)
529 priority_mark02.full = wm0.priority_mark.full;
530 if (rfixed_trunc(priority_mark02) < 0)
531 priority_mark02.full = 0;
532 if (wm0.priority_mark_max.full > priority_mark02.full)
533 priority_mark02.full = wm0.priority_mark_max.full;
534 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
535 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
536 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
537 S_006D48_D2MODE_PRIORITY_A_OFF(1));
538 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
539 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
540 } else {
541 if (rfixed_trunc(wm1.dbpp) > 64)
542 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
543 else
544 a.full = wm1.num_line_pair.full;
545 fill_rate.full = rfixed_div(wm1.sclk, a);
546 if (wm1.consumption_rate.full > fill_rate.full) {
547 b.full = wm1.consumption_rate.full - fill_rate.full;
548 b.full = rfixed_mul(b, wm1.active_time);
549 a.full = rfixed_mul(wm1.worst_case_latency,
550 wm1.consumption_rate);
551 a.full = a.full + b.full;
552 b.full = rfixed_const(16 * 1000);
553 priority_mark12.full = rfixed_div(a, b);
554 } else {
555 a.full = rfixed_mul(wm1.worst_case_latency,
556 wm1.consumption_rate);
557 b.full = rfixed_const(16 * 1000);
558 priority_mark12.full = rfixed_div(a, b);
559 }
560 if (wm1.priority_mark.full > priority_mark12.full)
561 priority_mark12.full = wm1.priority_mark.full;
562 if (rfixed_trunc(priority_mark12) < 0)
563 priority_mark12.full = 0;
564 if (wm1.priority_mark_max.full > priority_mark12.full)
565 priority_mark12.full = wm1.priority_mark_max.full;
566 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
567 S_006548_D1MODE_PRIORITY_A_OFF(1));
568 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
569 S_00654C_D1MODE_PRIORITY_B_OFF(1));
570 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
571 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
572 }
573 }
574
575 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
576 {
577 uint32_t r;
578
579 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
580 r = RREG32(R_00007C_MC_DATA);
581 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
582 return r;
583 }
584
585 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
586 {
587 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
588 S_000078_MC_IND_WR_EN(1));
589 WREG32(R_00007C_MC_DATA, v);
590 WREG32(R_000078_MC_INDEX, 0x7F);
591 }
592
593 void rs690_mc_program(struct radeon_device *rdev)
594 {
595 struct rv515_mc_save save;
596
597 /* Stops all mc clients */
598 rv515_mc_stop(rdev, &save);
599
600 /* Wait for mc idle */
601 if (rs690_mc_wait_for_idle(rdev))
602 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
603 /* Program MC, should be a 32bits limited address space */
604 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
605 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
606 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
607 WREG32(R_000134_HDP_FB_LOCATION,
608 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
609
610 rv515_mc_resume(rdev, &save);
611 }
612
613 static int rs690_startup(struct radeon_device *rdev)
614 {
615 int r;
616
617 rs690_mc_program(rdev);
618 /* Resume clock */
619 rv515_clock_startup(rdev);
620 /* Initialize GPU configuration (# pipes, ...) */
621 rs690_gpu_init(rdev);
622 /* Initialize GART (initialize after TTM so we can allocate
623 * memory through TTM but finalize after TTM) */
624 r = rs400_gart_enable(rdev);
625 if (r)
626 return r;
627 /* Enable IRQ */
628 rs600_irq_set(rdev);
629 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
630 /* 1M ring buffer */
631 r = r100_cp_init(rdev, 1024 * 1024);
632 if (r) {
633 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
634 return r;
635 }
636 r = r100_wb_init(rdev);
637 if (r)
638 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
639 r = r100_ib_init(rdev);
640 if (r) {
641 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
642 return r;
643 }
644 return 0;
645 }
646
647 int rs690_resume(struct radeon_device *rdev)
648 {
649 /* Make sur GART are not working */
650 rs400_gart_disable(rdev);
651 /* Resume clock before doing reset */
652 rv515_clock_startup(rdev);
653 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
654 if (radeon_gpu_reset(rdev)) {
655 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
656 RREG32(R_000E40_RBBM_STATUS),
657 RREG32(R_0007C0_CP_STAT));
658 }
659 /* post */
660 atom_asic_init(rdev->mode_info.atom_context);
661 /* Resume clock after posting */
662 rv515_clock_startup(rdev);
663 /* Initialize surface registers */
664 radeon_surface_init(rdev);
665 return rs690_startup(rdev);
666 }
667
668 int rs690_suspend(struct radeon_device *rdev)
669 {
670 r100_cp_disable(rdev);
671 r100_wb_disable(rdev);
672 rs600_irq_disable(rdev);
673 rs400_gart_disable(rdev);
674 return 0;
675 }
676
677 void rs690_fini(struct radeon_device *rdev)
678 {
679 rs690_suspend(rdev);
680 r100_cp_fini(rdev);
681 r100_wb_fini(rdev);
682 r100_ib_fini(rdev);
683 radeon_gem_fini(rdev);
684 rs400_gart_fini(rdev);
685 radeon_irq_kms_fini(rdev);
686 radeon_fence_driver_fini(rdev);
687 radeon_bo_fini(rdev);
688 radeon_atombios_fini(rdev);
689 kfree(rdev->bios);
690 rdev->bios = NULL;
691 }
692
693 int rs690_init(struct radeon_device *rdev)
694 {
695 int r;
696
697 /* Disable VGA */
698 rv515_vga_render_disable(rdev);
699 /* Initialize scratch registers */
700 radeon_scratch_init(rdev);
701 /* Initialize surface registers */
702 radeon_surface_init(rdev);
703 /* TODO: disable VGA need to use VGA request */
704 /* BIOS*/
705 if (!radeon_get_bios(rdev)) {
706 if (ASIC_IS_AVIVO(rdev))
707 return -EINVAL;
708 }
709 if (rdev->is_atom_bios) {
710 r = radeon_atombios_init(rdev);
711 if (r)
712 return r;
713 } else {
714 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
715 return -EINVAL;
716 }
717 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
718 if (radeon_gpu_reset(rdev)) {
719 dev_warn(rdev->dev,
720 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
721 RREG32(R_000E40_RBBM_STATUS),
722 RREG32(R_0007C0_CP_STAT));
723 }
724 /* check if cards are posted or not */
725 if (radeon_boot_test_post_card(rdev) == false)
726 return -EINVAL;
727
728 /* Initialize clocks */
729 radeon_get_clock_info(rdev->ddev);
730 /* Initialize power management */
731 radeon_pm_init(rdev);
732 /* Get vram informations */
733 rs690_vram_info(rdev);
734 /* Initialize memory controller (also test AGP) */
735 r = rs690_mc_init(rdev);
736 if (r)
737 return r;
738 rv515_debugfs(rdev);
739 /* Fence driver */
740 r = radeon_fence_driver_init(rdev);
741 if (r)
742 return r;
743 r = radeon_irq_kms_init(rdev);
744 if (r)
745 return r;
746 /* Memory manager */
747 r = radeon_bo_init(rdev);
748 if (r)
749 return r;
750 r = rs400_gart_init(rdev);
751 if (r)
752 return r;
753 rs600_set_safe_registers(rdev);
754 rdev->accel_working = true;
755 r = rs690_startup(rdev);
756 if (r) {
757 /* Somethings want wront with the accel init stop accel */
758 dev_err(rdev->dev, "Disabling GPU acceleration\n");
759 rs690_suspend(rdev);
760 r100_cp_fini(rdev);
761 r100_wb_fini(rdev);
762 r100_ib_fini(rdev);
763 rs400_gart_fini(rdev);
764 radeon_irq_kms_fini(rdev);
765 rdev->accel_working = false;
766 }
767 return 0;
768 }
CRIS linux kernel tree