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Linux 2.6.33-rc6
[cris-mirror.git] / drivers / mtd / nand / nand_base.c
blob8f2958fe2148a1d14b24ef33fc1b509bff809a7a
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/compatmac.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <asm/io.h>
50
51 #ifdef CONFIG_MTD_PARTITIONS
52 #include <linux/mtd/partitions.h>
53 #endif
54
55 /* Define default oob placement schemes for large and small page devices */
56 static struct nand_ecclayout nand_oob_8 = {
57 .eccbytes = 3,
58 .eccpos = {0, 1, 2},
59 .oobfree = {
60 {.offset = 3,
61 .length = 2},
62 {.offset = 6,
63 .length = 2}}
64 };
65
66 static struct nand_ecclayout nand_oob_16 = {
67 .eccbytes = 6,
68 .eccpos = {0, 1, 2, 3, 6, 7},
69 .oobfree = {
70 {.offset = 8,
71 . length = 8}}
72 };
73
74 static struct nand_ecclayout nand_oob_64 = {
75 .eccbytes = 24,
76 .eccpos = {
77 40, 41, 42, 43, 44, 45, 46, 47,
78 48, 49, 50, 51, 52, 53, 54, 55,
79 56, 57, 58, 59, 60, 61, 62, 63},
80 .oobfree = {
81 {.offset = 2,
82 .length = 38}}
83 };
84
85 static struct nand_ecclayout nand_oob_128 = {
86 .eccbytes = 48,
87 .eccpos = {
88 80, 81, 82, 83, 84, 85, 86, 87,
89 88, 89, 90, 91, 92, 93, 94, 95,
90 96, 97, 98, 99, 100, 101, 102, 103,
91 104, 105, 106, 107, 108, 109, 110, 111,
92 112, 113, 114, 115, 116, 117, 118, 119,
93 120, 121, 122, 123, 124, 125, 126, 127},
94 .oobfree = {
95 {.offset = 2,
96 .length = 78}}
97 };
98
99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
100 int new_state);
101
102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
103 struct mtd_oob_ops *ops);
104
105 /*
106 * For devices which display every fart in the system on a separate LED. Is
107 * compiled away when LED support is disabled.
108 */
109 DEFINE_LED_TRIGGER(nand_led_trigger);
110
111 /**
112 * nand_release_device - [GENERIC] release chip
113 * @mtd: MTD device structure
114 *
115 * Deselect, release chip lock and wake up anyone waiting on the device
116 */
117 static void nand_release_device(struct mtd_info *mtd)
118 {
119 struct nand_chip *chip = mtd->priv;
120
121 /* De-select the NAND device */
122 chip->select_chip(mtd, -1);
123
124 /* Release the controller and the chip */
125 spin_lock(&chip->controller->lock);
126 chip->controller->active = NULL;
127 chip->state = FL_READY;
128 wake_up(&chip->controller->wq);
129 spin_unlock(&chip->controller->lock);
130 }
131
132 /**
133 * nand_read_byte - [DEFAULT] read one byte from the chip
134 * @mtd: MTD device structure
135 *
136 * Default read function for 8bit buswith
137 */
138 static uint8_t nand_read_byte(struct mtd_info *mtd)
139 {
140 struct nand_chip *chip = mtd->priv;
141 return readb(chip->IO_ADDR_R);
142 }
143
144 /**
145 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
146 * @mtd: MTD device structure
147 *
148 * Default read function for 16bit buswith with
149 * endianess conversion
150 */
151 static uint8_t nand_read_byte16(struct mtd_info *mtd)
152 {
153 struct nand_chip *chip = mtd->priv;
154 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
155 }
156
157 /**
158 * nand_read_word - [DEFAULT] read one word from the chip
159 * @mtd: MTD device structure
160 *
161 * Default read function for 16bit buswith without
162 * endianess conversion
163 */
164 static u16 nand_read_word(struct mtd_info *mtd)
165 {
166 struct nand_chip *chip = mtd->priv;
167 return readw(chip->IO_ADDR_R);
168 }
169
170 /**
171 * nand_select_chip - [DEFAULT] control CE line
172 * @mtd: MTD device structure
173 * @chipnr: chipnumber to select, -1 for deselect
174 *
175 * Default select function for 1 chip devices.
176 */
177 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
178 {
179 struct nand_chip *chip = mtd->priv;
180
181 switch (chipnr) {
182 case -1:
183 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
184 break;
185 case 0:
186 break;
187
188 default:
189 BUG();
190 }
191 }
192
193 /**
194 * nand_write_buf - [DEFAULT] write buffer to chip
195 * @mtd: MTD device structure
196 * @buf: data buffer
197 * @len: number of bytes to write
198 *
199 * Default write function for 8bit buswith
200 */
201 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
202 {
203 int i;
204 struct nand_chip *chip = mtd->priv;
205
206 for (i = 0; i < len; i++)
207 writeb(buf[i], chip->IO_ADDR_W);
208 }
209
210 /**
211 * nand_read_buf - [DEFAULT] read chip data into buffer
212 * @mtd: MTD device structure
213 * @buf: buffer to store date
214 * @len: number of bytes to read
215 *
216 * Default read function for 8bit buswith
217 */
218 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
219 {
220 int i;
221 struct nand_chip *chip = mtd->priv;
222
223 for (i = 0; i < len; i++)
224 buf[i] = readb(chip->IO_ADDR_R);
225 }
226
227 /**
228 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
229 * @mtd: MTD device structure
230 * @buf: buffer containing the data to compare
231 * @len: number of bytes to compare
232 *
233 * Default verify function for 8bit buswith
234 */
235 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
236 {
237 int i;
238 struct nand_chip *chip = mtd->priv;
239
240 for (i = 0; i < len; i++)
241 if (buf[i] != readb(chip->IO_ADDR_R))
242 return -EFAULT;
243 return 0;
244 }
245
246 /**
247 * nand_write_buf16 - [DEFAULT] write buffer to chip
248 * @mtd: MTD device structure
249 * @buf: data buffer
250 * @len: number of bytes to write
251 *
252 * Default write function for 16bit buswith
253 */
254 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
255 {
256 int i;
257 struct nand_chip *chip = mtd->priv;
258 u16 *p = (u16 *) buf;
259 len >>= 1;
260
261 for (i = 0; i < len; i++)
262 writew(p[i], chip->IO_ADDR_W);
263
264 }
265
266 /**
267 * nand_read_buf16 - [DEFAULT] read chip data into buffer
268 * @mtd: MTD device structure
269 * @buf: buffer to store date
270 * @len: number of bytes to read
271 *
272 * Default read function for 16bit buswith
273 */
274 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
275 {
276 int i;
277 struct nand_chip *chip = mtd->priv;
278 u16 *p = (u16 *) buf;
279 len >>= 1;
280
281 for (i = 0; i < len; i++)
282 p[i] = readw(chip->IO_ADDR_R);
283 }
284
285 /**
286 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
287 * @mtd: MTD device structure
288 * @buf: buffer containing the data to compare
289 * @len: number of bytes to compare
290 *
291 * Default verify function for 16bit buswith
292 */
293 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
294 {
295 int i;
296 struct nand_chip *chip = mtd->priv;
297 u16 *p = (u16 *) buf;
298 len >>= 1;
299
300 for (i = 0; i < len; i++)
301 if (p[i] != readw(chip->IO_ADDR_R))
302 return -EFAULT;
303
304 return 0;
305 }
306
307 /**
308 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
309 * @mtd: MTD device structure
310 * @ofs: offset from device start
311 * @getchip: 0, if the chip is already selected
312 *
313 * Check, if the block is bad.
314 */
315 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
316 {
317 int page, chipnr, res = 0;
318 struct nand_chip *chip = mtd->priv;
319 u16 bad;
320
321 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
322
323 if (getchip) {
324 chipnr = (int)(ofs >> chip->chip_shift);
325
326 nand_get_device(chip, mtd, FL_READING);
327
328 /* Select the NAND device */
329 chip->select_chip(mtd, chipnr);
330 }
331
332 if (chip->options & NAND_BUSWIDTH_16) {
333 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
334 page);
335 bad = cpu_to_le16(chip->read_word(mtd));
336 if (chip->badblockpos & 0x1)
337 bad >>= 8;
338 if ((bad & 0xFF) != 0xff)
339 res = 1;
340 } else {
341 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
342 if (chip->read_byte(mtd) != 0xff)
343 res = 1;
344 }
345
346 if (getchip)
347 nand_release_device(mtd);
348
349 return res;
350 }
351
352 /**
353 * nand_default_block_markbad - [DEFAULT] mark a block bad
354 * @mtd: MTD device structure
355 * @ofs: offset from device start
356 *
357 * This is the default implementation, which can be overridden by
358 * a hardware specific driver.
359 */
360 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
361 {
362 struct nand_chip *chip = mtd->priv;
363 uint8_t buf[2] = { 0, 0 };
364 int block, ret;
365
366 /* Get block number */
367 block = (int)(ofs >> chip->bbt_erase_shift);
368 if (chip->bbt)
369 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
370
371 /* Do we have a flash based bad block table ? */
372 if (chip->options & NAND_USE_FLASH_BBT)
373 ret = nand_update_bbt(mtd, ofs);
374 else {
375 /* We write two bytes, so we dont have to mess with 16 bit
376 * access
377 */
378 nand_get_device(chip, mtd, FL_WRITING);
379 ofs += mtd->oobsize;
380 chip->ops.len = chip->ops.ooblen = 2;
381 chip->ops.datbuf = NULL;
382 chip->ops.oobbuf = buf;
383 chip->ops.ooboffs = chip->badblockpos & ~0x01;
384
385 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
386 nand_release_device(mtd);
387 }
388 if (!ret)
389 mtd->ecc_stats.badblocks++;
390
391 return ret;
392 }
393
394 /**
395 * nand_check_wp - [GENERIC] check if the chip is write protected
396 * @mtd: MTD device structure
397 * Check, if the device is write protected
398 *
399 * The function expects, that the device is already selected
400 */
401 static int nand_check_wp(struct mtd_info *mtd)
402 {
403 struct nand_chip *chip = mtd->priv;
404 /* Check the WP bit */
405 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
406 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
407 }
408
409 /**
410 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
411 * @mtd: MTD device structure
412 * @ofs: offset from device start
413 * @getchip: 0, if the chip is already selected
414 * @allowbbt: 1, if its allowed to access the bbt area
415 *
416 * Check, if the block is bad. Either by reading the bad block table or
417 * calling of the scan function.
418 */
419 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
420 int allowbbt)
421 {
422 struct nand_chip *chip = mtd->priv;
423
424 if (!chip->bbt)
425 return chip->block_bad(mtd, ofs, getchip);
426
427 /* Return info from the table */
428 return nand_isbad_bbt(mtd, ofs, allowbbt);
429 }
430
431 /**
432 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
433 * @mtd: MTD device structure
434 * @timeo: Timeout
435 *
436 * Helper function for nand_wait_ready used when needing to wait in interrupt
437 * context.
438 */
439 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
440 {
441 struct nand_chip *chip = mtd->priv;
442 int i;
443
444 /* Wait for the device to get ready */
445 for (i = 0; i < timeo; i++) {
446 if (chip->dev_ready(mtd))
447 break;
448 touch_softlockup_watchdog();
449 mdelay(1);
450 }
451 }
452
453 /*
454 * Wait for the ready pin, after a command
455 * The timeout is catched later.
456 */
457 void nand_wait_ready(struct mtd_info *mtd)
458 {
459 struct nand_chip *chip = mtd->priv;
460 unsigned long timeo = jiffies + 2;
461
462 /* 400ms timeout */
463 if (in_interrupt() || oops_in_progress)
464 return panic_nand_wait_ready(mtd, 400);
465
466 led_trigger_event(nand_led_trigger, LED_FULL);
467 /* wait until command is processed or timeout occures */
468 do {
469 if (chip->dev_ready(mtd))
470 break;
471 touch_softlockup_watchdog();
472 } while (time_before(jiffies, timeo));
473 led_trigger_event(nand_led_trigger, LED_OFF);
474 }
475 EXPORT_SYMBOL_GPL(nand_wait_ready);
476
477 /**
478 * nand_command - [DEFAULT] Send command to NAND device
479 * @mtd: MTD device structure
480 * @command: the command to be sent
481 * @column: the column address for this command, -1 if none
482 * @page_addr: the page address for this command, -1 if none
483 *
484 * Send command to NAND device. This function is used for small page
485 * devices (256/512 Bytes per page)
486 */
487 static void nand_command(struct mtd_info *mtd, unsigned int command,
488 int column, int page_addr)
489 {
490 register struct nand_chip *chip = mtd->priv;
491 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
492
493 /*
494 * Write out the command to the device.
495 */
496 if (command == NAND_CMD_SEQIN) {
497 int readcmd;
498
499 if (column >= mtd->writesize) {
500 /* OOB area */
501 column -= mtd->writesize;
502 readcmd = NAND_CMD_READOOB;
503 } else if (column < 256) {
504 /* First 256 bytes --> READ0 */
505 readcmd = NAND_CMD_READ0;
506 } else {
507 column -= 256;
508 readcmd = NAND_CMD_READ1;
509 }
510 chip->cmd_ctrl(mtd, readcmd, ctrl);
511 ctrl &= ~NAND_CTRL_CHANGE;
512 }
513 chip->cmd_ctrl(mtd, command, ctrl);
514
515 /*
516 * Address cycle, when necessary
517 */
518 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
519 /* Serially input address */
520 if (column != -1) {
521 /* Adjust columns for 16 bit buswidth */
522 if (chip->options & NAND_BUSWIDTH_16)
523 column >>= 1;
524 chip->cmd_ctrl(mtd, column, ctrl);
525 ctrl &= ~NAND_CTRL_CHANGE;
526 }
527 if (page_addr != -1) {
528 chip->cmd_ctrl(mtd, page_addr, ctrl);
529 ctrl &= ~NAND_CTRL_CHANGE;
530 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
531 /* One more address cycle for devices > 32MiB */
532 if (chip->chipsize > (32 << 20))
533 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
534 }
535 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
536
537 /*
538 * program and erase have their own busy handlers
539 * status and sequential in needs no delay
540 */
541 switch (command) {
542
543 case NAND_CMD_PAGEPROG:
544 case NAND_CMD_ERASE1:
545 case NAND_CMD_ERASE2:
546 case NAND_CMD_SEQIN:
547 case NAND_CMD_STATUS:
548 return;
549
550 case NAND_CMD_RESET:
551 if (chip->dev_ready)
552 break;
553 udelay(chip->chip_delay);
554 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
555 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
556 chip->cmd_ctrl(mtd,
557 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
558 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
559 return;
560
561 /* This applies to read commands */
562 default:
563 /*
564 * If we don't have access to the busy pin, we apply the given
565 * command delay
566 */
567 if (!chip->dev_ready) {
568 udelay(chip->chip_delay);
569 return;
570 }
571 }
572 /* Apply this short delay always to ensure that we do wait tWB in
573 * any case on any machine. */
574 ndelay(100);
575
576 nand_wait_ready(mtd);
577 }
578
579 /**
580 * nand_command_lp - [DEFAULT] Send command to NAND large page device
581 * @mtd: MTD device structure
582 * @command: the command to be sent
583 * @column: the column address for this command, -1 if none
584 * @page_addr: the page address for this command, -1 if none
585 *
586 * Send command to NAND device. This is the version for the new large page
587 * devices We dont have the separate regions as we have in the small page
588 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
589 */
590 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
591 int column, int page_addr)
592 {
593 register struct nand_chip *chip = mtd->priv;
594
595 /* Emulate NAND_CMD_READOOB */
596 if (command == NAND_CMD_READOOB) {
597 column += mtd->writesize;
598 command = NAND_CMD_READ0;
599 }
600
601 /* Command latch cycle */
602 chip->cmd_ctrl(mtd, command & 0xff,
603 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
604
605 if (column != -1 || page_addr != -1) {
606 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
607
608 /* Serially input address */
609 if (column != -1) {
610 /* Adjust columns for 16 bit buswidth */
611 if (chip->options & NAND_BUSWIDTH_16)
612 column >>= 1;
613 chip->cmd_ctrl(mtd, column, ctrl);
614 ctrl &= ~NAND_CTRL_CHANGE;
615 chip->cmd_ctrl(mtd, column >> 8, ctrl);
616 }
617 if (page_addr != -1) {
618 chip->cmd_ctrl(mtd, page_addr, ctrl);
619 chip->cmd_ctrl(mtd, page_addr >> 8,
620 NAND_NCE | NAND_ALE);
621 /* One more address cycle for devices > 128MiB */
622 if (chip->chipsize > (128 << 20))
623 chip->cmd_ctrl(mtd, page_addr >> 16,
624 NAND_NCE | NAND_ALE);
625 }
626 }
627 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
628
629 /*
630 * program and erase have their own busy handlers
631 * status, sequential in, and deplete1 need no delay
632 */
633 switch (command) {
634
635 case NAND_CMD_CACHEDPROG:
636 case NAND_CMD_PAGEPROG:
637 case NAND_CMD_ERASE1:
638 case NAND_CMD_ERASE2:
639 case NAND_CMD_SEQIN:
640 case NAND_CMD_RNDIN:
641 case NAND_CMD_STATUS:
642 case NAND_CMD_DEPLETE1:
643 return;
644
645 /*
646 * read error status commands require only a short delay
647 */
648 case NAND_CMD_STATUS_ERROR:
649 case NAND_CMD_STATUS_ERROR0:
650 case NAND_CMD_STATUS_ERROR1:
651 case NAND_CMD_STATUS_ERROR2:
652 case NAND_CMD_STATUS_ERROR3:
653 udelay(chip->chip_delay);
654 return;
655
656 case NAND_CMD_RESET:
657 if (chip->dev_ready)
658 break;
659 udelay(chip->chip_delay);
660 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
661 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
662 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
663 NAND_NCE | NAND_CTRL_CHANGE);
664 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
665 return;
666
667 case NAND_CMD_RNDOUT:
668 /* No ready / busy check necessary */
669 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
670 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
671 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
672 NAND_NCE | NAND_CTRL_CHANGE);
673 return;
674
675 case NAND_CMD_READ0:
676 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
677 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
678 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
679 NAND_NCE | NAND_CTRL_CHANGE);
680
681 /* This applies to read commands */
682 default:
683 /*
684 * If we don't have access to the busy pin, we apply the given
685 * command delay
686 */
687 if (!chip->dev_ready) {
688 udelay(chip->chip_delay);
689 return;
690 }
691 }
692
693 /* Apply this short delay always to ensure that we do wait tWB in
694 * any case on any machine. */
695 ndelay(100);
696
697 nand_wait_ready(mtd);
698 }
699
700 /**
701 * panic_nand_get_device - [GENERIC] Get chip for selected access
702 * @chip: the nand chip descriptor
703 * @mtd: MTD device structure
704 * @new_state: the state which is requested
705 *
706 * Used when in panic, no locks are taken.
707 */
708 static void panic_nand_get_device(struct nand_chip *chip,
709 struct mtd_info *mtd, int new_state)
710 {
711 /* Hardware controller shared among independend devices */
712 chip->controller->active = chip;
713 chip->state = new_state;
714 }
715
716 /**
717 * nand_get_device - [GENERIC] Get chip for selected access
718 * @chip: the nand chip descriptor
719 * @mtd: MTD device structure
720 * @new_state: the state which is requested
721 *
722 * Get the device and lock it for exclusive access
723 */
724 static int
725 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
726 {
727 spinlock_t *lock = &chip->controller->lock;
728 wait_queue_head_t *wq = &chip->controller->wq;
729 DECLARE_WAITQUEUE(wait, current);
730 retry:
731 spin_lock(lock);
732
733 /* Hardware controller shared among independent devices */
734 if (!chip->controller->active)
735 chip->controller->active = chip;
736
737 if (chip->controller->active == chip && chip->state == FL_READY) {
738 chip->state = new_state;
739 spin_unlock(lock);
740 return 0;
741 }
742 if (new_state == FL_PM_SUSPENDED) {
743 if (chip->controller->active->state == FL_PM_SUSPENDED) {
744 chip->state = FL_PM_SUSPENDED;
745 spin_unlock(lock);
746 return 0;
747 } else {
748 spin_unlock(lock);
749 return -EAGAIN;
750 }
751 }
752 set_current_state(TASK_UNINTERRUPTIBLE);
753 add_wait_queue(wq, &wait);
754 spin_unlock(lock);
755 schedule();
756 remove_wait_queue(wq, &wait);
757 goto retry;
758 }
759
760 /**
761 * panic_nand_wait - [GENERIC] wait until the command is done
762 * @mtd: MTD device structure
763 * @chip: NAND chip structure
764 * @timeo: Timeout
765 *
766 * Wait for command done. This is a helper function for nand_wait used when
767 * we are in interrupt context. May happen when in panic and trying to write
768 * an oops trough mtdoops.
769 */
770 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
771 unsigned long timeo)
772 {
773 int i;
774 for (i = 0; i < timeo; i++) {
775 if (chip->dev_ready) {
776 if (chip->dev_ready(mtd))
777 break;
778 } else {
779 if (chip->read_byte(mtd) & NAND_STATUS_READY)
780 break;
781 }
782 mdelay(1);
783 }
784 }
785
786 /**
787 * nand_wait - [DEFAULT] wait until the command is done
788 * @mtd: MTD device structure
789 * @chip: NAND chip structure
790 *
791 * Wait for command done. This applies to erase and program only
792 * Erase can take up to 400ms and program up to 20ms according to
793 * general NAND and SmartMedia specs
794 */
795 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
796 {
797
798 unsigned long timeo = jiffies;
799 int status, state = chip->state;
800
801 if (state == FL_ERASING)
802 timeo += (HZ * 400) / 1000;
803 else
804 timeo += (HZ * 20) / 1000;
805
806 led_trigger_event(nand_led_trigger, LED_FULL);
807
808 /* Apply this short delay always to ensure that we do wait tWB in
809 * any case on any machine. */
810 ndelay(100);
811
812 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
813 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
814 else
815 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
816
817 if (in_interrupt() || oops_in_progress)
818 panic_nand_wait(mtd, chip, timeo);
819 else {
820 while (time_before(jiffies, timeo)) {
821 if (chip->dev_ready) {
822 if (chip->dev_ready(mtd))
823 break;
824 } else {
825 if (chip->read_byte(mtd) & NAND_STATUS_READY)
826 break;
827 }
828 cond_resched();
829 }
830 }
831 led_trigger_event(nand_led_trigger, LED_OFF);
832
833 status = (int)chip->read_byte(mtd);
834 return status;
835 }
836
837 /**
838 * nand_read_page_raw - [Intern] read raw page data without ecc
839 * @mtd: mtd info structure
840 * @chip: nand chip info structure
841 * @buf: buffer to store read data
842 * @page: page number to read
843 *
844 * Not for syndrome calculating ecc controllers, which use a special oob layout
845 */
846 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
847 uint8_t *buf, int page)
848 {
849 chip->read_buf(mtd, buf, mtd->writesize);
850 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
851 return 0;
852 }
853
854 /**
855 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
856 * @mtd: mtd info structure
857 * @chip: nand chip info structure
858 * @buf: buffer to store read data
859 * @page: page number to read
860 *
861 * We need a special oob layout and handling even when OOB isn't used.
862 */
863 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
864 uint8_t *buf, int page)
865 {
866 int eccsize = chip->ecc.size;
867 int eccbytes = chip->ecc.bytes;
868 uint8_t *oob = chip->oob_poi;
869 int steps, size;
870
871 for (steps = chip->ecc.steps; steps > 0; steps--) {
872 chip->read_buf(mtd, buf, eccsize);
873 buf += eccsize;
874
875 if (chip->ecc.prepad) {
876 chip->read_buf(mtd, oob, chip->ecc.prepad);
877 oob += chip->ecc.prepad;
878 }
879
880 chip->read_buf(mtd, oob, eccbytes);
881 oob += eccbytes;
882
883 if (chip->ecc.postpad) {
884 chip->read_buf(mtd, oob, chip->ecc.postpad);
885 oob += chip->ecc.postpad;
886 }
887 }
888
889 size = mtd->oobsize - (oob - chip->oob_poi);
890 if (size)
891 chip->read_buf(mtd, oob, size);
892
893 return 0;
894 }
895
896 /**
897 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
898 * @mtd: mtd info structure
899 * @chip: nand chip info structure
900 * @buf: buffer to store read data
901 * @page: page number to read
902 */
903 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
904 uint8_t *buf, int page)
905 {
906 int i, eccsize = chip->ecc.size;
907 int eccbytes = chip->ecc.bytes;
908 int eccsteps = chip->ecc.steps;
909 uint8_t *p = buf;
910 uint8_t *ecc_calc = chip->buffers->ecccalc;
911 uint8_t *ecc_code = chip->buffers->ecccode;
912 uint32_t *eccpos = chip->ecc.layout->eccpos;
913
914 chip->ecc.read_page_raw(mtd, chip, buf, page);
915
916 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
917 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
918
919 for (i = 0; i < chip->ecc.total; i++)
920 ecc_code[i] = chip->oob_poi[eccpos[i]];
921
922 eccsteps = chip->ecc.steps;
923 p = buf;
924
925 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
926 int stat;
927
928 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
929 if (stat < 0)
930 mtd->ecc_stats.failed++;
931 else
932 mtd->ecc_stats.corrected += stat;
933 }
934 return 0;
935 }
936
937 /**
938 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
939 * @mtd: mtd info structure
940 * @chip: nand chip info structure
941 * @data_offs: offset of requested data within the page
942 * @readlen: data length
943 * @bufpoi: buffer to store read data
944 */
945 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
946 {
947 int start_step, end_step, num_steps;
948 uint32_t *eccpos = chip->ecc.layout->eccpos;
949 uint8_t *p;
950 int data_col_addr, i, gaps = 0;
951 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
952 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
953
954 /* Column address wihin the page aligned to ECC size (256bytes). */
955 start_step = data_offs / chip->ecc.size;
956 end_step = (data_offs + readlen - 1) / chip->ecc.size;
957 num_steps = end_step - start_step + 1;
958
959 /* Data size aligned to ECC ecc.size*/
960 datafrag_len = num_steps * chip->ecc.size;
961 eccfrag_len = num_steps * chip->ecc.bytes;
962
963 data_col_addr = start_step * chip->ecc.size;
964 /* If we read not a page aligned data */
965 if (data_col_addr != 0)
966 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
967
968 p = bufpoi + data_col_addr;
969 chip->read_buf(mtd, p, datafrag_len);
970
971 /* Calculate ECC */
972 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
973 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
974
975 /* The performance is faster if to position offsets
976 according to ecc.pos. Let make sure here that
977 there are no gaps in ecc positions */
978 for (i = 0; i < eccfrag_len - 1; i++) {
979 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
980 eccpos[i + start_step * chip->ecc.bytes + 1]) {
981 gaps = 1;
982 break;
983 }
984 }
985 if (gaps) {
986 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
987 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
988 } else {
989 /* send the command to read the particular ecc bytes */
990 /* take care about buswidth alignment in read_buf */
991 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
992 aligned_len = eccfrag_len;
993 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
994 aligned_len++;
995 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
996 aligned_len++;
997
998 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
999 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1000 }
1001
1002 for (i = 0; i < eccfrag_len; i++)
1003 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1004
1005 p = bufpoi + data_col_addr;
1006 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1007 int stat;
1008
1009 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1010 if (stat == -1)
1011 mtd->ecc_stats.failed++;
1012 else
1013 mtd->ecc_stats.corrected += stat;
1014 }
1015 return 0;
1016 }
1017
1018 /**
1019 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1020 * @mtd: mtd info structure
1021 * @chip: nand chip info structure
1022 * @buf: buffer to store read data
1023 * @page: page number to read
1024 *
1025 * Not for syndrome calculating ecc controllers which need a special oob layout
1026 */
1027 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1028 uint8_t *buf, int page)
1029 {
1030 int i, eccsize = chip->ecc.size;
1031 int eccbytes = chip->ecc.bytes;
1032 int eccsteps = chip->ecc.steps;
1033 uint8_t *p = buf;
1034 uint8_t *ecc_calc = chip->buffers->ecccalc;
1035 uint8_t *ecc_code = chip->buffers->ecccode;
1036 uint32_t *eccpos = chip->ecc.layout->eccpos;
1037
1038 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1039 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1040 chip->read_buf(mtd, p, eccsize);
1041 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1042 }
1043 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1044
1045 for (i = 0; i < chip->ecc.total; i++)
1046 ecc_code[i] = chip->oob_poi[eccpos[i]];
1047
1048 eccsteps = chip->ecc.steps;
1049 p = buf;
1050
1051 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1052 int stat;
1053
1054 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1055 if (stat < 0)
1056 mtd->ecc_stats.failed++;
1057 else
1058 mtd->ecc_stats.corrected += stat;
1059 }
1060 return 0;
1061 }
1062
1063 /**
1064 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1065 * @mtd: mtd info structure
1066 * @chip: nand chip info structure
1067 * @buf: buffer to store read data
1068 * @page: page number to read
1069 *
1070 * Hardware ECC for large page chips, require OOB to be read first.
1071 * For this ECC mode, the write_page method is re-used from ECC_HW.
1072 * These methods read/write ECC from the OOB area, unlike the
1073 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1074 * "infix ECC" scheme and reads/writes ECC from the data area, by
1075 * overwriting the NAND manufacturer bad block markings.
1076 */
1077 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1078 struct nand_chip *chip, uint8_t *buf, int page)
1079 {
1080 int i, eccsize = chip->ecc.size;
1081 int eccbytes = chip->ecc.bytes;
1082 int eccsteps = chip->ecc.steps;
1083 uint8_t *p = buf;
1084 uint8_t *ecc_code = chip->buffers->ecccode;
1085 uint32_t *eccpos = chip->ecc.layout->eccpos;
1086 uint8_t *ecc_calc = chip->buffers->ecccalc;
1087
1088 /* Read the OOB area first */
1089 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1090 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1091 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1092
1093 for (i = 0; i < chip->ecc.total; i++)
1094 ecc_code[i] = chip->oob_poi[eccpos[i]];
1095
1096 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1097 int stat;
1098
1099 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1100 chip->read_buf(mtd, p, eccsize);
1101 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1102
1103 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1104 if (stat < 0)
1105 mtd->ecc_stats.failed++;
1106 else
1107 mtd->ecc_stats.corrected += stat;
1108 }
1109 return 0;
1110 }
1111
1112 /**
1113 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1114 * @mtd: mtd info structure
1115 * @chip: nand chip info structure
1116 * @buf: buffer to store read data
1117 * @page: page number to read
1118 *
1119 * The hw generator calculates the error syndrome automatically. Therefor
1120 * we need a special oob layout and handling.
1121 */
1122 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1123 uint8_t *buf, int page)
1124 {
1125 int i, eccsize = chip->ecc.size;
1126 int eccbytes = chip->ecc.bytes;
1127 int eccsteps = chip->ecc.steps;
1128 uint8_t *p = buf;
1129 uint8_t *oob = chip->oob_poi;
1130
1131 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1132 int stat;
1133
1134 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1135 chip->read_buf(mtd, p, eccsize);
1136
1137 if (chip->ecc.prepad) {
1138 chip->read_buf(mtd, oob, chip->ecc.prepad);
1139 oob += chip->ecc.prepad;
1140 }
1141
1142 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1143 chip->read_buf(mtd, oob, eccbytes);
1144 stat = chip->ecc.correct(mtd, p, oob, NULL);
1145
1146 if (stat < 0)
1147 mtd->ecc_stats.failed++;
1148 else
1149 mtd->ecc_stats.corrected += stat;
1150
1151 oob += eccbytes;
1152
1153 if (chip->ecc.postpad) {
1154 chip->read_buf(mtd, oob, chip->ecc.postpad);
1155 oob += chip->ecc.postpad;
1156 }
1157 }
1158
1159 /* Calculate remaining oob bytes */
1160 i = mtd->oobsize - (oob - chip->oob_poi);
1161 if (i)
1162 chip->read_buf(mtd, oob, i);
1163
1164 return 0;
1165 }
1166
1167 /**
1168 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1169 * @chip: nand chip structure
1170 * @oob: oob destination address
1171 * @ops: oob ops structure
1172 * @len: size of oob to transfer
1173 */
1174 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1175 struct mtd_oob_ops *ops, size_t len)
1176 {
1177 switch(ops->mode) {
1178
1179 case MTD_OOB_PLACE:
1180 case MTD_OOB_RAW:
1181 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1182 return oob + len;
1183
1184 case MTD_OOB_AUTO: {
1185 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1186 uint32_t boffs = 0, roffs = ops->ooboffs;
1187 size_t bytes = 0;
1188
1189 for(; free->length && len; free++, len -= bytes) {
1190 /* Read request not from offset 0 ? */
1191 if (unlikely(roffs)) {
1192 if (roffs >= free->length) {
1193 roffs -= free->length;
1194 continue;
1195 }
1196 boffs = free->offset + roffs;
1197 bytes = min_t(size_t, len,
1198 (free->length - roffs));
1199 roffs = 0;
1200 } else {
1201 bytes = min_t(size_t, len, free->length);
1202 boffs = free->offset;
1203 }
1204 memcpy(oob, chip->oob_poi + boffs, bytes);
1205 oob += bytes;
1206 }
1207 return oob;
1208 }
1209 default:
1210 BUG();
1211 }
1212 return NULL;
1213 }
1214
1215 /**
1216 * nand_do_read_ops - [Internal] Read data with ECC
1217 *
1218 * @mtd: MTD device structure
1219 * @from: offset to read from
1220 * @ops: oob ops structure
1221 *
1222 * Internal function. Called with chip held.
1223 */
1224 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1225 struct mtd_oob_ops *ops)
1226 {
1227 int chipnr, page, realpage, col, bytes, aligned;
1228 struct nand_chip *chip = mtd->priv;
1229 struct mtd_ecc_stats stats;
1230 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1231 int sndcmd = 1;
1232 int ret = 0;
1233 uint32_t readlen = ops->len;
1234 uint32_t oobreadlen = ops->ooblen;
1235 uint8_t *bufpoi, *oob, *buf;
1236
1237 stats = mtd->ecc_stats;
1238
1239 chipnr = (int)(from >> chip->chip_shift);
1240 chip->select_chip(mtd, chipnr);
1241
1242 realpage = (int)(from >> chip->page_shift);
1243 page = realpage & chip->pagemask;
1244
1245 col = (int)(from & (mtd->writesize - 1));
1246
1247 buf = ops->datbuf;
1248 oob = ops->oobbuf;
1249
1250 while(1) {
1251 bytes = min(mtd->writesize - col, readlen);
1252 aligned = (bytes == mtd->writesize);
1253
1254 /* Is the current page in the buffer ? */
1255 if (realpage != chip->pagebuf || oob) {
1256 bufpoi = aligned ? buf : chip->buffers->databuf;
1257
1258 if (likely(sndcmd)) {
1259 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1260 sndcmd = 0;
1261 }
1262
1263 /* Now read the page into the buffer */
1264 if (unlikely(ops->mode == MTD_OOB_RAW))
1265 ret = chip->ecc.read_page_raw(mtd, chip,
1266 bufpoi, page);
1267 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1268 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1269 else
1270 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1271 page);
1272 if (ret < 0)
1273 break;
1274
1275 /* Transfer not aligned data */
1276 if (!aligned) {
1277 if (!NAND_SUBPAGE_READ(chip) && !oob)
1278 chip->pagebuf = realpage;
1279 memcpy(buf, chip->buffers->databuf + col, bytes);
1280 }
1281
1282 buf += bytes;
1283
1284 if (unlikely(oob)) {
1285 /* Raw mode does data:oob:data:oob */
1286 if (ops->mode != MTD_OOB_RAW) {
1287 int toread = min(oobreadlen,
1288 chip->ecc.layout->oobavail);
1289 if (toread) {
1290 oob = nand_transfer_oob(chip,
1291 oob, ops, toread);
1292 oobreadlen -= toread;
1293 }
1294 } else
1295 buf = nand_transfer_oob(chip,
1296 buf, ops, mtd->oobsize);
1297 }
1298
1299 if (!(chip->options & NAND_NO_READRDY)) {
1300 /*
1301 * Apply delay or wait for ready/busy pin. Do
1302 * this before the AUTOINCR check, so no
1303 * problems arise if a chip which does auto
1304 * increment is marked as NOAUTOINCR by the
1305 * board driver.
1306 */
1307 if (!chip->dev_ready)
1308 udelay(chip->chip_delay);
1309 else
1310 nand_wait_ready(mtd);
1311 }
1312 } else {
1313 memcpy(buf, chip->buffers->databuf + col, bytes);
1314 buf += bytes;
1315 }
1316
1317 readlen -= bytes;
1318
1319 if (!readlen)
1320 break;
1321
1322 /* For subsequent reads align to page boundary. */
1323 col = 0;
1324 /* Increment page address */
1325 realpage++;
1326
1327 page = realpage & chip->pagemask;
1328 /* Check, if we cross a chip boundary */
1329 if (!page) {
1330 chipnr++;
1331 chip->select_chip(mtd, -1);
1332 chip->select_chip(mtd, chipnr);
1333 }
1334
1335 /* Check, if the chip supports auto page increment
1336 * or if we have hit a block boundary.
1337 */
1338 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1339 sndcmd = 1;
1340 }
1341
1342 ops->retlen = ops->len - (size_t) readlen;
1343 if (oob)
1344 ops->oobretlen = ops->ooblen - oobreadlen;
1345
1346 if (ret)
1347 return ret;
1348
1349 if (mtd->ecc_stats.failed - stats.failed)
1350 return -EBADMSG;
1351
1352 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1353 }
1354
1355 /**
1356 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1357 * @mtd: MTD device structure
1358 * @from: offset to read from
1359 * @len: number of bytes to read
1360 * @retlen: pointer to variable to store the number of read bytes
1361 * @buf: the databuffer to put data
1362 *
1363 * Get hold of the chip and call nand_do_read
1364 */
1365 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1366 size_t *retlen, uint8_t *buf)
1367 {
1368 struct nand_chip *chip = mtd->priv;
1369 int ret;
1370
1371 /* Do not allow reads past end of device */
1372 if ((from + len) > mtd->size)
1373 return -EINVAL;
1374 if (!len)
1375 return 0;
1376
1377 nand_get_device(chip, mtd, FL_READING);
1378
1379 chip->ops.len = len;
1380 chip->ops.datbuf = buf;
1381 chip->ops.oobbuf = NULL;
1382
1383 ret = nand_do_read_ops(mtd, from, &chip->ops);
1384
1385 *retlen = chip->ops.retlen;
1386
1387 nand_release_device(mtd);
1388
1389 return ret;
1390 }
1391
1392 /**
1393 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1394 * @mtd: mtd info structure
1395 * @chip: nand chip info structure
1396 * @page: page number to read
1397 * @sndcmd: flag whether to issue read command or not
1398 */
1399 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1400 int page, int sndcmd)
1401 {
1402 if (sndcmd) {
1403 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1404 sndcmd = 0;
1405 }
1406 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1407 return sndcmd;
1408 }
1409
1410 /**
1411 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1412 * with syndromes
1413 * @mtd: mtd info structure
1414 * @chip: nand chip info structure
1415 * @page: page number to read
1416 * @sndcmd: flag whether to issue read command or not
1417 */
1418 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1419 int page, int sndcmd)
1420 {
1421 uint8_t *buf = chip->oob_poi;
1422 int length = mtd->oobsize;
1423 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1424 int eccsize = chip->ecc.size;
1425 uint8_t *bufpoi = buf;
1426 int i, toread, sndrnd = 0, pos;
1427
1428 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1429 for (i = 0; i < chip->ecc.steps; i++) {
1430 if (sndrnd) {
1431 pos = eccsize + i * (eccsize + chunk);
1432 if (mtd->writesize > 512)
1433 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1434 else
1435 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1436 } else
1437 sndrnd = 1;
1438 toread = min_t(int, length, chunk);
1439 chip->read_buf(mtd, bufpoi, toread);
1440 bufpoi += toread;
1441 length -= toread;
1442 }
1443 if (length > 0)
1444 chip->read_buf(mtd, bufpoi, length);
1445
1446 return 1;
1447 }
1448
1449 /**
1450 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1451 * @mtd: mtd info structure
1452 * @chip: nand chip info structure
1453 * @page: page number to write
1454 */
1455 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1456 int page)
1457 {
1458 int status = 0;
1459 const uint8_t *buf = chip->oob_poi;
1460 int length = mtd->oobsize;
1461
1462 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1463 chip->write_buf(mtd, buf, length);
1464 /* Send command to program the OOB data */
1465 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1466
1467 status = chip->waitfunc(mtd, chip);
1468
1469 return status & NAND_STATUS_FAIL ? -EIO : 0;
1470 }
1471
1472 /**
1473 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1474 * with syndrome - only for large page flash !
1475 * @mtd: mtd info structure
1476 * @chip: nand chip info structure
1477 * @page: page number to write
1478 */
1479 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1480 struct nand_chip *chip, int page)
1481 {
1482 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1483 int eccsize = chip->ecc.size, length = mtd->oobsize;
1484 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1485 const uint8_t *bufpoi = chip->oob_poi;
1486
1487 /*
1488 * data-ecc-data-ecc ... ecc-oob
1489 * or
1490 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1491 */
1492 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1493 pos = steps * (eccsize + chunk);
1494 steps = 0;
1495 } else
1496 pos = eccsize;
1497
1498 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1499 for (i = 0; i < steps; i++) {
1500 if (sndcmd) {
1501 if (mtd->writesize <= 512) {
1502 uint32_t fill = 0xFFFFFFFF;
1503
1504 len = eccsize;
1505 while (len > 0) {
1506 int num = min_t(int, len, 4);
1507 chip->write_buf(mtd, (uint8_t *)&fill,
1508 num);
1509 len -= num;
1510 }
1511 } else {
1512 pos = eccsize + i * (eccsize + chunk);
1513 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1514 }
1515 } else
1516 sndcmd = 1;
1517 len = min_t(int, length, chunk);
1518 chip->write_buf(mtd, bufpoi, len);
1519 bufpoi += len;
1520 length -= len;
1521 }
1522 if (length > 0)
1523 chip->write_buf(mtd, bufpoi, length);
1524
1525 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1526 status = chip->waitfunc(mtd, chip);
1527
1528 return status & NAND_STATUS_FAIL ? -EIO : 0;
1529 }
1530
1531 /**
1532 * nand_do_read_oob - [Intern] NAND read out-of-band
1533 * @mtd: MTD device structure
1534 * @from: offset to read from
1535 * @ops: oob operations description structure
1536 *
1537 * NAND read out-of-band data from the spare area
1538 */
1539 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1540 struct mtd_oob_ops *ops)
1541 {
1542 int page, realpage, chipnr, sndcmd = 1;
1543 struct nand_chip *chip = mtd->priv;
1544 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1545 int readlen = ops->ooblen;
1546 int len;
1547 uint8_t *buf = ops->oobbuf;
1548
1549 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1550 __func__, (unsigned long long)from, readlen);
1551
1552 if (ops->mode == MTD_OOB_AUTO)
1553 len = chip->ecc.layout->oobavail;
1554 else
1555 len = mtd->oobsize;
1556
1557 if (unlikely(ops->ooboffs >= len)) {
1558 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1559 "outside oob\n", __func__);
1560 return -EINVAL;
1561 }
1562
1563 /* Do not allow reads past end of device */
1564 if (unlikely(from >= mtd->size ||
1565 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1566 (from >> chip->page_shift)) * len)) {
1567 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1568 "of device\n", __func__);
1569 return -EINVAL;
1570 }
1571
1572 chipnr = (int)(from >> chip->chip_shift);
1573 chip->select_chip(mtd, chipnr);
1574
1575 /* Shift to get page */
1576 realpage = (int)(from >> chip->page_shift);
1577 page = realpage & chip->pagemask;
1578
1579 while(1) {
1580 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1581
1582 len = min(len, readlen);
1583 buf = nand_transfer_oob(chip, buf, ops, len);
1584
1585 if (!(chip->options & NAND_NO_READRDY)) {
1586 /*
1587 * Apply delay or wait for ready/busy pin. Do this
1588 * before the AUTOINCR check, so no problems arise if a
1589 * chip which does auto increment is marked as
1590 * NOAUTOINCR by the board driver.
1591 */
1592 if (!chip->dev_ready)
1593 udelay(chip->chip_delay);
1594 else
1595 nand_wait_ready(mtd);
1596 }
1597
1598 readlen -= len;
1599 if (!readlen)
1600 break;
1601
1602 /* Increment page address */
1603 realpage++;
1604
1605 page = realpage & chip->pagemask;
1606 /* Check, if we cross a chip boundary */
1607 if (!page) {
1608 chipnr++;
1609 chip->select_chip(mtd, -1);
1610 chip->select_chip(mtd, chipnr);
1611 }
1612
1613 /* Check, if the chip supports auto page increment
1614 * or if we have hit a block boundary.
1615 */
1616 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1617 sndcmd = 1;
1618 }
1619
1620 ops->oobretlen = ops->ooblen;
1621 return 0;
1622 }
1623
1624 /**
1625 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1626 * @mtd: MTD device structure
1627 * @from: offset to read from
1628 * @ops: oob operation description structure
1629 *
1630 * NAND read data and/or out-of-band data
1631 */
1632 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1633 struct mtd_oob_ops *ops)
1634 {
1635 struct nand_chip *chip = mtd->priv;
1636 int ret = -ENOTSUPP;
1637
1638 ops->retlen = 0;
1639
1640 /* Do not allow reads past end of device */
1641 if (ops->datbuf && (from + ops->len) > mtd->size) {
1642 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1643 "beyond end of device\n", __func__);
1644 return -EINVAL;
1645 }
1646
1647 nand_get_device(chip, mtd, FL_READING);
1648
1649 switch(ops->mode) {
1650 case MTD_OOB_PLACE:
1651 case MTD_OOB_AUTO:
1652 case MTD_OOB_RAW:
1653 break;
1654
1655 default:
1656 goto out;
1657 }
1658
1659 if (!ops->datbuf)
1660 ret = nand_do_read_oob(mtd, from, ops);
1661 else
1662 ret = nand_do_read_ops(mtd, from, ops);
1663
1664 out:
1665 nand_release_device(mtd);
1666 return ret;
1667 }
1668
1669
1670 /**
1671 * nand_write_page_raw - [Intern] raw page write function
1672 * @mtd: mtd info structure
1673 * @chip: nand chip info structure
1674 * @buf: data buffer
1675 *
1676 * Not for syndrome calculating ecc controllers, which use a special oob layout
1677 */
1678 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1679 const uint8_t *buf)
1680 {
1681 chip->write_buf(mtd, buf, mtd->writesize);
1682 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1683 }
1684
1685 /**
1686 * nand_write_page_raw_syndrome - [Intern] raw page write function
1687 * @mtd: mtd info structure
1688 * @chip: nand chip info structure
1689 * @buf: data buffer
1690 *
1691 * We need a special oob layout and handling even when ECC isn't checked.
1692 */
1693 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1694 const uint8_t *buf)
1695 {
1696 int eccsize = chip->ecc.size;
1697 int eccbytes = chip->ecc.bytes;
1698 uint8_t *oob = chip->oob_poi;
1699 int steps, size;
1700
1701 for (steps = chip->ecc.steps; steps > 0; steps--) {
1702 chip->write_buf(mtd, buf, eccsize);
1703 buf += eccsize;
1704
1705 if (chip->ecc.prepad) {
1706 chip->write_buf(mtd, oob, chip->ecc.prepad);
1707 oob += chip->ecc.prepad;
1708 }
1709
1710 chip->read_buf(mtd, oob, eccbytes);
1711 oob += eccbytes;
1712
1713 if (chip->ecc.postpad) {
1714 chip->write_buf(mtd, oob, chip->ecc.postpad);
1715 oob += chip->ecc.postpad;
1716 }
1717 }
1718
1719 size = mtd->oobsize - (oob - chip->oob_poi);
1720 if (size)
1721 chip->write_buf(mtd, oob, size);
1722 }
1723 /**
1724 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1725 * @mtd: mtd info structure
1726 * @chip: nand chip info structure
1727 * @buf: data buffer
1728 */
1729 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1730 const uint8_t *buf)
1731 {
1732 int i, eccsize = chip->ecc.size;
1733 int eccbytes = chip->ecc.bytes;
1734 int eccsteps = chip->ecc.steps;
1735 uint8_t *ecc_calc = chip->buffers->ecccalc;
1736 const uint8_t *p = buf;
1737 uint32_t *eccpos = chip->ecc.layout->eccpos;
1738
1739 /* Software ecc calculation */
1740 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1741 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1742
1743 for (i = 0; i < chip->ecc.total; i++)
1744 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1745
1746 chip->ecc.write_page_raw(mtd, chip, buf);
1747 }
1748
1749 /**
1750 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1751 * @mtd: mtd info structure
1752 * @chip: nand chip info structure
1753 * @buf: data buffer
1754 */
1755 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1756 const uint8_t *buf)
1757 {
1758 int i, eccsize = chip->ecc.size;
1759 int eccbytes = chip->ecc.bytes;
1760 int eccsteps = chip->ecc.steps;
1761 uint8_t *ecc_calc = chip->buffers->ecccalc;
1762 const uint8_t *p = buf;
1763 uint32_t *eccpos = chip->ecc.layout->eccpos;
1764
1765 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1766 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1767 chip->write_buf(mtd, p, eccsize);
1768 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1769 }
1770
1771 for (i = 0; i < chip->ecc.total; i++)
1772 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1773
1774 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1775 }
1776
1777 /**
1778 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1779 * @mtd: mtd info structure
1780 * @chip: nand chip info structure
1781 * @buf: data buffer
1782 *
1783 * The hw generator calculates the error syndrome automatically. Therefor
1784 * we need a special oob layout and handling.
1785 */
1786 static void nand_write_page_syndrome(struct mtd_info *mtd,
1787 struct nand_chip *chip, const uint8_t *buf)
1788 {
1789 int i, eccsize = chip->ecc.size;
1790 int eccbytes = chip->ecc.bytes;
1791 int eccsteps = chip->ecc.steps;
1792 const uint8_t *p = buf;
1793 uint8_t *oob = chip->oob_poi;
1794
1795 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1796
1797 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1798 chip->write_buf(mtd, p, eccsize);
1799
1800 if (chip->ecc.prepad) {
1801 chip->write_buf(mtd, oob, chip->ecc.prepad);
1802 oob += chip->ecc.prepad;
1803 }
1804
1805 chip->ecc.calculate(mtd, p, oob);
1806 chip->write_buf(mtd, oob, eccbytes);
1807 oob += eccbytes;
1808
1809 if (chip->ecc.postpad) {
1810 chip->write_buf(mtd, oob, chip->ecc.postpad);
1811 oob += chip->ecc.postpad;
1812 }
1813 }
1814
1815 /* Calculate remaining oob bytes */
1816 i = mtd->oobsize - (oob - chip->oob_poi);
1817 if (i)
1818 chip->write_buf(mtd, oob, i);
1819 }
1820
1821 /**
1822 * nand_write_page - [REPLACEABLE] write one page
1823 * @mtd: MTD device structure
1824 * @chip: NAND chip descriptor
1825 * @buf: the data to write
1826 * @page: page number to write
1827 * @cached: cached programming
1828 * @raw: use _raw version of write_page
1829 */
1830 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1831 const uint8_t *buf, int page, int cached, int raw)
1832 {
1833 int status;
1834
1835 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1836
1837 if (unlikely(raw))
1838 chip->ecc.write_page_raw(mtd, chip, buf);
1839 else
1840 chip->ecc.write_page(mtd, chip, buf);
1841
1842 /*
1843 * Cached progamming disabled for now, Not sure if its worth the
1844 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1845 */
1846 cached = 0;
1847
1848 if (!cached || !(chip->options & NAND_CACHEPRG)) {
1849
1850 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1851 status = chip->waitfunc(mtd, chip);
1852 /*
1853 * See if operation failed and additional status checks are
1854 * available
1855 */
1856 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1857 status = chip->errstat(mtd, chip, FL_WRITING, status,
1858 page);
1859
1860 if (status & NAND_STATUS_FAIL)
1861 return -EIO;
1862 } else {
1863 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1864 status = chip->waitfunc(mtd, chip);
1865 }
1866
1867 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1868 /* Send command to read back the data */
1869 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1870
1871 if (chip->verify_buf(mtd, buf, mtd->writesize))
1872 return -EIO;
1873 #endif
1874 return 0;
1875 }
1876
1877 /**
1878 * nand_fill_oob - [Internal] Transfer client buffer to oob
1879 * @chip: nand chip structure
1880 * @oob: oob data buffer
1881 * @ops: oob ops structure
1882 */
1883 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1884 struct mtd_oob_ops *ops)
1885 {
1886 size_t len = ops->ooblen;
1887
1888 switch(ops->mode) {
1889
1890 case MTD_OOB_PLACE:
1891 case MTD_OOB_RAW:
1892 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1893 return oob + len;
1894
1895 case MTD_OOB_AUTO: {
1896 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1897 uint32_t boffs = 0, woffs = ops->ooboffs;
1898 size_t bytes = 0;
1899
1900 for(; free->length && len; free++, len -= bytes) {
1901 /* Write request not from offset 0 ? */
1902 if (unlikely(woffs)) {
1903 if (woffs >= free->length) {
1904 woffs -= free->length;
1905 continue;
1906 }
1907 boffs = free->offset + woffs;
1908 bytes = min_t(size_t, len,
1909 (free->length - woffs));
1910 woffs = 0;
1911 } else {
1912 bytes = min_t(size_t, len, free->length);
1913 boffs = free->offset;
1914 }
1915 memcpy(chip->oob_poi + boffs, oob, bytes);
1916 oob += bytes;
1917 }
1918 return oob;
1919 }
1920 default:
1921 BUG();
1922 }
1923 return NULL;
1924 }
1925
1926 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
1927
1928 /**
1929 * nand_do_write_ops - [Internal] NAND write with ECC
1930 * @mtd: MTD device structure
1931 * @to: offset to write to
1932 * @ops: oob operations description structure
1933 *
1934 * NAND write with ECC
1935 */
1936 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1937 struct mtd_oob_ops *ops)
1938 {
1939 int chipnr, realpage, page, blockmask, column;
1940 struct nand_chip *chip = mtd->priv;
1941 uint32_t writelen = ops->len;
1942 uint8_t *oob = ops->oobbuf;
1943 uint8_t *buf = ops->datbuf;
1944 int ret, subpage;
1945
1946 ops->retlen = 0;
1947 if (!writelen)
1948 return 0;
1949
1950 /* reject writes, which are not page aligned */
1951 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1952 printk(KERN_NOTICE "%s: Attempt to write not "
1953 "page aligned data\n", __func__);
1954 return -EINVAL;
1955 }
1956
1957 column = to & (mtd->writesize - 1);
1958 subpage = column || (writelen & (mtd->writesize - 1));
1959
1960 if (subpage && oob)
1961 return -EINVAL;
1962
1963 chipnr = (int)(to >> chip->chip_shift);
1964 chip->select_chip(mtd, chipnr);
1965
1966 /* Check, if it is write protected */
1967 if (nand_check_wp(mtd))
1968 return -EIO;
1969
1970 realpage = (int)(to >> chip->page_shift);
1971 page = realpage & chip->pagemask;
1972 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1973
1974 /* Invalidate the page cache, when we write to the cached page */
1975 if (to <= (chip->pagebuf << chip->page_shift) &&
1976 (chip->pagebuf << chip->page_shift) < (to + ops->len))
1977 chip->pagebuf = -1;
1978
1979 /* If we're not given explicit OOB data, let it be 0xFF */
1980 if (likely(!oob))
1981 memset(chip->oob_poi, 0xff, mtd->oobsize);
1982
1983 while(1) {
1984 int bytes = mtd->writesize;
1985 int cached = writelen > bytes && page != blockmask;
1986 uint8_t *wbuf = buf;
1987
1988 /* Partial page write ? */
1989 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1990 cached = 0;
1991 bytes = min_t(int, bytes - column, (int) writelen);
1992 chip->pagebuf = -1;
1993 memset(chip->buffers->databuf, 0xff, mtd->writesize);
1994 memcpy(&chip->buffers->databuf[column], buf, bytes);
1995 wbuf = chip->buffers->databuf;
1996 }
1997
1998 if (unlikely(oob))
1999 oob = nand_fill_oob(chip, oob, ops);
2000
2001 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2002 (ops->mode == MTD_OOB_RAW));
2003 if (ret)
2004 break;
2005
2006 writelen -= bytes;
2007 if (!writelen)
2008 break;
2009
2010 column = 0;
2011 buf += bytes;
2012 realpage++;
2013
2014 page = realpage & chip->pagemask;
2015 /* Check, if we cross a chip boundary */
2016 if (!page) {
2017 chipnr++;
2018 chip->select_chip(mtd, -1);
2019 chip->select_chip(mtd, chipnr);
2020 }
2021 }
2022
2023 ops->retlen = ops->len - writelen;
2024 if (unlikely(oob))
2025 ops->oobretlen = ops->ooblen;
2026 return ret;
2027 }
2028
2029 /**
2030 * panic_nand_write - [MTD Interface] NAND write with ECC
2031 * @mtd: MTD device structure
2032 * @to: offset to write to
2033 * @len: number of bytes to write
2034 * @retlen: pointer to variable to store the number of written bytes
2035 * @buf: the data to write
2036 *
2037 * NAND write with ECC. Used when performing writes in interrupt context, this
2038 * may for example be called by mtdoops when writing an oops while in panic.
2039 */
2040 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2041 size_t *retlen, const uint8_t *buf)
2042 {
2043 struct nand_chip *chip = mtd->priv;
2044 int ret;
2045
2046 /* Do not allow reads past end of device */
2047 if ((to + len) > mtd->size)
2048 return -EINVAL;
2049 if (!len)
2050 return 0;
2051
2052 /* Wait for the device to get ready. */
2053 panic_nand_wait(mtd, chip, 400);
2054
2055 /* Grab the device. */
2056 panic_nand_get_device(chip, mtd, FL_WRITING);
2057
2058 chip->ops.len = len;
2059 chip->ops.datbuf = (uint8_t *)buf;
2060 chip->ops.oobbuf = NULL;
2061
2062 ret = nand_do_write_ops(mtd, to, &chip->ops);
2063
2064 *retlen = chip->ops.retlen;
2065 return ret;
2066 }
2067
2068 /**
2069 * nand_write - [MTD Interface] NAND write with ECC
2070 * @mtd: MTD device structure
2071 * @to: offset to write to
2072 * @len: number of bytes to write
2073 * @retlen: pointer to variable to store the number of written bytes
2074 * @buf: the data to write
2075 *
2076 * NAND write with ECC
2077 */
2078 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2079 size_t *retlen, const uint8_t *buf)
2080 {
2081 struct nand_chip *chip = mtd->priv;
2082 int ret;
2083
2084 /* Do not allow reads past end of device */
2085 if ((to + len) > mtd->size)
2086 return -EINVAL;
2087 if (!len)
2088 return 0;
2089
2090 nand_get_device(chip, mtd, FL_WRITING);
2091
2092 chip->ops.len = len;
2093 chip->ops.datbuf = (uint8_t *)buf;
2094 chip->ops.oobbuf = NULL;
2095
2096 ret = nand_do_write_ops(mtd, to, &chip->ops);
2097
2098 *retlen = chip->ops.retlen;
2099
2100 nand_release_device(mtd);
2101
2102 return ret;
2103 }
2104
2105 /**
2106 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2107 * @mtd: MTD device structure
2108 * @to: offset to write to
2109 * @ops: oob operation description structure
2110 *
2111 * NAND write out-of-band
2112 */
2113 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2114 struct mtd_oob_ops *ops)
2115 {
2116 int chipnr, page, status, len;
2117 struct nand_chip *chip = mtd->priv;
2118
2119 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2120 __func__, (unsigned int)to, (int)ops->ooblen);
2121
2122 if (ops->mode == MTD_OOB_AUTO)
2123 len = chip->ecc.layout->oobavail;
2124 else
2125 len = mtd->oobsize;
2126
2127 /* Do not allow write past end of page */
2128 if ((ops->ooboffs + ops->ooblen) > len) {
2129 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2130 "past end of page\n", __func__);
2131 return -EINVAL;
2132 }
2133
2134 if (unlikely(ops->ooboffs >= len)) {
2135 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2136 "write outside oob\n", __func__);
2137 return -EINVAL;
2138 }
2139
2140 /* Do not allow reads past end of device */
2141 if (unlikely(to >= mtd->size ||
2142 ops->ooboffs + ops->ooblen >
2143 ((mtd->size >> chip->page_shift) -
2144 (to >> chip->page_shift)) * len)) {
2145 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2146 "end of device\n", __func__);
2147 return -EINVAL;
2148 }
2149
2150 chipnr = (int)(to >> chip->chip_shift);
2151 chip->select_chip(mtd, chipnr);
2152
2153 /* Shift to get page */
2154 page = (int)(to >> chip->page_shift);
2155
2156 /*
2157 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2158 * of my DiskOnChip 2000 test units) will clear the whole data page too
2159 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2160 * it in the doc2000 driver in August 1999. dwmw2.
2161 */
2162 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2163
2164 /* Check, if it is write protected */
2165 if (nand_check_wp(mtd))
2166 return -EROFS;
2167
2168 /* Invalidate the page cache, if we write to the cached page */
2169 if (page == chip->pagebuf)
2170 chip->pagebuf = -1;
2171
2172 memset(chip->oob_poi, 0xff, mtd->oobsize);
2173 nand_fill_oob(chip, ops->oobbuf, ops);
2174 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2175 memset(chip->oob_poi, 0xff, mtd->oobsize);
2176
2177 if (status)
2178 return status;
2179
2180 ops->oobretlen = ops->ooblen;
2181
2182 return 0;
2183 }
2184
2185 /**
2186 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2187 * @mtd: MTD device structure
2188 * @to: offset to write to
2189 * @ops: oob operation description structure
2190 */
2191 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2192 struct mtd_oob_ops *ops)
2193 {
2194 struct nand_chip *chip = mtd->priv;
2195 int ret = -ENOTSUPP;
2196
2197 ops->retlen = 0;
2198
2199 /* Do not allow writes past end of device */
2200 if (ops->datbuf && (to + ops->len) > mtd->size) {
2201 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2202 "end of device\n", __func__);
2203 return -EINVAL;
2204 }
2205
2206 nand_get_device(chip, mtd, FL_WRITING);
2207
2208 switch(ops->mode) {
2209 case MTD_OOB_PLACE:
2210 case MTD_OOB_AUTO:
2211 case MTD_OOB_RAW:
2212 break;
2213
2214 default:
2215 goto out;
2216 }
2217
2218 if (!ops->datbuf)
2219 ret = nand_do_write_oob(mtd, to, ops);
2220 else
2221 ret = nand_do_write_ops(mtd, to, ops);
2222
2223 out:
2224 nand_release_device(mtd);
2225 return ret;
2226 }
2227
2228 /**
2229 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2230 * @mtd: MTD device structure
2231 * @page: the page address of the block which will be erased
2232 *
2233 * Standard erase command for NAND chips
2234 */
2235 static void single_erase_cmd(struct mtd_info *mtd, int page)
2236 {
2237 struct nand_chip *chip = mtd->priv;
2238 /* Send commands to erase a block */
2239 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2240 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2241 }
2242
2243 /**
2244 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2245 * @mtd: MTD device structure
2246 * @page: the page address of the block which will be erased
2247 *
2248 * AND multi block erase command function
2249 * Erase 4 consecutive blocks
2250 */
2251 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2252 {
2253 struct nand_chip *chip = mtd->priv;
2254 /* Send commands to erase a block */
2255 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2256 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2257 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2258 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2259 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2260 }
2261
2262 /**
2263 * nand_erase - [MTD Interface] erase block(s)
2264 * @mtd: MTD device structure
2265 * @instr: erase instruction
2266 *
2267 * Erase one ore more blocks
2268 */
2269 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2270 {
2271 return nand_erase_nand(mtd, instr, 0);
2272 }
2273
2274 #define BBT_PAGE_MASK 0xffffff3f
2275 /**
2276 * nand_erase_nand - [Internal] erase block(s)
2277 * @mtd: MTD device structure
2278 * @instr: erase instruction
2279 * @allowbbt: allow erasing the bbt area
2280 *
2281 * Erase one ore more blocks
2282 */
2283 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2284 int allowbbt)
2285 {
2286 int page, status, pages_per_block, ret, chipnr;
2287 struct nand_chip *chip = mtd->priv;
2288 loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2289 unsigned int bbt_masked_page = 0xffffffff;
2290 loff_t len;
2291
2292 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2293 __func__, (unsigned long long)instr->addr,
2294 (unsigned long long)instr->len);
2295
2296 /* Start address must align on block boundary */
2297 if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2298 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
2299 return -EINVAL;
2300 }
2301
2302 /* Length must align on block boundary */
2303 if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2304 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
2305 __func__);
2306 return -EINVAL;
2307 }
2308
2309 /* Do not allow erase past end of device */
2310 if ((instr->len + instr->addr) > mtd->size) {
2311 DEBUG(MTD_DEBUG_LEVEL0, "%s: Erase past end of device\n",
2312 __func__);
2313 return -EINVAL;
2314 }
2315
2316 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2317
2318 /* Grab the lock and see if the device is available */
2319 nand_get_device(chip, mtd, FL_ERASING);
2320
2321 /* Shift to get first page */
2322 page = (int)(instr->addr >> chip->page_shift);
2323 chipnr = (int)(instr->addr >> chip->chip_shift);
2324
2325 /* Calculate pages in each block */
2326 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2327
2328 /* Select the NAND device */
2329 chip->select_chip(mtd, chipnr);
2330
2331 /* Check, if it is write protected */
2332 if (nand_check_wp(mtd)) {
2333 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2334 __func__);
2335 instr->state = MTD_ERASE_FAILED;
2336 goto erase_exit;
2337 }
2338
2339 /*
2340 * If BBT requires refresh, set the BBT page mask to see if the BBT
2341 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2342 * can not be matched. This is also done when the bbt is actually
2343 * erased to avoid recusrsive updates
2344 */
2345 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2346 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2347
2348 /* Loop through the pages */
2349 len = instr->len;
2350
2351 instr->state = MTD_ERASING;
2352
2353 while (len) {
2354 /*
2355 * heck if we have a bad block, we do not erase bad blocks !
2356 */
2357 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2358 chip->page_shift, 0, allowbbt)) {
2359 printk(KERN_WARNING "%s: attempt to erase a bad block "
2360 "at page 0x%08x\n", __func__, page);
2361 instr->state = MTD_ERASE_FAILED;
2362 goto erase_exit;
2363 }
2364
2365 /*
2366 * Invalidate the page cache, if we erase the block which
2367 * contains the current cached page
2368 */
2369 if (page <= chip->pagebuf && chip->pagebuf <
2370 (page + pages_per_block))
2371 chip->pagebuf = -1;
2372
2373 chip->erase_cmd(mtd, page & chip->pagemask);
2374
2375 status = chip->waitfunc(mtd, chip);
2376
2377 /*
2378 * See if operation failed and additional status checks are
2379 * available
2380 */
2381 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2382 status = chip->errstat(mtd, chip, FL_ERASING,
2383 status, page);
2384
2385 /* See if block erase succeeded */
2386 if (status & NAND_STATUS_FAIL) {
2387 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2388 "page 0x%08x\n", __func__, page);
2389 instr->state = MTD_ERASE_FAILED;
2390 instr->fail_addr =
2391 ((loff_t)page << chip->page_shift);
2392 goto erase_exit;
2393 }
2394
2395 /*
2396 * If BBT requires refresh, set the BBT rewrite flag to the
2397 * page being erased
2398 */
2399 if (bbt_masked_page != 0xffffffff &&
2400 (page & BBT_PAGE_MASK) == bbt_masked_page)
2401 rewrite_bbt[chipnr] =
2402 ((loff_t)page << chip->page_shift);
2403
2404 /* Increment page address and decrement length */
2405 len -= (1 << chip->phys_erase_shift);
2406 page += pages_per_block;
2407
2408 /* Check, if we cross a chip boundary */
2409 if (len && !(page & chip->pagemask)) {
2410 chipnr++;
2411 chip->select_chip(mtd, -1);
2412 chip->select_chip(mtd, chipnr);
2413
2414 /*
2415 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2416 * page mask to see if this BBT should be rewritten
2417 */
2418 if (bbt_masked_page != 0xffffffff &&
2419 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2420 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2421 BBT_PAGE_MASK;
2422 }
2423 }
2424 instr->state = MTD_ERASE_DONE;
2425
2426 erase_exit:
2427
2428 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2429
2430 /* Deselect and wake up anyone waiting on the device */
2431 nand_release_device(mtd);
2432
2433 /* Do call back function */
2434 if (!ret)
2435 mtd_erase_callback(instr);
2436
2437 /*
2438 * If BBT requires refresh and erase was successful, rewrite any
2439 * selected bad block tables
2440 */
2441 if (bbt_masked_page == 0xffffffff || ret)
2442 return ret;
2443
2444 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2445 if (!rewrite_bbt[chipnr])
2446 continue;
2447 /* update the BBT for chip */
2448 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2449 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2450 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2451 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2452 }
2453
2454 /* Return more or less happy */
2455 return ret;
2456 }
2457
2458 /**
2459 * nand_sync - [MTD Interface] sync
2460 * @mtd: MTD device structure
2461 *
2462 * Sync is actually a wait for chip ready function
2463 */
2464 static void nand_sync(struct mtd_info *mtd)
2465 {
2466 struct nand_chip *chip = mtd->priv;
2467
2468 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2469
2470 /* Grab the lock and see if the device is available */
2471 nand_get_device(chip, mtd, FL_SYNCING);
2472 /* Release it and go back */
2473 nand_release_device(mtd);
2474 }
2475
2476 /**
2477 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2478 * @mtd: MTD device structure
2479 * @offs: offset relative to mtd start
2480 */
2481 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2482 {
2483 /* Check for invalid offset */
2484 if (offs > mtd->size)
2485 return -EINVAL;
2486
2487 return nand_block_checkbad(mtd, offs, 1, 0);
2488 }
2489
2490 /**
2491 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2492 * @mtd: MTD device structure
2493 * @ofs: offset relative to mtd start
2494 */
2495 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2496 {
2497 struct nand_chip *chip = mtd->priv;
2498 int ret;
2499
2500 if ((ret = nand_block_isbad(mtd, ofs))) {
2501 /* If it was bad already, return success and do nothing. */
2502 if (ret > 0)
2503 return 0;
2504 return ret;
2505 }
2506
2507 return chip->block_markbad(mtd, ofs);
2508 }
2509
2510 /**
2511 * nand_suspend - [MTD Interface] Suspend the NAND flash
2512 * @mtd: MTD device structure
2513 */
2514 static int nand_suspend(struct mtd_info *mtd)
2515 {
2516 struct nand_chip *chip = mtd->priv;
2517
2518 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2519 }
2520
2521 /**
2522 * nand_resume - [MTD Interface] Resume the NAND flash
2523 * @mtd: MTD device structure
2524 */
2525 static void nand_resume(struct mtd_info *mtd)
2526 {
2527 struct nand_chip *chip = mtd->priv;
2528
2529 if (chip->state == FL_PM_SUSPENDED)
2530 nand_release_device(mtd);
2531 else
2532 printk(KERN_ERR "%s called for a chip which is not "
2533 "in suspended state\n", __func__);
2534 }
2535
2536 /*
2537 * Set default functions
2538 */
2539 static void nand_set_defaults(struct nand_chip *chip, int busw)
2540 {
2541 /* check for proper chip_delay setup, set 20us if not */
2542 if (!chip->chip_delay)
2543 chip->chip_delay = 20;
2544
2545 /* check, if a user supplied command function given */
2546 if (chip->cmdfunc == NULL)
2547 chip->cmdfunc = nand_command;
2548
2549 /* check, if a user supplied wait function given */
2550 if (chip->waitfunc == NULL)
2551 chip->waitfunc = nand_wait;
2552
2553 if (!chip->select_chip)
2554 chip->select_chip = nand_select_chip;
2555 if (!chip->read_byte)
2556 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2557 if (!chip->read_word)
2558 chip->read_word = nand_read_word;
2559 if (!chip->block_bad)
2560 chip->block_bad = nand_block_bad;
2561 if (!chip->block_markbad)
2562 chip->block_markbad = nand_default_block_markbad;
2563 if (!chip->write_buf)
2564 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2565 if (!chip->read_buf)
2566 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2567 if (!chip->verify_buf)
2568 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2569 if (!chip->scan_bbt)
2570 chip->scan_bbt = nand_default_bbt;
2571
2572 if (!chip->controller) {
2573 chip->controller = &chip->hwcontrol;
2574 spin_lock_init(&chip->controller->lock);
2575 init_waitqueue_head(&chip->controller->wq);
2576 }
2577
2578 }
2579
2580 /*
2581 * Get the flash and manufacturer id and lookup if the type is supported
2582 */
2583 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2584 struct nand_chip *chip,
2585 int busw, int *maf_id)
2586 {
2587 struct nand_flash_dev *type = NULL;
2588 int i, dev_id, maf_idx;
2589 int tmp_id, tmp_manf;
2590
2591 /* Select the device */
2592 chip->select_chip(mtd, 0);
2593
2594 /*
2595 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2596 * after power-up
2597 */
2598 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2599
2600 /* Send the command for reading device ID */
2601 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2602
2603 /* Read manufacturer and device IDs */
2604 *maf_id = chip->read_byte(mtd);
2605 dev_id = chip->read_byte(mtd);
2606
2607 /* Try again to make sure, as some systems the bus-hold or other
2608 * interface concerns can cause random data which looks like a
2609 * possibly credible NAND flash to appear. If the two results do
2610 * not match, ignore the device completely.
2611 */
2612
2613 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2614
2615 /* Read manufacturer and device IDs */
2616
2617 tmp_manf = chip->read_byte(mtd);
2618 tmp_id = chip->read_byte(mtd);
2619
2620 if (tmp_manf != *maf_id || tmp_id != dev_id) {
2621 printk(KERN_INFO "%s: second ID read did not match "
2622 "%02x,%02x against %02x,%02x\n", __func__,
2623 *maf_id, dev_id, tmp_manf, tmp_id);
2624 return ERR_PTR(-ENODEV);
2625 }
2626
2627 /* Lookup the flash id */
2628 for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2629 if (dev_id == nand_flash_ids[i].id) {
2630 type = &nand_flash_ids[i];
2631 break;
2632 }
2633 }
2634
2635 if (!type)
2636 return ERR_PTR(-ENODEV);
2637
2638 if (!mtd->name)
2639 mtd->name = type->name;
2640
2641 chip->chipsize = (uint64_t)type->chipsize << 20;
2642
2643 /* Newer devices have all the information in additional id bytes */
2644 if (!type->pagesize) {
2645 int extid;
2646 /* The 3rd id byte holds MLC / multichip data */
2647 chip->cellinfo = chip->read_byte(mtd);
2648 /* The 4th id byte is the important one */
2649 extid = chip->read_byte(mtd);
2650 /* Calc pagesize */
2651 mtd->writesize = 1024 << (extid & 0x3);
2652 extid >>= 2;
2653 /* Calc oobsize */
2654 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2655 extid >>= 2;
2656 /* Calc blocksize. Blocksize is multiples of 64KiB */
2657 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2658 extid >>= 2;
2659 /* Get buswidth information */
2660 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2661
2662 } else {
2663 /*
2664 * Old devices have chip data hardcoded in the device id table
2665 */
2666 mtd->erasesize = type->erasesize;
2667 mtd->writesize = type->pagesize;
2668 mtd->oobsize = mtd->writesize / 32;
2669 busw = type->options & NAND_BUSWIDTH_16;
2670 }
2671
2672 /* Try to identify manufacturer */
2673 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2674 if (nand_manuf_ids[maf_idx].id == *maf_id)
2675 break;
2676 }
2677
2678 /*
2679 * Check, if buswidth is correct. Hardware drivers should set
2680 * chip correct !
2681 */
2682 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2683 printk(KERN_INFO "NAND device: Manufacturer ID:"
2684 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2685 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2686 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2687 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2688 busw ? 16 : 8);
2689 return ERR_PTR(-EINVAL);
2690 }
2691
2692 /* Calculate the address shift from the page size */
2693 chip->page_shift = ffs(mtd->writesize) - 1;
2694 /* Convert chipsize to number of pages per chip -1. */
2695 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2696
2697 chip->bbt_erase_shift = chip->phys_erase_shift =
2698 ffs(mtd->erasesize) - 1;
2699 if (chip->chipsize & 0xffffffff)
2700 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2701 else
2702 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2703
2704 /* Set the bad block position */
2705 chip->badblockpos = mtd->writesize > 512 ?
2706 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2707
2708 /* Get chip options, preserve non chip based options */
2709 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2710 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2711
2712 /*
2713 * Set chip as a default. Board drivers can override it, if necessary
2714 */
2715 chip->options |= NAND_NO_AUTOINCR;
2716
2717 /* Check if chip is a not a samsung device. Do not clear the
2718 * options for chips which are not having an extended id.
2719 */
2720 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2721 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2722
2723 /* Check for AND chips with 4 page planes */
2724 if (chip->options & NAND_4PAGE_ARRAY)
2725 chip->erase_cmd = multi_erase_cmd;
2726 else
2727 chip->erase_cmd = single_erase_cmd;
2728
2729 /* Do not replace user supplied command function ! */
2730 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2731 chip->cmdfunc = nand_command_lp;
2732
2733 printk(KERN_INFO "NAND device: Manufacturer ID:"
2734 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2735 nand_manuf_ids[maf_idx].name, type->name);
2736
2737 return type;
2738 }
2739
2740 /**
2741 * nand_scan_ident - [NAND Interface] Scan for the NAND device
2742 * @mtd: MTD device structure
2743 * @maxchips: Number of chips to scan for
2744 *
2745 * This is the first phase of the normal nand_scan() function. It
2746 * reads the flash ID and sets up MTD fields accordingly.
2747 *
2748 * The mtd->owner field must be set to the module of the caller.
2749 */
2750 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2751 {
2752 int i, busw, nand_maf_id;
2753 struct nand_chip *chip = mtd->priv;
2754 struct nand_flash_dev *type;
2755
2756 /* Get buswidth to select the correct functions */
2757 busw = chip->options & NAND_BUSWIDTH_16;
2758 /* Set the default functions */
2759 nand_set_defaults(chip, busw);
2760
2761 /* Read the flash type */
2762 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2763
2764 if (IS_ERR(type)) {
2765 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
2766 printk(KERN_WARNING "No NAND device found.\n");
2767 chip->select_chip(mtd, -1);
2768 return PTR_ERR(type);
2769 }
2770
2771 /* Check for a chip array */
2772 for (i = 1; i < maxchips; i++) {
2773 chip->select_chip(mtd, i);
2774 /* See comment in nand_get_flash_type for reset */
2775 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2776 /* Send the command for reading device ID */
2777 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2778 /* Read manufacturer and device IDs */
2779 if (nand_maf_id != chip->read_byte(mtd) ||
2780 type->id != chip->read_byte(mtd))
2781 break;
2782 }
2783 if (i > 1)
2784 printk(KERN_INFO "%d NAND chips detected\n", i);
2785
2786 /* Store the number of chips and calc total size for mtd */
2787 chip->numchips = i;
2788 mtd->size = i * chip->chipsize;
2789
2790 return 0;
2791 }
2792
2793
2794 /**
2795 * nand_scan_tail - [NAND Interface] Scan for the NAND device
2796 * @mtd: MTD device structure
2797 *
2798 * This is the second phase of the normal nand_scan() function. It
2799 * fills out all the uninitialized function pointers with the defaults
2800 * and scans for a bad block table if appropriate.
2801 */
2802 int nand_scan_tail(struct mtd_info *mtd)
2803 {
2804 int i;
2805 struct nand_chip *chip = mtd->priv;
2806
2807 if (!(chip->options & NAND_OWN_BUFFERS))
2808 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2809 if (!chip->buffers)
2810 return -ENOMEM;
2811
2812 /* Set the internal oob buffer location, just after the page data */
2813 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2814
2815 /*
2816 * If no default placement scheme is given, select an appropriate one
2817 */
2818 if (!chip->ecc.layout) {
2819 switch (mtd->oobsize) {
2820 case 8:
2821 chip->ecc.layout = &nand_oob_8;
2822 break;
2823 case 16:
2824 chip->ecc.layout = &nand_oob_16;
2825 break;
2826 case 64:
2827 chip->ecc.layout = &nand_oob_64;
2828 break;
2829 case 128:
2830 chip->ecc.layout = &nand_oob_128;
2831 break;
2832 default:
2833 printk(KERN_WARNING "No oob scheme defined for "
2834 "oobsize %d\n", mtd->oobsize);
2835 BUG();
2836 }
2837 }
2838
2839 if (!chip->write_page)
2840 chip->write_page = nand_write_page;
2841
2842 /*
2843 * check ECC mode, default to software if 3byte/512byte hardware ECC is
2844 * selected and we have 256 byte pagesize fallback to software ECC
2845 */
2846
2847 switch (chip->ecc.mode) {
2848 case NAND_ECC_HW_OOB_FIRST:
2849 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2850 if (!chip->ecc.calculate || !chip->ecc.correct ||
2851 !chip->ecc.hwctl) {
2852 printk(KERN_WARNING "No ECC functions supplied; "
2853 "Hardware ECC not possible\n");
2854 BUG();
2855 }
2856 if (!chip->ecc.read_page)
2857 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2858
2859 case NAND_ECC_HW:
2860 /* Use standard hwecc read page function ? */
2861 if (!chip->ecc.read_page)
2862 chip->ecc.read_page = nand_read_page_hwecc;
2863 if (!chip->ecc.write_page)
2864 chip->ecc.write_page = nand_write_page_hwecc;
2865 if (!chip->ecc.read_page_raw)
2866 chip->ecc.read_page_raw = nand_read_page_raw;
2867 if (!chip->ecc.write_page_raw)
2868 chip->ecc.write_page_raw = nand_write_page_raw;
2869 if (!chip->ecc.read_oob)
2870 chip->ecc.read_oob = nand_read_oob_std;
2871 if (!chip->ecc.write_oob)
2872 chip->ecc.write_oob = nand_write_oob_std;
2873
2874 case NAND_ECC_HW_SYNDROME:
2875 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2876 !chip->ecc.hwctl) &&
2877 (!chip->ecc.read_page ||
2878 chip->ecc.read_page == nand_read_page_hwecc ||
2879 !chip->ecc.write_page ||
2880 chip->ecc.write_page == nand_write_page_hwecc)) {
2881 printk(KERN_WARNING "No ECC functions supplied; "
2882 "Hardware ECC not possible\n");
2883 BUG();
2884 }
2885 /* Use standard syndrome read/write page function ? */
2886 if (!chip->ecc.read_page)
2887 chip->ecc.read_page = nand_read_page_syndrome;
2888 if (!chip->ecc.write_page)
2889 chip->ecc.write_page = nand_write_page_syndrome;
2890 if (!chip->ecc.read_page_raw)
2891 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2892 if (!chip->ecc.write_page_raw)
2893 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2894 if (!chip->ecc.read_oob)
2895 chip->ecc.read_oob = nand_read_oob_syndrome;
2896 if (!chip->ecc.write_oob)
2897 chip->ecc.write_oob = nand_write_oob_syndrome;
2898
2899 if (mtd->writesize >= chip->ecc.size)
2900 break;
2901 printk(KERN_WARNING "%d byte HW ECC not possible on "
2902 "%d byte page size, fallback to SW ECC\n",
2903 chip->ecc.size, mtd->writesize);
2904 chip->ecc.mode = NAND_ECC_SOFT;
2905
2906 case NAND_ECC_SOFT:
2907 chip->ecc.calculate = nand_calculate_ecc;
2908 chip->ecc.correct = nand_correct_data;
2909 chip->ecc.read_page = nand_read_page_swecc;
2910 chip->ecc.read_subpage = nand_read_subpage;
2911 chip->ecc.write_page = nand_write_page_swecc;
2912 chip->ecc.read_page_raw = nand_read_page_raw;
2913 chip->ecc.write_page_raw = nand_write_page_raw;
2914 chip->ecc.read_oob = nand_read_oob_std;
2915 chip->ecc.write_oob = nand_write_oob_std;
2916 if (!chip->ecc.size)
2917 chip->ecc.size = 256;
2918 chip->ecc.bytes = 3;
2919 break;
2920
2921 case NAND_ECC_NONE:
2922 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2923 "This is not recommended !!\n");
2924 chip->ecc.read_page = nand_read_page_raw;
2925 chip->ecc.write_page = nand_write_page_raw;
2926 chip->ecc.read_oob = nand_read_oob_std;
2927 chip->ecc.read_page_raw = nand_read_page_raw;
2928 chip->ecc.write_page_raw = nand_write_page_raw;
2929 chip->ecc.write_oob = nand_write_oob_std;
2930 chip->ecc.size = mtd->writesize;
2931 chip->ecc.bytes = 0;
2932 break;
2933
2934 default:
2935 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2936 chip->ecc.mode);
2937 BUG();
2938 }
2939
2940 /*
2941 * The number of bytes available for a client to place data into
2942 * the out of band area
2943 */
2944 chip->ecc.layout->oobavail = 0;
2945 for (i = 0; chip->ecc.layout->oobfree[i].length
2946 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2947 chip->ecc.layout->oobavail +=
2948 chip->ecc.layout->oobfree[i].length;
2949 mtd->oobavail = chip->ecc.layout->oobavail;
2950
2951 /*
2952 * Set the number of read / write steps for one page depending on ECC
2953 * mode
2954 */
2955 chip->ecc.steps = mtd->writesize / chip->ecc.size;
2956 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2957 printk(KERN_WARNING "Invalid ecc parameters\n");
2958 BUG();
2959 }
2960 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2961
2962 /*
2963 * Allow subpage writes up to ecc.steps. Not possible for MLC
2964 * FLASH.
2965 */
2966 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2967 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2968 switch(chip->ecc.steps) {
2969 case 2:
2970 mtd->subpage_sft = 1;
2971 break;
2972 case 4:
2973 case 8:
2974 case 16:
2975 mtd->subpage_sft = 2;
2976 break;
2977 }
2978 }
2979 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2980
2981 /* Initialize state */
2982 chip->state = FL_READY;
2983
2984 /* De-select the device */
2985 chip->select_chip(mtd, -1);
2986
2987 /* Invalidate the pagebuffer reference */
2988 chip->pagebuf = -1;
2989
2990 /* Fill in remaining MTD driver data */
2991 mtd->type = MTD_NANDFLASH;
2992 mtd->flags = MTD_CAP_NANDFLASH;
2993 mtd->erase = nand_erase;
2994 mtd->point = NULL;
2995 mtd->unpoint = NULL;
2996 mtd->read = nand_read;
2997 mtd->write = nand_write;
2998 mtd->panic_write = panic_nand_write;
2999 mtd->read_oob = nand_read_oob;
3000 mtd->write_oob = nand_write_oob;
3001 mtd->sync = nand_sync;
3002 mtd->lock = NULL;
3003 mtd->unlock = NULL;
3004 mtd->suspend = nand_suspend;
3005 mtd->resume = nand_resume;
3006 mtd->block_isbad = nand_block_isbad;
3007 mtd->block_markbad = nand_block_markbad;
3008
3009 /* propagate ecc.layout to mtd_info */
3010 mtd->ecclayout = chip->ecc.layout;
3011
3012 /* Check, if we should skip the bad block table scan */
3013 if (chip->options & NAND_SKIP_BBTSCAN)
3014 return 0;
3015
3016 /* Build bad block table */
3017 return chip->scan_bbt(mtd);
3018 }
3019
3020 /* is_module_text_address() isn't exported, and it's mostly a pointless
3021 test if this is a module _anyway_ -- they'd have to try _really_ hard
3022 to call us from in-kernel code if the core NAND support is modular. */
3023 #ifdef MODULE
3024 #define caller_is_module() (1)
3025 #else
3026 #define caller_is_module() \
3027 is_module_text_address((unsigned long)__builtin_return_address(0))
3028 #endif
3029
3030 /**
3031 * nand_scan - [NAND Interface] Scan for the NAND device
3032 * @mtd: MTD device structure
3033 * @maxchips: Number of chips to scan for
3034 *
3035 * This fills out all the uninitialized function pointers
3036 * with the defaults.
3037 * The flash ID is read and the mtd/chip structures are
3038 * filled with the appropriate values.
3039 * The mtd->owner field must be set to the module of the caller
3040 *
3041 */
3042 int nand_scan(struct mtd_info *mtd, int maxchips)
3043 {
3044 int ret;
3045
3046 /* Many callers got this wrong, so check for it for a while... */
3047 if (!mtd->owner && caller_is_module()) {
3048 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3049 __func__);
3050 BUG();
3051 }
3052
3053 ret = nand_scan_ident(mtd, maxchips);
3054 if (!ret)
3055 ret = nand_scan_tail(mtd);
3056 return ret;
3057 }
3058
3059 /**
3060 * nand_release - [NAND Interface] Free resources held by the NAND device
3061 * @mtd: MTD device structure
3062 */
3063 void nand_release(struct mtd_info *mtd)
3064 {
3065 struct nand_chip *chip = mtd->priv;
3066
3067 #ifdef CONFIG_MTD_PARTITIONS
3068 /* Deregister partitions */
3069 del_mtd_partitions(mtd);
3070 #endif
3071 /* Deregister the device */
3072 del_mtd_device(mtd);
3073
3074 /* Free bad block table memory */
3075 kfree(chip->bbt);
3076 if (!(chip->options & NAND_OWN_BUFFERS))
3077 kfree(chip->buffers);
3078 }
3079
3080 EXPORT_SYMBOL_GPL(nand_scan);
3081 EXPORT_SYMBOL_GPL(nand_scan_ident);
3082 EXPORT_SYMBOL_GPL(nand_scan_tail);
3083 EXPORT_SYMBOL_GPL(nand_release);
3084
3085 static int __init nand_base_init(void)
3086 {
3087 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3088 return 0;
3089 }
3090
3091 static void __exit nand_base_exit(void)
3092 {
3093 led_trigger_unregister_simple(nand_led_trigger);
3094 }
3095
3096 module_init(nand_base_init);
3097 module_exit(nand_base_exit);
3098
3099 MODULE_LICENSE("GPL");
3100 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3101 MODULE_DESCRIPTION("Generic NAND flash driver code");
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