?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux 2.6.33-rc6
[cris-mirror.git] / drivers / watchdog / iTCO_wdt.c
blob4bdb7f1a90772d780037bf2456e3656c1ad6a1ae
1 /*
2 * intel TCO Watchdog Driver
3 *
4 * (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 313056-003, 313057-017: 82801H (ICH8)
30 * document number 316972-004, 316973-012: 82801I (ICH9)
31 * document number 319973-002, 319974-002: 82801J (ICH10)
32 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
33 * document number 320066-003, 320257-008: EP80597 (IICH)
34 * document number TBD : Cougar Point (CPT)
35 */
36
37 /*
38 * Includes, defines, variables, module parameters, ...
39 */
40
41 /* Module and version information */
42 #define DRV_NAME "iTCO_wdt"
43 #define DRV_VERSION "1.05"
44 #define PFX DRV_NAME ": "
45
46 /* Includes */
47 #include <linux/module.h> /* For module specific items */
48 #include <linux/moduleparam.h> /* For new moduleparam's */
49 #include <linux/types.h> /* For standard types (like size_t) */
50 #include <linux/errno.h> /* For the -ENODEV/... values */
51 #include <linux/kernel.h> /* For printk/panic/... */
52 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
53 (WATCHDOG_MINOR) */
54 #include <linux/watchdog.h> /* For the watchdog specific items */
55 #include <linux/init.h> /* For __init/__exit/... */
56 #include <linux/fs.h> /* For file operations */
57 #include <linux/platform_device.h> /* For platform_driver framework */
58 #include <linux/pci.h> /* For pci functions */
59 #include <linux/ioport.h> /* For io-port access */
60 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
61 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
62 #include <linux/io.h> /* For inb/outb/... */
63
64 #include "iTCO_vendor.h"
65
66 /* TCO related info */
67 enum iTCO_chipsets {
68 TCO_ICH = 0, /* ICH */
69 TCO_ICH0, /* ICH0 */
70 TCO_ICH2, /* ICH2 */
71 TCO_ICH2M, /* ICH2-M */
72 TCO_ICH3, /* ICH3-S */
73 TCO_ICH3M, /* ICH3-M */
74 TCO_ICH4, /* ICH4 */
75 TCO_ICH4M, /* ICH4-M */
76 TCO_CICH, /* C-ICH */
77 TCO_ICH5, /* ICH5 & ICH5R */
78 TCO_6300ESB, /* 6300ESB */
79 TCO_ICH6, /* ICH6 & ICH6R */
80 TCO_ICH6M, /* ICH6-M */
81 TCO_ICH6W, /* ICH6W & ICH6RW */
82 TCO_631XESB, /* 631xESB/632xESB */
83 TCO_ICH7, /* ICH7 & ICH7R */
84 TCO_ICH7DH, /* ICH7DH */
85 TCO_ICH7M, /* ICH7-M & ICH7-U */
86 TCO_ICH7MDH, /* ICH7-M DH */
87 TCO_ICH8, /* ICH8 & ICH8R */
88 TCO_ICH8DH, /* ICH8DH */
89 TCO_ICH8DO, /* ICH8DO */
90 TCO_ICH8M, /* ICH8M */
91 TCO_ICH8ME, /* ICH8M-E */
92 TCO_ICH9, /* ICH9 */
93 TCO_ICH9R, /* ICH9R */
94 TCO_ICH9DH, /* ICH9DH */
95 TCO_ICH9DO, /* ICH9DO */
96 TCO_ICH9M, /* ICH9M */
97 TCO_ICH9ME, /* ICH9M-E */
98 TCO_ICH10, /* ICH10 */
99 TCO_ICH10R, /* ICH10R */
100 TCO_ICH10D, /* ICH10D */
101 TCO_ICH10DO, /* ICH10DO */
102 TCO_PCH, /* PCH Desktop Full Featured */
103 TCO_PCHM, /* PCH Mobile Full Featured */
104 TCO_P55, /* P55 */
105 TCO_PM55, /* PM55 */
106 TCO_H55, /* H55 */
107 TCO_QM57, /* QM57 */
108 TCO_H57, /* H57 */
109 TCO_HM55, /* HM55 */
110 TCO_Q57, /* Q57 */
111 TCO_HM57, /* HM57 */
112 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */
113 TCO_QS57, /* QS57 */
114 TCO_3400, /* 3400 */
115 TCO_3420, /* 3420 */
116 TCO_3450, /* 3450 */
117 TCO_EP80579, /* EP80579 */
118 TCO_CPTD, /* CPT Desktop */
119 TCO_CPTM, /* CPT Mobile */
120 };
121
122 static struct {
123 char *name;
124 unsigned int iTCO_version;
125 } iTCO_chipset_info[] __devinitdata = {
126 {"ICH", 1},
127 {"ICH0", 1},
128 {"ICH2", 1},
129 {"ICH2-M", 1},
130 {"ICH3-S", 1},
131 {"ICH3-M", 1},
132 {"ICH4", 1},
133 {"ICH4-M", 1},
134 {"C-ICH", 1},
135 {"ICH5 or ICH5R", 1},
136 {"6300ESB", 1},
137 {"ICH6 or ICH6R", 2},
138 {"ICH6-M", 2},
139 {"ICH6W or ICH6RW", 2},
140 {"631xESB/632xESB", 2},
141 {"ICH7 or ICH7R", 2},
142 {"ICH7DH", 2},
143 {"ICH7-M or ICH7-U", 2},
144 {"ICH7-M DH", 2},
145 {"ICH8 or ICH8R", 2},
146 {"ICH8DH", 2},
147 {"ICH8DO", 2},
148 {"ICH8M", 2},
149 {"ICH8M-E", 2},
150 {"ICH9", 2},
151 {"ICH9R", 2},
152 {"ICH9DH", 2},
153 {"ICH9DO", 2},
154 {"ICH9M", 2},
155 {"ICH9M-E", 2},
156 {"ICH10", 2},
157 {"ICH10R", 2},
158 {"ICH10D", 2},
159 {"ICH10DO", 2},
160 {"PCH Desktop Full Featured", 2},
161 {"PCH Mobile Full Featured", 2},
162 {"P55", 2},
163 {"PM55", 2},
164 {"H55", 2},
165 {"QM57", 2},
166 {"H57", 2},
167 {"HM55", 2},
168 {"Q57", 2},
169 {"HM57", 2},
170 {"PCH Mobile SFF Full Featured", 2},
171 {"QS57", 2},
172 {"3400", 2},
173 {"3420", 2},
174 {"3450", 2},
175 {"EP80579", 2},
176 {"CPT Desktop", 2},
177 {"CPT Mobile", 2},
178 {NULL, 0}
179 };
180
181 #define ITCO_PCI_DEVICE(dev, data) \
182 .vendor = PCI_VENDOR_ID_INTEL, \
183 .device = dev, \
184 .subvendor = PCI_ANY_ID, \
185 .subdevice = PCI_ANY_ID, \
186 .class = 0, \
187 .class_mask = 0, \
188 .driver_data = data
189
190 /*
191 * This data only exists for exporting the supported PCI ids
192 * via MODULE_DEVICE_TABLE. We do not actually register a
193 * pci_driver, because the I/O Controller Hub has also other
194 * functions that probably will be registered by other drivers.
195 */
196 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
197 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)},
198 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)},
199 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)},
200 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)},
201 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)},
202 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)},
203 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)},
204 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)},
205 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)},
206 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)},
207 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)},
208 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)},
209 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)},
210 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)},
211 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)},
212 { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)},
213 { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)},
214 { ITCO_PCI_DEVICE(0x2673, TCO_631XESB)},
215 { ITCO_PCI_DEVICE(0x2674, TCO_631XESB)},
216 { ITCO_PCI_DEVICE(0x2675, TCO_631XESB)},
217 { ITCO_PCI_DEVICE(0x2676, TCO_631XESB)},
218 { ITCO_PCI_DEVICE(0x2677, TCO_631XESB)},
219 { ITCO_PCI_DEVICE(0x2678, TCO_631XESB)},
220 { ITCO_PCI_DEVICE(0x2679, TCO_631XESB)},
221 { ITCO_PCI_DEVICE(0x267a, TCO_631XESB)},
222 { ITCO_PCI_DEVICE(0x267b, TCO_631XESB)},
223 { ITCO_PCI_DEVICE(0x267c, TCO_631XESB)},
224 { ITCO_PCI_DEVICE(0x267d, TCO_631XESB)},
225 { ITCO_PCI_DEVICE(0x267e, TCO_631XESB)},
226 { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)},
227 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)},
228 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30, TCO_ICH7DH)},
229 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)},
230 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)},
231 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)},
232 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)},
233 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)},
234 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)},
235 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)},
236 { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)},
237 { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)},
238 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)},
239 { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)},
240 { ITCO_PCI_DEVICE(0x2919, TCO_ICH9M)},
241 { ITCO_PCI_DEVICE(0x2917, TCO_ICH9ME)},
242 { ITCO_PCI_DEVICE(0x3a18, TCO_ICH10)},
243 { ITCO_PCI_DEVICE(0x3a16, TCO_ICH10R)},
244 { ITCO_PCI_DEVICE(0x3a1a, TCO_ICH10D)},
245 { ITCO_PCI_DEVICE(0x3a14, TCO_ICH10DO)},
246 { ITCO_PCI_DEVICE(0x3b00, TCO_PCH)},
247 { ITCO_PCI_DEVICE(0x3b01, TCO_PCHM)},
248 { ITCO_PCI_DEVICE(0x3b02, TCO_P55)},
249 { ITCO_PCI_DEVICE(0x3b03, TCO_PM55)},
250 { ITCO_PCI_DEVICE(0x3b06, TCO_H55)},
251 { ITCO_PCI_DEVICE(0x3b07, TCO_QM57)},
252 { ITCO_PCI_DEVICE(0x3b08, TCO_H57)},
253 { ITCO_PCI_DEVICE(0x3b09, TCO_HM55)},
254 { ITCO_PCI_DEVICE(0x3b0a, TCO_Q57)},
255 { ITCO_PCI_DEVICE(0x3b0b, TCO_HM57)},
256 { ITCO_PCI_DEVICE(0x3b0d, TCO_PCHMSFF)},
257 { ITCO_PCI_DEVICE(0x3b0f, TCO_QS57)},
258 { ITCO_PCI_DEVICE(0x3b12, TCO_3400)},
259 { ITCO_PCI_DEVICE(0x3b14, TCO_3420)},
260 { ITCO_PCI_DEVICE(0x3b16, TCO_3450)},
261 { ITCO_PCI_DEVICE(0x5031, TCO_EP80579)},
262 { ITCO_PCI_DEVICE(0x1c42, TCO_CPTD)},
263 { ITCO_PCI_DEVICE(0x1c43, TCO_CPTM)},
264 { 0, }, /* End of list */
265 };
266 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
267
268 /* Address definitions for the TCO */
269 /* TCO base address */
270 #define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
271 /* SMI Control and Enable Register */
272 #define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
273
274 #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
275 #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
276 #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
277 #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
278 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
279 #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
280 #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
281 #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
282 #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
283
284 /* internal variables */
285 static unsigned long is_active;
286 static char expect_release;
287 static struct { /* this is private data for the iTCO_wdt device */
288 /* TCO version/generation */
289 unsigned int iTCO_version;
290 /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
291 unsigned long ACPIBASE;
292 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
293 unsigned long __iomem *gcs;
294 /* the lock for io operations */
295 spinlock_t io_lock;
296 /* the PCI-device */
297 struct pci_dev *pdev;
298 } iTCO_wdt_private;
299
300 /* the watchdog platform device */
301 static struct platform_device *iTCO_wdt_platform_device;
302
303 /* module parameters */
304 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
305 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
306 module_param(heartbeat, int, 0);
307 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. "
308 "(2<heartbeat<39 (TCO v1) or 613 (TCO v2), default="
309 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
310
311 static int nowayout = WATCHDOG_NOWAYOUT;
312 module_param(nowayout, int, 0);
313 MODULE_PARM_DESC(nowayout,
314 "Watchdog cannot be stopped once started (default="
315 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
316
317 /*
318 * Some TCO specific functions
319 */
320
321 static inline unsigned int seconds_to_ticks(int seconds)
322 {
323 /* the internal timer is stored as ticks which decrement
324 * every 0.6 seconds */
325 return (seconds * 10) / 6;
326 }
327
328 static void iTCO_wdt_set_NO_REBOOT_bit(void)
329 {
330 u32 val32;
331
332 /* Set the NO_REBOOT bit: this disables reboots */
333 if (iTCO_wdt_private.iTCO_version == 2) {
334 val32 = readl(iTCO_wdt_private.gcs);
335 val32 |= 0x00000020;
336 writel(val32, iTCO_wdt_private.gcs);
337 } else if (iTCO_wdt_private.iTCO_version == 1) {
338 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
339 val32 |= 0x00000002;
340 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
341 }
342 }
343
344 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
345 {
346 int ret = 0;
347 u32 val32;
348
349 /* Unset the NO_REBOOT bit: this enables reboots */
350 if (iTCO_wdt_private.iTCO_version == 2) {
351 val32 = readl(iTCO_wdt_private.gcs);
352 val32 &= 0xffffffdf;
353 writel(val32, iTCO_wdt_private.gcs);
354
355 val32 = readl(iTCO_wdt_private.gcs);
356 if (val32 & 0x00000020)
357 ret = -EIO;
358 } else if (iTCO_wdt_private.iTCO_version == 1) {
359 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
360 val32 &= 0xfffffffd;
361 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
362
363 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
364 if (val32 & 0x00000002)
365 ret = -EIO;
366 }
367
368 return ret; /* returns: 0 = OK, -EIO = Error */
369 }
370
371 static int iTCO_wdt_start(void)
372 {
373 unsigned int val;
374
375 spin_lock(&iTCO_wdt_private.io_lock);
376
377 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
378
379 /* disable chipset's NO_REBOOT bit */
380 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
381 spin_unlock(&iTCO_wdt_private.io_lock);
382 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
383 "reboot disabled by hardware\n");
384 return -EIO;
385 }
386
387 /* Force the timer to its reload value by writing to the TCO_RLD
388 register */
389 if (iTCO_wdt_private.iTCO_version == 2)
390 outw(0x01, TCO_RLD);
391 else if (iTCO_wdt_private.iTCO_version == 1)
392 outb(0x01, TCO_RLD);
393
394 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
395 val = inw(TCO1_CNT);
396 val &= 0xf7ff;
397 outw(val, TCO1_CNT);
398 val = inw(TCO1_CNT);
399 spin_unlock(&iTCO_wdt_private.io_lock);
400
401 if (val & 0x0800)
402 return -1;
403 return 0;
404 }
405
406 static int iTCO_wdt_stop(void)
407 {
408 unsigned int val;
409
410 spin_lock(&iTCO_wdt_private.io_lock);
411
412 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
413
414 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
415 val = inw(TCO1_CNT);
416 val |= 0x0800;
417 outw(val, TCO1_CNT);
418 val = inw(TCO1_CNT);
419
420 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
421 iTCO_wdt_set_NO_REBOOT_bit();
422
423 spin_unlock(&iTCO_wdt_private.io_lock);
424
425 if ((val & 0x0800) == 0)
426 return -1;
427 return 0;
428 }
429
430 static int iTCO_wdt_keepalive(void)
431 {
432 spin_lock(&iTCO_wdt_private.io_lock);
433
434 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
435
436 /* Reload the timer by writing to the TCO Timer Counter register */
437 if (iTCO_wdt_private.iTCO_version == 2)
438 outw(0x01, TCO_RLD);
439 else if (iTCO_wdt_private.iTCO_version == 1)
440 outb(0x01, TCO_RLD);
441
442 spin_unlock(&iTCO_wdt_private.io_lock);
443 return 0;
444 }
445
446 static int iTCO_wdt_set_heartbeat(int t)
447 {
448 unsigned int val16;
449 unsigned char val8;
450 unsigned int tmrval;
451
452 tmrval = seconds_to_ticks(t);
453 /* from the specs: */
454 /* "Values of 0h-3h are ignored and should not be attempted" */
455 if (tmrval < 0x04)
456 return -EINVAL;
457 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
458 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
459 return -EINVAL;
460
461 iTCO_vendor_pre_set_heartbeat(tmrval);
462
463 /* Write new heartbeat to watchdog */
464 if (iTCO_wdt_private.iTCO_version == 2) {
465 spin_lock(&iTCO_wdt_private.io_lock);
466 val16 = inw(TCOv2_TMR);
467 val16 &= 0xfc00;
468 val16 |= tmrval;
469 outw(val16, TCOv2_TMR);
470 val16 = inw(TCOv2_TMR);
471 spin_unlock(&iTCO_wdt_private.io_lock);
472
473 if ((val16 & 0x3ff) != tmrval)
474 return -EINVAL;
475 } else if (iTCO_wdt_private.iTCO_version == 1) {
476 spin_lock(&iTCO_wdt_private.io_lock);
477 val8 = inb(TCOv1_TMR);
478 val8 &= 0xc0;
479 val8 |= (tmrval & 0xff);
480 outb(val8, TCOv1_TMR);
481 val8 = inb(TCOv1_TMR);
482 spin_unlock(&iTCO_wdt_private.io_lock);
483
484 if ((val8 & 0x3f) != tmrval)
485 return -EINVAL;
486 }
487
488 heartbeat = t;
489 return 0;
490 }
491
492 static int iTCO_wdt_get_timeleft(int *time_left)
493 {
494 unsigned int val16;
495 unsigned char val8;
496
497 /* read the TCO Timer */
498 if (iTCO_wdt_private.iTCO_version == 2) {
499 spin_lock(&iTCO_wdt_private.io_lock);
500 val16 = inw(TCO_RLD);
501 val16 &= 0x3ff;
502 spin_unlock(&iTCO_wdt_private.io_lock);
503
504 *time_left = (val16 * 6) / 10;
505 } else if (iTCO_wdt_private.iTCO_version == 1) {
506 spin_lock(&iTCO_wdt_private.io_lock);
507 val8 = inb(TCO_RLD);
508 val8 &= 0x3f;
509 spin_unlock(&iTCO_wdt_private.io_lock);
510
511 *time_left = (val8 * 6) / 10;
512 } else
513 return -EINVAL;
514 return 0;
515 }
516
517 /*
518 * /dev/watchdog handling
519 */
520
521 static int iTCO_wdt_open(struct inode *inode, struct file *file)
522 {
523 /* /dev/watchdog can only be opened once */
524 if (test_and_set_bit(0, &is_active))
525 return -EBUSY;
526
527 /*
528 * Reload and activate timer
529 */
530 iTCO_wdt_start();
531 return nonseekable_open(inode, file);
532 }
533
534 static int iTCO_wdt_release(struct inode *inode, struct file *file)
535 {
536 /*
537 * Shut off the timer.
538 */
539 if (expect_release == 42) {
540 iTCO_wdt_stop();
541 } else {
542 printk(KERN_CRIT PFX
543 "Unexpected close, not stopping watchdog!\n");
544 iTCO_wdt_keepalive();
545 }
546 clear_bit(0, &is_active);
547 expect_release = 0;
548 return 0;
549 }
550
551 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
552 size_t len, loff_t *ppos)
553 {
554 /* See if we got the magic character 'V' and reload the timer */
555 if (len) {
556 if (!nowayout) {
557 size_t i;
558
559 /* note: just in case someone wrote the magic
560 character five months ago... */
561 expect_release = 0;
562
563 /* scan to see whether or not we got the
564 magic character */
565 for (i = 0; i != len; i++) {
566 char c;
567 if (get_user(c, data + i))
568 return -EFAULT;
569 if (c == 'V')
570 expect_release = 42;
571 }
572 }
573
574 /* someone wrote to us, we should reload the timer */
575 iTCO_wdt_keepalive();
576 }
577 return len;
578 }
579
580 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
581 unsigned long arg)
582 {
583 int new_options, retval = -EINVAL;
584 int new_heartbeat;
585 void __user *argp = (void __user *)arg;
586 int __user *p = argp;
587 static struct watchdog_info ident = {
588 .options = WDIOF_SETTIMEOUT |
589 WDIOF_KEEPALIVEPING |
590 WDIOF_MAGICCLOSE,
591 .firmware_version = 0,
592 .identity = DRV_NAME,
593 };
594
595 switch (cmd) {
596 case WDIOC_GETSUPPORT:
597 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
598 case WDIOC_GETSTATUS:
599 case WDIOC_GETBOOTSTATUS:
600 return put_user(0, p);
601
602 case WDIOC_SETOPTIONS:
603 {
604 if (get_user(new_options, p))
605 return -EFAULT;
606
607 if (new_options & WDIOS_DISABLECARD) {
608 iTCO_wdt_stop();
609 retval = 0;
610 }
611 if (new_options & WDIOS_ENABLECARD) {
612 iTCO_wdt_keepalive();
613 iTCO_wdt_start();
614 retval = 0;
615 }
616 return retval;
617 }
618 case WDIOC_KEEPALIVE:
619 iTCO_wdt_keepalive();
620 return 0;
621
622 case WDIOC_SETTIMEOUT:
623 {
624 if (get_user(new_heartbeat, p))
625 return -EFAULT;
626 if (iTCO_wdt_set_heartbeat(new_heartbeat))
627 return -EINVAL;
628 iTCO_wdt_keepalive();
629 /* Fall */
630 }
631 case WDIOC_GETTIMEOUT:
632 return put_user(heartbeat, p);
633 case WDIOC_GETTIMELEFT:
634 {
635 int time_left;
636 if (iTCO_wdt_get_timeleft(&time_left))
637 return -EINVAL;
638 return put_user(time_left, p);
639 }
640 default:
641 return -ENOTTY;
642 }
643 }
644
645 /*
646 * Kernel Interfaces
647 */
648
649 static const struct file_operations iTCO_wdt_fops = {
650 .owner = THIS_MODULE,
651 .llseek = no_llseek,
652 .write = iTCO_wdt_write,
653 .unlocked_ioctl = iTCO_wdt_ioctl,
654 .open = iTCO_wdt_open,
655 .release = iTCO_wdt_release,
656 };
657
658 static struct miscdevice iTCO_wdt_miscdev = {
659 .minor = WATCHDOG_MINOR,
660 .name = "watchdog",
661 .fops = &iTCO_wdt_fops,
662 };
663
664 /*
665 * Init & exit routines
666 */
667
668 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
669 const struct pci_device_id *ent, struct platform_device *dev)
670 {
671 int ret;
672 u32 base_address;
673 unsigned long RCBA;
674 unsigned long val32;
675
676 /*
677 * Find the ACPI/PM base I/O address which is the base
678 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
679 * ACPIBASE is bits [15:7] from 0x40-0x43
680 */
681 pci_read_config_dword(pdev, 0x40, &base_address);
682 base_address &= 0x0000ff80;
683 if (base_address == 0x00000000) {
684 /* Something's wrong here, ACPIBASE has to be set */
685 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
686 pci_dev_put(pdev);
687 return -ENODEV;
688 }
689 iTCO_wdt_private.iTCO_version =
690 iTCO_chipset_info[ent->driver_data].iTCO_version;
691 iTCO_wdt_private.ACPIBASE = base_address;
692 iTCO_wdt_private.pdev = pdev;
693
694 /* Get the Memory-Mapped GCS register, we need it for the
695 NO_REBOOT flag (TCO v2). To get access to it you have to
696 read RCBA from PCI Config space 0xf0 and use it as base.
697 GCS = RCBA + ICH6_GCS(0x3410). */
698 if (iTCO_wdt_private.iTCO_version == 2) {
699 pci_read_config_dword(pdev, 0xf0, &base_address);
700 if ((base_address & 1) == 0) {
701 printk(KERN_ERR PFX "RCBA is disabled by harddware\n");
702 ret = -ENODEV;
703 goto out;
704 }
705 RCBA = base_address & 0xffffc000;
706 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
707 }
708
709 /* Check chipset's NO_REBOOT bit */
710 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
711 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
712 "reboot disabled by hardware\n");
713 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
714 goto out_unmap;
715 }
716
717 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
718 iTCO_wdt_set_NO_REBOOT_bit();
719
720 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
721 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
722 printk(KERN_ERR PFX
723 "I/O address 0x%04lx already in use\n", SMI_EN);
724 ret = -EIO;
725 goto out_unmap;
726 }
727 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
728 val32 = inl(SMI_EN);
729 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
730 outl(val32, SMI_EN);
731
732 /* The TCO I/O registers reside in a 32-byte range pointed to
733 by the TCOBASE value */
734 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
735 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
736 TCOBASE);
737 ret = -EIO;
738 goto unreg_smi_en;
739 }
740
741 printk(KERN_INFO PFX
742 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
743 iTCO_chipset_info[ent->driver_data].name,
744 iTCO_chipset_info[ent->driver_data].iTCO_version,
745 TCOBASE);
746
747 /* Clear out the (probably old) status */
748 outb(8, TCO1_STS); /* Clear the Time Out Status bit */
749 outb(2, TCO2_STS); /* Clear SECOND_TO_STS bit */
750 outb(4, TCO2_STS); /* Clear BOOT_STS bit */
751
752 /* Make sure the watchdog is not running */
753 iTCO_wdt_stop();
754
755 /* Check that the heartbeat value is within it's range;
756 if not reset to the default */
757 if (iTCO_wdt_set_heartbeat(heartbeat)) {
758 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
759 printk(KERN_INFO PFX
760 "heartbeat value must be 2 < heartbeat < 39 (TCO v1) "
761 "or 613 (TCO v2), using %d\n", heartbeat);
762 }
763
764 ret = misc_register(&iTCO_wdt_miscdev);
765 if (ret != 0) {
766 printk(KERN_ERR PFX
767 "cannot register miscdev on minor=%d (err=%d)\n",
768 WATCHDOG_MINOR, ret);
769 goto unreg_region;
770 }
771
772 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
773 heartbeat, nowayout);
774
775 return 0;
776
777 unreg_region:
778 release_region(TCOBASE, 0x20);
779 unreg_smi_en:
780 release_region(SMI_EN, 4);
781 out_unmap:
782 if (iTCO_wdt_private.iTCO_version == 2)
783 iounmap(iTCO_wdt_private.gcs);
784 out:
785 pci_dev_put(iTCO_wdt_private.pdev);
786 iTCO_wdt_private.ACPIBASE = 0;
787 return ret;
788 }
789
790 static void __devexit iTCO_wdt_cleanup(void)
791 {
792 /* Stop the timer before we leave */
793 if (!nowayout)
794 iTCO_wdt_stop();
795
796 /* Deregister */
797 misc_deregister(&iTCO_wdt_miscdev);
798 release_region(TCOBASE, 0x20);
799 release_region(SMI_EN, 4);
800 if (iTCO_wdt_private.iTCO_version == 2)
801 iounmap(iTCO_wdt_private.gcs);
802 pci_dev_put(iTCO_wdt_private.pdev);
803 iTCO_wdt_private.ACPIBASE = 0;
804 }
805
806 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
807 {
808 int found = 0;
809 struct pci_dev *pdev = NULL;
810 const struct pci_device_id *ent;
811
812 spin_lock_init(&iTCO_wdt_private.io_lock);
813
814 for_each_pci_dev(pdev) {
815 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
816 if (ent) {
817 if (!(iTCO_wdt_init(pdev, ent, dev))) {
818 found++;
819 break;
820 }
821 }
822 }
823
824 if (!found) {
825 printk(KERN_INFO PFX "No card detected\n");
826 return -ENODEV;
827 }
828
829 return 0;
830 }
831
832 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
833 {
834 if (iTCO_wdt_private.ACPIBASE)
835 iTCO_wdt_cleanup();
836
837 return 0;
838 }
839
840 static void iTCO_wdt_shutdown(struct platform_device *dev)
841 {
842 iTCO_wdt_stop();
843 }
844
845 #define iTCO_wdt_suspend NULL
846 #define iTCO_wdt_resume NULL
847
848 static struct platform_driver iTCO_wdt_driver = {
849 .probe = iTCO_wdt_probe,
850 .remove = __devexit_p(iTCO_wdt_remove),
851 .shutdown = iTCO_wdt_shutdown,
852 .suspend = iTCO_wdt_suspend,
853 .resume = iTCO_wdt_resume,
854 .driver = {
855 .owner = THIS_MODULE,
856 .name = DRV_NAME,
857 },
858 };
859
860 static int __init iTCO_wdt_init_module(void)
861 {
862 int err;
863
864 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
865 DRV_VERSION);
866
867 err = platform_driver_register(&iTCO_wdt_driver);
868 if (err)
869 return err;
870
871 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
872 -1, NULL, 0);
873 if (IS_ERR(iTCO_wdt_platform_device)) {
874 err = PTR_ERR(iTCO_wdt_platform_device);
875 goto unreg_platform_driver;
876 }
877
878 return 0;
879
880 unreg_platform_driver:
881 platform_driver_unregister(&iTCO_wdt_driver);
882 return err;
883 }
884
885 static void __exit iTCO_wdt_cleanup_module(void)
886 {
887 platform_device_unregister(iTCO_wdt_platform_device);
888 platform_driver_unregister(&iTCO_wdt_driver);
889 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
890 }
891
892 module_init(iTCO_wdt_init_module);
893 module_exit(iTCO_wdt_cleanup_module);
894
895 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
896 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
897 MODULE_VERSION(DRV_VERSION);
898 MODULE_LICENSE("GPL");
899 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
CRIS linux kernel tree