Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt

   1 * Samsung Exynos 5440 PCIe interface
   2
   3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
   4 and thus inherits all the common properties defined in designware-pcie.txt.
   5
   6 Required properties:
   7 - compatible: "samsung,exynos5440-pcie"
   8 - reg: base addresses and lengths of the PCIe controller,
   9 - reg-names : First name should be set to "elbi".
  10         And use the "config" instead of getting the configuration address space
  11         from "ranges".
  12         NOTE: When using the "config" property, reg-names must be set.
  13 - interrupts: A list of interrupt outputs for level interrupt,
  14         pulse interrupt, special interrupt.
  15 - phys: From PHY binding. Phandle for the generic PHY.
  16         Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
  17
  18 For other common properties, refer to
  19         Documentation/devicetree/bindings/pci/designware-pcie.txt
  20
  21 Example:
  22
  23 SoC-specific DT Entry (with using PHY framework):
  24
  25         pcie_phy0: pcie-phy@270000 {
  26                 ...
  27                 reg = <0x270000 0x1000>, <0x271000 0x40>;
  28                 reg-names = "phy", "block";
  29                 ...
  30         };
  31
  32         pcie@290000 {
  33                 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
  34                 reg = <0x290000 0x1000>, <0x40000000 0x1000>;
  35                 reg-names = "elbi", "config";
  36                 clocks = <&clock 28>, <&clock 27>;
  37                 clock-names = "pcie", "pcie_bus";
  38                 #address-cells = <3>;
  39                 #size-cells = <2>;
  40                 device_type = "pci";
  41                 phys = <&pcie_phy0>;
  42                 ranges = <0x81000000 0 0          0x60001000 0 0x00010000
  43                           0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
  44                 #interrupt-cells = <1>;
  45                 interrupt-map-mask = <0 0 0 0>;
  46                 interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
  47                 num-lanes = <4>;
  48         };
  49
  50 Board-specific DT Entry:
  51
  52         pcie@290000 {
  53                 reset-gpio = <&pin_ctrl 5 0>;
  54         };
  55
  56         pcie@2a0000 {
  57                 reset-gpio = <&pin_ctrl 22 0>;
  58         };