Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt

   1 MediaTek display PWM controller
   2
   3 Required properties:
   4  - compatible: should be "mediatek,<name>-disp-pwm":
   5    - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
   6    - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
   7    - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
   8  - reg: physical base address and length of the controller's registers.
   9  - #pwm-cells: must be 2. See pwm.txt in this directory for a description of
  10    the cell format.
  11  - clocks: phandle and clock specifier of the PWM reference clock.
  12  - clock-names: must contain the following:
  13    - "main": clock used to generate PWM signals.
  14    - "mm": sync signals from the modules of mmsys.
  15  - pinctrl-names: Must contain a "default" entry.
  16  - pinctrl-0: One property must exist for each entry in pinctrl-names.
  17    See pinctrl/pinctrl-bindings.txt for details of the property values.
  18
  19 Example:
  20         pwm0: pwm@1401e000 {
  21                 compatible = "mediatek,mt8173-disp-pwm",
  22                              "mediatek,mt6595-disp-pwm";
  23                 reg = <0 0x1401e000 0 0x1000>;
  24                 #pwm-cells = <2>;
  25                 clocks = <&mmsys CLK_MM_DISP_PWM026M>,
  26                          <&mmsys CLK_MM_DISP_PWM0MM>;
  27                 clock-names = "main", "mm";
  28                 pinctrl-names = "default";
  29                 pinctrl-0 = <&disp_pwm0_pins>;
  30         };
  31
  32         backlight_lcd: backlight_lcd {
  33                 compatible = "pwm-backlight";
  34                 pwms = <&pwm0 0 1000000>;
  35                 brightness-levels = <
  36                           0  16  32  48  64  80  96 112
  37                         128 144 160 176 192 208 224 240
  38                         255
  39                 >;
  40                 default-brightness-level = <9>;
  41                 power-supply = <&mt6397_vio18_reg>;
  42                 enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
  43         };