arch/arm/mach-integrator/integrator_ap.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_ap.c
   3  *
   4  *  Copyright (C) 2000-2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include <linux/types.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/list.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/slab.h>
  26 #include <linux/string.h>
  27 #include <linux/sysdev.h>
  28 #include <linux/amba/bus.h>
  29 #include <linux/amba/kmi.h>
  30 #include <linux/clocksource.h>
  31 #include <linux/clockchips.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/io.h>
  34
  35 #include <mach/hardware.h>
  36 #include <mach/platform.h>
  37 #include <asm/hardware/arm_timer.h>
  38 #include <asm/irq.h>
  39 #include <asm/setup.h>
  40 #include <asm/param.h>          /* HZ */
  41 #include <asm/mach-types.h>
  42
  43 #include <mach/lm.h>
  44
  45 #include <asm/mach/arch.h>
  46 #include <asm/mach/flash.h>
  47 #include <asm/mach/irq.h>
  48 #include <asm/mach/map.h>
  49 #include <asm/mach/time.h>
  50
  51 /*
  52  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  53  * is the (PA >> 12).
  54  *
  55  * Setup a VA for the Integrator interrupt controller (for header #0,
  56  * just for now).
  57  */
  58 #define VA_IC_BASE      IO_ADDRESS(INTEGRATOR_IC_BASE)
  59 #define VA_SC_BASE      IO_ADDRESS(INTEGRATOR_SC_BASE)
  60 #define VA_EBI_BASE     IO_ADDRESS(INTEGRATOR_EBI_BASE)
  61 #define VA_CMIC_BASE    IO_ADDRESS(INTEGRATOR_HDR_IC)
  62
  63 /*
  64  * Logical      Physical
  65  * e8000000     40000000        PCI memory              PHYS_PCI_MEM_BASE       (max 512M)
  66  * ec000000     61000000        PCI config space        PHYS_PCI_CONFIG_BASE    (max 16M)
  67  * ed000000     62000000        PCI V3 regs             PHYS_PCI_V3_BASE        (max 64k)
  68  * ee000000     60000000        PCI IO                  PHYS_PCI_IO_BASE        (max 16M)
  69  * ef000000                     Cache flush
  70  * f1000000     10000000        Core module registers
  71  * f1100000     11000000        System controller registers
  72  * f1200000     12000000        EBI registers
  73  * f1300000     13000000        Counter/Timer
  74  * f1400000     14000000        Interrupt controller
  75  * f1600000     16000000        UART 0
  76  * f1700000     17000000        UART 1
  77  * f1a00000     1a000000        Debug LEDs
  78  * f1b00000     1b000000        GPIO
  79  */
  80
  81 static struct map_desc ap_io_desc[] __initdata = {
  82         {
  83                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  84                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  85                 .length         = SZ_4K,
  86                 .type           = MT_DEVICE
  87         }, {
  88                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  89                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  90                 .length         = SZ_4K,
  91                 .type           = MT_DEVICE
  92         }, {
  93                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
  94                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
  95                 .length         = SZ_4K,
  96                 .type           = MT_DEVICE
  97         }, {
  98                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
  99                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 100                 .length         = SZ_4K,
 101                 .type           = MT_DEVICE
 102         }, {
 103                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 104                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 105                 .length         = SZ_4K,
 106                 .type           = MT_DEVICE
 107         }, {
 108                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 109                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 110                 .length         = SZ_4K,
 111                 .type           = MT_DEVICE
 112         }, {
 113                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 114                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 115                 .length         = SZ_4K,
 116                 .type           = MT_DEVICE
 117         }, {
 118                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 119                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 120                 .length         = SZ_4K,
 121                 .type           = MT_DEVICE
 122         }, {
 123                 .virtual        = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
 124                 .pfn            = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
 125                 .length         = SZ_4K,
 126                 .type           = MT_DEVICE
 127         }, {
 128                 .virtual        = PCI_MEMORY_VADDR,
 129                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
 130                 .length         = SZ_16M,
 131                 .type           = MT_DEVICE
 132         }, {
 133                 .virtual        = PCI_CONFIG_VADDR,
 134                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
 135                 .length         = SZ_16M,
 136                 .type           = MT_DEVICE
 137         }, {
 138                 .virtual        = PCI_V3_VADDR,
 139                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
 140                 .length         = SZ_64K,
 141                 .type           = MT_DEVICE
 142         }, {
 143                 .virtual        = PCI_IO_VADDR,
 144                 .pfn            = __phys_to_pfn(PHYS_PCI_IO_BASE),
 145                 .length         = SZ_64K,
 146                 .type           = MT_DEVICE
 147         }
 148 };
 149
 150 static void __init ap_map_io(void)
 151 {
 152         iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
 153 }
 154
 155 #define INTEGRATOR_SC_VALID_INT 0x003fffff
 156
 157 static void sc_mask_irq(unsigned int irq)
 158 {
 159         writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 160 }
 161
 162 static void sc_unmask_irq(unsigned int irq)
 163 {
 164         writel(1 << irq, VA_IC_BASE + IRQ_ENABLE_SET);
 165 }
 166
 167 static struct irq_chip sc_chip = {
 168         .name   = "SC",
 169         .ack    = sc_mask_irq,
 170         .mask   = sc_mask_irq,
 171         .unmask = sc_unmask_irq,
 172 };
 173
 174 static void __init ap_init_irq(void)
 175 {
 176         unsigned int i;
 177
 178         /* Disable all interrupts initially. */
 179         /* Do the core module ones */
 180         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 181
 182         /* do the header card stuff next */
 183         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 184         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 185
 186         for (i = 0; i < NR_IRQS; i++) {
 187                 if (((1 << i) & INTEGRATOR_SC_VALID_INT) != 0) {
 188                         set_irq_chip(i, &sc_chip);
 189                         set_irq_handler(i, handle_level_irq);
 190                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 191                 }
 192         }
 193 }
 194
 195 #ifdef CONFIG_PM
 196 static unsigned long ic_irq_enable;
 197
 198 static int irq_suspend(struct sys_device *dev, pm_message_t state)
 199 {
 200         ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
 201         return 0;
 202 }
 203
 204 static int irq_resume(struct sys_device *dev)
 205 {
 206         /* disable all irq sources */
 207         writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
 208         writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
 209         writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
 210
 211         writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
 212         return 0;
 213 }
 214 #else
 215 #define irq_suspend NULL
 216 #define irq_resume NULL
 217 #endif
 218
 219 static struct sysdev_class irq_class = {
 220         .name           = "irq",
 221         .suspend        = irq_suspend,
 222         .resume         = irq_resume,
 223 };
 224
 225 static struct sys_device irq_device = {
 226         .id     = 0,
 227         .cls    = &irq_class,
 228 };
 229
 230 static int __init irq_init_sysfs(void)
 231 {
 232         int ret = sysdev_class_register(&irq_class);
 233         if (ret == 0)
 234                 ret = sysdev_register(&irq_device);
 235         return ret;
 236 }
 237
 238 device_initcall(irq_init_sysfs);
 239
 240 /*
 241  * Flash handling.
 242  */
 243 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
 244 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
 245 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
 246 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
 247
 248 static int ap_flash_init(void)
 249 {
 250         u32 tmp;
 251
 252         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 253
 254         tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
 255         writel(tmp, EBI_CSR1);
 256
 257         if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
 258                 writel(0xa05f, EBI_LOCK);
 259                 writel(tmp, EBI_CSR1);
 260                 writel(0, EBI_LOCK);
 261         }
 262         return 0;
 263 }
 264
 265 static void ap_flash_exit(void)
 266 {
 267         u32 tmp;
 268
 269         writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
 270
 271         tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
 272         writel(tmp, EBI_CSR1);
 273
 274         if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
 275                 writel(0xa05f, EBI_LOCK);
 276                 writel(tmp, EBI_CSR1);
 277                 writel(0, EBI_LOCK);
 278         }
 279 }
 280
 281 static void ap_flash_set_vpp(int on)
 282 {
 283         unsigned long reg = on ? SC_CTRLS : SC_CTRLC;
 284
 285         writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
 286 }
 287
 288 static struct flash_platform_data ap_flash_data = {
 289         .map_name       = "cfi_probe",
 290         .width          = 4,
 291         .init           = ap_flash_init,
 292         .exit           = ap_flash_exit,
 293         .set_vpp        = ap_flash_set_vpp,
 294 };
 295
 296 static struct resource cfi_flash_resource = {
 297         .start          = INTEGRATOR_FLASH_BASE,
 298         .end            = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
 299         .flags          = IORESOURCE_MEM,
 300 };
 301
 302 static struct platform_device cfi_flash_device = {
 303         .name           = "armflash",
 304         .id             = 0,
 305         .dev            = {
 306                 .platform_data  = &ap_flash_data,
 307         },
 308         .num_resources  = 1,
 309         .resource       = &cfi_flash_resource,
 310 };
 311
 312 static void __init ap_init(void)
 313 {
 314         unsigned long sc_dec;
 315         int i;
 316
 317         platform_device_register(&cfi_flash_device);
 318
 319         sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
 320         for (i = 0; i < 4; i++) {
 321                 struct lm_device *lmdev;
 322
 323                 if ((sc_dec & (16 << i)) == 0)
 324                         continue;
 325
 326                 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
 327                 if (!lmdev)
 328                         continue;
 329
 330                 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
 331                 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
 332                 lmdev->resource.flags = IORESOURCE_MEM;
 333                 lmdev->irq = IRQ_AP_EXPINT0 + i;
 334                 lmdev->id = i;
 335
 336                 lm_device_register(lmdev);
 337         }
 338 }
 339
 340 /*
 341  * Where is the timer (VA)?
 342  */
 343 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
 344 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
 345 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
 346
 347 /*
 348  * How long is the timer interval?
 349  */
 350 #define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
 351 #if TIMER_INTERVAL >= 0x100000
 352 #define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
 353 #elif TIMER_INTERVAL >= 0x10000
 354 #define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
 355 #else
 356 #define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
 357 #endif
 358
 359 static unsigned long timer_reload;
 360
 361 static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
 362
 363 static cycle_t timersp_read(struct clocksource *cs)
 364 {
 365         return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
 366 }
 367
 368 static struct clocksource clocksource_timersp = {
 369         .name           = "timer2",
 370         .rating         = 200,
 371         .read           = timersp_read,
 372         .mask           = CLOCKSOURCE_MASK(16),
 373         .shift          = 16,
 374         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 375 };
 376
 377 static void integrator_clocksource_init(u32 khz)
 378 {
 379         struct clocksource *cs = &clocksource_timersp;
 380         void __iomem *base = clksrc_base;
 381         u32 ctrl = TIMER_CTRL_ENABLE;
 382
 383         if (khz >= 1500) {
 384                 khz /= 16;
 385                 ctrl = TIMER_CTRL_DIV16;
 386         }
 387
 388         writel(ctrl, base + TIMER_CTRL);
 389         writel(0xffff, base + TIMER_LOAD);
 390
 391         cs->mult = clocksource_khz2mult(khz, cs->shift);
 392         clocksource_register(cs);
 393 }
 394
 395 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
 396
 397 /*
 398  * IRQ handler for the timer
 399  */
 400 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
 401 {
 402         struct clock_event_device *evt = dev_id;
 403
 404         /* clear the interrupt */
 405         writel(1, clkevt_base + TIMER_INTCLR);
 406
 407         evt->event_handler(evt);
 408
 409         return IRQ_HANDLED;
 410 }
 411
 412 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
 413 {
 414         u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
 415
 416         BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
 417
 418         if (mode == CLOCK_EVT_MODE_PERIODIC) {
 419                 writel(ctrl, clkevt_base + TIMER_CTRL);
 420                 writel(timer_reload, clkevt_base + TIMER_LOAD);
 421                 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
 422         }
 423
 424         writel(ctrl, clkevt_base + TIMER_CTRL);
 425 }
 426
 427 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
 428 {
 429         unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 430
 431         writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 432         writel(next, clkevt_base + TIMER_LOAD);
 433         writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 434
 435         return 0;
 436 }
 437
 438 static struct clock_event_device integrator_clockevent = {
 439         .name           = "timer1",
 440         .shift          = 34,
 441         .features       = CLOCK_EVT_FEAT_PERIODIC,
 442         .set_mode       = clkevt_set_mode,
 443         .set_next_event = clkevt_set_next_event,
 444         .rating         = 300,
 445         .cpumask        = cpu_all_mask,
 446 };
 447
 448 static struct irqaction integrator_timer_irq = {
 449         .name           = "timer",
 450         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 451         .handler        = integrator_timer_interrupt,
 452         .dev_id         = &integrator_clockevent,
 453 };
 454
 455 static void integrator_clockevent_init(u32 khz)
 456 {
 457         struct clock_event_device *evt = &integrator_clockevent;
 458         unsigned int ctrl = 0;
 459
 460         if (khz * 1000 > 0x100000 * HZ) {
 461                 khz /= 256;
 462                 ctrl |= TIMER_CTRL_DIV256;
 463         } else if (khz * 1000 > 0x10000 * HZ) {
 464                 khz /= 16;
 465                 ctrl |= TIMER_CTRL_DIV16;
 466         }
 467
 468         timer_reload = khz * 1000 / HZ;
 469         writel(ctrl, clkevt_base + TIMER_CTRL);
 470
 471         evt->irq = IRQ_TIMERINT1;
 472         evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
 473         evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
 474         evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
 475
 476         setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
 477         clockevents_register_device(evt);
 478 }
 479
 480 /*
 481  * Set up timer(s).
 482  */
 483 static void __init ap_init_timer(void)
 484 {
 485         u32 khz = TICKS_PER_uSEC * 1000;
 486
 487         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 488         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 489         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 490
 491         integrator_clocksource_init(khz);
 492         integrator_clockevent_init(khz);
 493 }
 494
 495 static struct sys_timer ap_timer = {
 496         .init           = ap_init_timer,
 497 };
 498
 499 MACHINE_START(INTEGRATOR, "ARM-Integrator")
 500         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 501         .phys_io        = 0x16000000,
 502         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
 503         .boot_params    = 0x00000100,
 504         .map_io         = ap_map_io,
 505         .init_irq       = ap_init_irq,
 506         .timer          = &ap_timer,
 507         .init_machine   = ap_init,
 508 MACHINE_END