| blob | 72507c630ceb563e9242145722b542b52731a7b3 |
1 /*
2 * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020.
25 *
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
39 /*
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
43 *
44 * This value should be chosen such that we choose the cheapest
45 * alternative.
46 */
47 #define MAX_AREA_SIZE 32768
49 /*
50 * The size of one data cache line.
51 */
52 #define CACHE_DLINESIZE 32
54 /*
55 * The number of data cache segments.
56 */
57 #define CACHE_DSEGMENTS 16
59 /*
60 * The number of lines in a cache segment.
61 */
62 #define CACHE_DENTRIES 64
64 /*
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintainence instructions.
68 */
69 #define CACHE_DLIMIT 32768
71 .text
72 /*
73 * cpu_arm1020_proc_init()
74 */
75 ENTRY(cpu_arm1020_proc_init)
76 mov pc, lr
78 /*
79 * cpu_arm1020_proc_fin()
80 */
81 ENTRY(cpu_arm1020_proc_fin)
82 stmfd sp!, {lr}
83 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
84 msr cpsr_c, ip
85 bl arm1020_flush_kern_cache_all
86 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
87 bic r0, r0, #0x1000 @ ...i............
88 bic r0, r0, #0x000e @ ............wca.
89 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 ldmfd sp!, {pc}
92 /*
93 * cpu_arm1020_reset(loc)
94 *
95 * Perform a soft reset of the system. Put the CPU into the
96 * same state as it would be if it had been reset, and branch
97 * to what would be the reset vector.
98 *
99 * loc: location to jump to for soft reset
100 */
101 .align 5
102 ENTRY(cpu_arm1020_reset)
103 mov ip, #0
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
106 #ifdef CONFIG_MMU
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 #endif
109 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
110 bic ip, ip, #0x000f @ ............wcam
111 bic ip, ip, #0x1100 @ ...i...s........
112 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
113 mov pc, r0
115 /*
116 * cpu_arm1020_do_idle()
117 */
118 .align 5
119 ENTRY(cpu_arm1020_do_idle)
120 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
121 mov pc, lr
123 /* ================================= CACHE ================================ */
125 .align 5
126 /*
127 * flush_user_cache_all()
128 *
129 * Invalidate all cache entries in a particular address
130 * space.
131 */
132 ENTRY(arm1020_flush_user_cache_all)
133 /* FALLTHROUGH */
134 /*
135 * flush_kern_cache_all()
136 *
137 * Clean and invalidate the entire cache.
138 */
139 ENTRY(arm1020_flush_kern_cache_all)
140 mov r2, #VM_EXEC
141 mov ip, #0
142 __flush_whole_cache:
143 #ifndef CONFIG_CPU_DCACHE_DISABLE
144 mcr p15, 0, ip, c7, c10, 4 @ drain WB
145 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
146 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
148 mcr p15, 0, ip, c7, c10, 4 @ drain WB
149 subs r3, r3, #1 << 26
150 bcs 2b @ entries 63 to 0
151 subs r1, r1, #1 << 5
152 bcs 1b @ segments 15 to 0
153 #endif
154 tst r2, #VM_EXEC
155 #ifndef CONFIG_CPU_ICACHE_DISABLE
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
157 #endif
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
159 mov pc, lr
161 /*
162 * flush_user_cache_range(start, end, flags)
163 *
164 * Invalidate a range of cache entries in the specified
165 * address space.
166 *
167 * - start - start address (inclusive)
168 * - end - end address (exclusive)
169 * - flags - vm_flags for this space
170 */
171 ENTRY(arm1020_flush_user_cache_range)
172 mov ip, #0
173 sub r3, r1, r0 @ calculate total size
174 cmp r3, #CACHE_DLIMIT
175 bhs __flush_whole_cache
177 #ifndef CONFIG_CPU_DCACHE_DISABLE
178 mcr p15, 0, ip, c7, c10, 4
179 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 mcr p15, 0, ip, c7, c10, 4 @ drain WB
181 add r0, r0, #CACHE_DLINESIZE
182 cmp r0, r1
183 blo 1b
184 #endif
185 tst r2, #VM_EXEC
186 #ifndef CONFIG_CPU_ICACHE_DISABLE
187 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
188 #endif
189 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
190 mov pc, lr
192 /*
193 * coherent_kern_range(start, end)
194 *
195 * Ensure coherency between the Icache and the Dcache in the
196 * region described by start. If you have non-snooping
197 * Harvard caches, you need to implement this function.
198 *
199 * - start - virtual start address
200 * - end - virtual end address
201 */
202 ENTRY(arm1020_coherent_kern_range)
203 /* FALLTRHOUGH */
205 /*
206 * coherent_user_range(start, end)
207 *
208 * Ensure coherency between the Icache and the Dcache in the
209 * region described by start. If you have non-snooping
210 * Harvard caches, you need to implement this function.
211 *
212 * - start - virtual start address
213 * - end - virtual end address
214 */
215 ENTRY(arm1020_coherent_user_range)
216 mov ip, #0
217 bic r0, r0, #CACHE_DLINESIZE - 1
218 mcr p15, 0, ip, c7, c10, 4
219 1:
220 #ifndef CONFIG_CPU_DCACHE_DISABLE
221 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
222 mcr p15, 0, ip, c7, c10, 4 @ drain WB
223 #endif
224 #ifndef CONFIG_CPU_ICACHE_DISABLE
225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
226 #endif
227 add r0, r0, #CACHE_DLINESIZE
228 cmp r0, r1
229 blo 1b
230 mcr p15, 0, ip, c7, c10, 4 @ drain WB
231 mov pc, lr
233 /*
234 * flush_kern_dcache_area(void *addr, size_t size)
235 *
236 * Ensure no D cache aliasing occurs, either with itself or
237 * the I cache
238 *
239 * - addr - kernel address
240 * - size - region size
241 */
242 ENTRY(arm1020_flush_kern_dcache_area)
243 mov ip, #0
244 #ifndef CONFIG_CPU_DCACHE_DISABLE
245 add r1, r0, r1
246 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
247 mcr p15, 0, ip, c7, c10, 4 @ drain WB
248 add r0, r0, #CACHE_DLINESIZE
249 cmp r0, r1
250 blo 1b
251 #endif
252 mcr p15, 0, ip, c7, c10, 4 @ drain WB
253 mov pc, lr
255 /*
256 * dma_inv_range(start, end)
257 *
258 * Invalidate (discard) the specified virtual address range.
259 * May not write back any entries. If 'start' or 'end'
260 * are not cache line aligned, those lines must be written
261 * back.
262 *
263 * - start - virtual start address
264 * - end - virtual end address
265 *
266 * (same as v4wb)
267 */
268 arm1020_dma_inv_range:
269 mov ip, #0
270 #ifndef CONFIG_CPU_DCACHE_DISABLE
271 tst r0, #CACHE_DLINESIZE - 1
272 bic r0, r0, #CACHE_DLINESIZE - 1
273 mcrne p15, 0, ip, c7, c10, 4
274 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
275 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
276 tst r1, #CACHE_DLINESIZE - 1
277 mcrne p15, 0, ip, c7, c10, 4
278 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
279 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
280 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
281 add r0, r0, #CACHE_DLINESIZE
282 cmp r0, r1
283 blo 1b
284 #endif
285 mcr p15, 0, ip, c7, c10, 4 @ drain WB
286 mov pc, lr
288 /*
289 * dma_clean_range(start, end)
290 *
291 * Clean the specified virtual address range.
292 *
293 * - start - virtual start address
294 * - end - virtual end address
295 *
296 * (same as v4wb)
297 */
298 arm1020_dma_clean_range:
299 mov ip, #0
300 #ifndef CONFIG_CPU_DCACHE_DISABLE
301 bic r0, r0, #CACHE_DLINESIZE - 1
302 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
303 mcr p15, 0, ip, c7, c10, 4 @ drain WB
304 add r0, r0, #CACHE_DLINESIZE
305 cmp r0, r1
306 blo 1b
307 #endif
308 mcr p15, 0, ip, c7, c10, 4 @ drain WB
309 mov pc, lr
311 /*
312 * dma_flush_range(start, end)
313 *
314 * Clean and invalidate the specified virtual address range.
315 *
316 * - start - virtual start address
317 * - end - virtual end address
318 */
319 ENTRY(arm1020_dma_flush_range)
320 mov ip, #0
321 #ifndef CONFIG_CPU_DCACHE_DISABLE
322 bic r0, r0, #CACHE_DLINESIZE - 1
323 mcr p15, 0, ip, c7, c10, 4
324 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
325 mcr p15, 0, ip, c7, c10, 4 @ drain WB
326 add r0, r0, #CACHE_DLINESIZE
327 cmp r0, r1
328 blo 1b
329 #endif
330 mcr p15, 0, ip, c7, c10, 4 @ drain WB
331 mov pc, lr
333 /*
334 * dma_map_area(start, size, dir)
335 * - start - kernel virtual start address
336 * - size - size of region
337 * - dir - DMA direction
338 */
339 ENTRY(arm1020_dma_map_area)
340 add r1, r1, r0
341 cmp r2, #DMA_TO_DEVICE
342 beq arm1020_dma_clean_range
343 bcs arm1020_dma_inv_range
344 b arm1020_dma_flush_range
345 ENDPROC(arm1020_dma_map_area)
347 /*
348 * dma_unmap_area(start, size, dir)
349 * - start - kernel virtual start address
350 * - size - size of region
351 * - dir - DMA direction
352 */
353 ENTRY(arm1020_dma_unmap_area)
354 mov pc, lr
355 ENDPROC(arm1020_dma_unmap_area)
357 ENTRY(arm1020_cache_fns)
358 .long arm1020_flush_kern_cache_all
359 .long arm1020_flush_user_cache_all
360 .long arm1020_flush_user_cache_range
361 .long arm1020_coherent_kern_range
362 .long arm1020_coherent_user_range
363 .long arm1020_flush_kern_dcache_area
364 .long arm1020_dma_map_area
365 .long arm1020_dma_unmap_area
366 .long arm1020_dma_flush_range
368 .align 5
369 ENTRY(cpu_arm1020_dcache_clean_area)
370 #ifndef CONFIG_CPU_DCACHE_DISABLE
371 mov ip, #0
372 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
373 mcr p15, 0, ip, c7, c10, 4 @ drain WB
374 add r0, r0, #CACHE_DLINESIZE
375 subs r1, r1, #CACHE_DLINESIZE
376 bhi 1b
377 #endif
378 mov pc, lr
380 /* =============================== PageTable ============================== */
382 /*
383 * cpu_arm1020_switch_mm(pgd)
384 *
385 * Set the translation base pointer to be as described by pgd.
386 *
387 * pgd: new page tables
388 */
389 .align 5
390 ENTRY(cpu_arm1020_switch_mm)
391 #ifdef CONFIG_MMU
392 #ifndef CONFIG_CPU_DCACHE_DISABLE
393 mcr p15, 0, r3, c7, c10, 4
394 mov r1, #0xF @ 16 segments
395 1: mov r3, #0x3F @ 64 entries
396 2: mov ip, r3, LSL #26 @ shift up entry
397 orr ip, ip, r1, LSL #5 @ shift in/up index
398 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
399 mov ip, #0
400 mcr p15, 0, ip, c7, c10, 4
401 subs r3, r3, #1
402 cmp r3, #0
403 bge 2b @ entries 3F to 0
404 subs r1, r1, #1
405 cmp r1, #0
406 bge 1b @ segments 15 to 0
408 #endif
409 mov r1, #0
410 #ifndef CONFIG_CPU_ICACHE_DISABLE
411 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
412 #endif
413 mcr p15, 0, r1, c7, c10, 4 @ drain WB
414 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
415 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
416 #endif /* CONFIG_MMU */
417 mov pc, lr
419 /*
420 * cpu_arm1020_set_pte(ptep, pte)
421 *
422 * Set a PTE and flush it out
423 */
424 .align 5
425 ENTRY(cpu_arm1020_set_pte_ext)
426 #ifdef CONFIG_MMU
427 armv3_set_pte_ext
428 mov r0, r0
429 #ifndef CONFIG_CPU_DCACHE_DISABLE
430 mcr p15, 0, r0, c7, c10, 4
431 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
432 #endif
433 mcr p15, 0, r0, c7, c10, 4 @ drain WB
434 #endif /* CONFIG_MMU */
435 mov pc, lr
437 __INIT
439 .type __arm1020_setup, #function
440 __arm1020_setup:
441 mov r0, #0
442 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
443 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
444 #ifdef CONFIG_MMU
445 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
446 #endif
448 adr r5, arm1020_crval
449 ldmia r5, {r5, r6}
450 mrc p15, 0, r0, c1, c0 @ get control register v4
451 bic r0, r0, r5
452 orr r0, r0, r6
453 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
454 orr r0, r0, #0x4000 @ .R.. .... .... ....
455 #endif
456 mov pc, lr
457 .size __arm1020_setup, . - __arm1020_setup
459 /*
460 * R
461 * .RVI ZFRS BLDP WCAM
462 * .011 1001 ..11 0101
463 */
464 .type arm1020_crval, #object
465 arm1020_crval:
466 crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
468 __INITDATA
470 /*
471 * Purpose : Function pointers used to access above functions - all calls
472 * come through these
473 */
474 .type arm1020_processor_functions, #object
475 arm1020_processor_functions:
476 .word v4t_early_abort
477 .word legacy_pabort
478 .word cpu_arm1020_proc_init
479 .word cpu_arm1020_proc_fin
480 .word cpu_arm1020_reset
481 .word cpu_arm1020_do_idle
482 .word cpu_arm1020_dcache_clean_area
483 .word cpu_arm1020_switch_mm
484 .word cpu_arm1020_set_pte_ext
485 .size arm1020_processor_functions, . - arm1020_processor_functions
487 .section ".rodata"
489 .type cpu_arch_name, #object
490 cpu_arch_name:
491 .asciz "armv5t"
492 .size cpu_arch_name, . - cpu_arch_name
494 .type cpu_elf_name, #object
495 cpu_elf_name:
496 .asciz "v5"
497 .size cpu_elf_name, . - cpu_elf_name
499 .type cpu_arm1020_name, #object
500 cpu_arm1020_name:
501 .ascii "ARM1020"
502 #ifndef CONFIG_CPU_ICACHE_DISABLE
503 .ascii "i"
504 #endif
505 #ifndef CONFIG_CPU_DCACHE_DISABLE
506 .ascii "d"
507 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
508 .ascii "(wt)"
509 #else
510 .ascii "(wb)"
511 #endif
512 #endif
513 #ifndef CONFIG_CPU_BPREDICT_DISABLE
514 .ascii "B"
515 #endif
516 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
517 .ascii "RR"
518 #endif
519 .ascii "\0"
520 .size cpu_arm1020_name, . - cpu_arm1020_name
522 .align
524 .section ".proc.info.init", #alloc, #execinstr
526 .type __arm1020_proc_info,#object
527 __arm1020_proc_info:
528 .long 0x4104a200 @ ARM 1020T (Architecture v5T)
529 .long 0xff0ffff0
530 .long PMD_TYPE_SECT | \
531 PMD_SECT_AP_WRITE | \
532 PMD_SECT_AP_READ
533 .long PMD_TYPE_SECT | \
534 PMD_SECT_AP_WRITE | \
535 PMD_SECT_AP_READ
536 b __arm1020_setup
537 .long cpu_arch_name
538 .long cpu_elf_name
539 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
540 .long cpu_arm1020_name
541 .long arm1020_processor_functions
542 .long v4wbi_tlb_fns
543 .long v4wb_user_fns
544 .long arm1020_cache_fns
545 .size __arm1020_proc_info, . - __arm1020_proc_info