1 Hisilicon Platforms Device Tree Bindings
2 ----------------------------------------------------
4 Required root node properties:
5 - compatible = "hisilicon,hi3660";
8 Required root node properties:
9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660";
12 Required root node properties:
13 - compatible = "hisilicon,hi3798cv200";
15 Hi3798cv200 Poplar Board
16 Required root node properties:
17 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
20 Required root node properties:
21 - compatible = "hisilicon,hi3620-hi4511";
24 Required root node properties:
25 - compatible = "hisilicon,hi6220";
28 Required root node properties:
29 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220";
32 Required root node properties:
33 - compatible = "hisilicon,hip01-ca9x2";
36 Required root node properties:
37 - compatible = "hisilicon,hip04-d01";
40 Required root node properties:
41 - compatible = "hisilicon,hip05-d02";
44 Required root node properties:
45 - compatible = "hisilicon,hip06-d03";
48 Required root node properties:
49 - compatible = "hisilicon,hip07-d05";
51 Hisilicon system controller
54 - compatible : "hisilicon,sysctrl"
55 - reg : Register address and size
58 - smp-offset : offset in sysctrl for notifying slave cpu booting
62 If reg value is not zero, cpun exit wfi and go
63 - resume-offset : offset in sysctrl for notifying cpu0 when resume
64 - reboot-offset : offset in sysctrl for system reboot
69 sysctrl: system-controller@fc802000 {
70 compatible = "hisilicon,sysctrl";
71 reg = <0xfc802000 0x1000>;
73 resume-offset = <0x308>;
74 reboot-offset = <0x4>;
77 -----------------------------------------------------------------------
78 Hisilicon Hi6220 system controller
81 - compatible : "hisilicon,hi6220-sysctrl"
82 - reg : Register address and size
83 - #clock-cells: should be set to 1, many clock registers are defined
84 under this controller and this property must be present.
86 Hisilicon designs this controller as one of the system controllers,
87 its main functions are the same as Hisilicon system controller, but
88 the register offset of some core modules are different.
92 sys_ctrl: sys_ctrl@f7030000 {
93 compatible = "hisilicon,hi6220-sysctrl", "syscon";
94 reg = <0x0 0xf7030000 0x0 0x2000>;
99 Hisilicon Hi6220 Power Always ON domain controller
102 - compatible : "hisilicon,hi6220-aoctrl"
103 - reg : Register address and size
104 - #clock-cells: should be set to 1, many clock registers are defined
105 under this controller and this property must be present.
107 Hisilicon designs this system controller to control the power always
108 on domain for mobile platform.
112 ao_ctrl: ao_ctrl@f7800000 {
113 compatible = "hisilicon,hi6220-aoctrl", "syscon";
114 reg = <0x0 0xf7800000 0x0 0x2000>;
119 Hisilicon Hi6220 Media domain controller
122 - compatible : "hisilicon,hi6220-mediactrl"
123 - reg : Register address and size
124 - #clock-cells: should be set to 1, many clock registers are defined
125 under this controller and this property must be present.
127 Hisilicon designs this system controller to control the multimedia
128 domain(e.g. codec, G3D ...) for mobile platform.
132 media_ctrl: media_ctrl@f4410000 {
133 compatible = "hisilicon,hi6220-mediactrl", "syscon";
134 reg = <0x0 0xf4410000 0x0 0x1000>;
139 Hisilicon Hi6220 Power Management domain controller
142 - compatible : "hisilicon,hi6220-pmctrl"
143 - reg : Register address and size
144 - #clock-cells: should be set to 1, some clock registers are define
145 under this controller and this property must be present.
147 Hisilicon designs this system controller to control the power management
148 domain for mobile platform.
152 pm_ctrl: pm_ctrl@f7032000 {
153 compatible = "hisilicon,hi6220-pmctrl", "syscon";
154 reg = <0x0 0xf7032000 0x0 0x1000>;
159 Hisilicon Hi6220 SRAM controller
162 - compatible : "hisilicon,hi6220-sramctrl", "syscon"
163 - reg : Register address and size
165 Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
166 SRAM banks for power management, modem, security, etc. Further, use "syscon"
167 managing the common sram which can be shared by multiple modules.
171 sram: sram@fff80000 {
172 compatible = "hisilicon,hi6220-sramctrl", "syscon";
173 reg = <0x0 0xfff80000 0x0 0x12000>;
176 -----------------------------------------------------------------------
177 Hisilicon HiP01 system controller
180 - compatible : "hisilicon,hip01-sysctrl"
181 - reg : Register address and size
183 The HiP01 system controller is mostly compatible with hisilicon
184 system controller,but it has some specific control registers for
185 HIP01 SoC family, such as slave core boot, and also some same
186 registers located at different offset.
190 /* for hip01-ca9x2 */
191 sysctrl: system-controller@10000000 {
192 compatible = "hisilicon,hip01-sysctrl", "hisilicon,sysctrl";
193 reg = <0x10000000 0x1000>;
194 reboot-offset = <0x4>;
197 -----------------------------------------------------------------------
198 Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
201 - compatible : "hisilicon,pcie-sas-subctrl", "syscon";
202 - reg : Register address and size
204 The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
205 HiP05 or HiP06 Soc to implement some basic configurations.
208 /* for HiP05 PCIe-SAS sub system */
209 pcie_sas: system_controller@b0000000 {
210 compatible = "hisilicon,pcie-sas-subctrl", "syscon";
211 reg = <0xb0000000 0x10000>;
214 Hisilicon HiP05/HiP06 PERI sub system controller
217 - compatible : "hisilicon,peri-subctrl", "syscon";
218 - reg : Register address and size
220 The PERI sub system controller is shared by peripheral controllers in
221 HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
222 controllers include mdio, ddr, iic, uart, timer and so on.
225 /* for HiP05 sub peri system */
226 peri_c_subctrl: syscon@80000000 {
227 compatible = "hisilicon,peri-subctrl", "syscon";
228 reg = <0x0 0x80000000 0x0 0x10000>;
231 Hisilicon HiP05/HiP06 DSA sub system controller
234 - compatible : "hisilicon,dsa-subctrl", "syscon";
235 - reg : Register address and size
237 The DSA sub system controller is shared by peripheral controllers in
238 HiP05 or HiP06 Soc to implement some basic configurations.
241 /* for HiP05 dsa sub system */
242 pcie_sas: system_controller@a0000000 {
243 compatible = "hisilicon,dsa-subctrl", "syscon";
244 reg = <0xa0000000 0x10000>;
247 -----------------------------------------------------------------------
248 Hisilicon CPU controller
251 - compatible : "hisilicon,cpuctrl"
252 - reg : Register address and size
254 The clock registers and power registers of secondary cores are defined
255 in CPU controller, especially in HIX5HD2 SoC.
257 -----------------------------------------------------------------------
258 PCTRL: Peripheral misc control register
261 - compatible: "hisilicon,pctrl"
262 - reg: Address and size of pctrl.
267 pctrl: pctrl@fca09000 {
268 compatible = "hisilicon,pctrl";
269 reg = <0xfca09000 0x1000>;
272 -----------------------------------------------------------------------
276 - compatible: "hisilicon,hip04-fabric";
277 - reg: Address and size of Fabric
279 -----------------------------------------------------------------------
280 Bootwrapper boot method (software protocol on SMP):
283 - compatible: "hisilicon,hip04-bootwrapper";
284 - boot-method: Address and size of boot method.
285 [0]: bootwrapper physical address
286 [1]: bootwrapper size
287 [2]: relocation physical address