1 MediaTek PCIESYS controller
2 ============================
4 The MediaTek PCIESYS controller provides various clocks to the system.
8 - compatible: Should be:
9 - "mediatek,mt7622-pciesys", "syscon"
10 - #clock-cells: Must be 1
12 The PCIESYS controller uses the common clk binding from
13 Documentation/devicetree/bindings/clock/clock-bindings.txt
14 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
18 pciesys: pciesys@1a100800 {
19 compatible = "mediatek,mt7622-pciesys", "syscon";
20 reg = <0 0x1a100800 0 0x1000>;