Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

   1 ARM Mali Utgard GPU
   2 ===================
   3
   4 Required properties:
   5   - compatible
   6     * Must be one of the following:
   7       + "arm,mali-300"
   8       + "arm,mali-400"
   9       + "arm,mali-450"
  10     * And, optionally, one of the vendor specific compatible:
  11       + allwinner,sun4i-a10-mali
  12       + allwinner,sun7i-a20-mali
  13       + allwinner,sun50i-h5-mali
  14       + amlogic,meson-gxbb-mali
  15       + amlogic,meson-gxl-mali
  16       + rockchip,rk3036-mali
  17       + rockchip,rk3066-mali
  18       + rockchip,rk3188-mali
  19       + rockchip,rk3228-mali
  20       + rockchip,rk3328-mali
  21       + stericsson,db8500-mali
  22
  23   - reg: Physical base address and length of the GPU registers
  24
  25   - interrupts: an entry for each entry in interrupt-names.
  26     See ../interrupt-controller/interrupts.txt for details.
  27
  28   - interrupt-names:
  29     * ppX: Pixel Processor X interrupt (X from 0 to 7)
  30     * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
  31     * pp: Pixel Processor broadcast interrupt (mali-450 only)
  32     * gp: Geometry Processor interrupt
  33     * gpmmu: Geometry Processor MMU interrupt
  34
  35   - clocks: an entry for each entry in clock-names
  36   - clock-names:
  37     * bus: bus clock for the GPU
  38     * core: clock driving the GPU itself
  39
  40 Optional properties:
  41   - interrupt-names and interrupts:
  42     * pmu: Power Management Unit interrupt, if implemented in hardware
  43
  44   - memory-region:
  45     Memory region to allocate from, as defined in
  46     Documentation/devicetree/bindi/reserved-memory/reserved-memory.txt
  47
  48   - mali-supply:
  49     Phandle to regulator for the Mali device, as defined in
  50     Documentation/devicetree/bindings/regulator/regulator.txt for details.
  51
  52   - operating-points-v2:
  53     Operating Points for the GPU, as defined in
  54     Documentation/devicetree/bindings/opp/opp.txt
  55
  56   - power-domains:
  57     A power domain consumer specifier as defined in
  58     Documentation/devicetree/bindings/power/power_domain.txt
  59
  60 Vendor-specific bindings
  61 ------------------------
  62
  63 The Mali GPU is integrated very differently from one SoC to
  64 another. In order to accomodate those differences, you have the option
  65 to specify one more vendor-specific compatible, among:
  66
  67   - allwinner,sun4i-a10-mali
  68     Required properties:
  69       * resets: phandle to the reset line for the GPU
  70
  71   - allwinner,sun7i-a20-mali
  72     Required properties:
  73       * resets: phandle to the reset line for the GPU
  74
  75   - allwinner,sun50i-h5-mali
  76     Required properties:
  77       * resets: phandle to the reset line for the GPU
  78
  79   - Rockchip variants:
  80     Required properties:
  81       * resets: phandle to the reset line for the GPU
  82
  83   - stericsson,db8500-mali
  84     Required properties:
  85       * interrupt-names and interrupts:
  86         + combined: combined interrupt of all of the above lines
  87
  88 Example:
  89
  90 mali: gpu@1c40000 {
  91         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
  92         reg = <0x01c40000 0x10000>;
  93         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  94                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
  95                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  96                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  97                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  98                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
  99                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 100         interrupt-names = "gp",
 101                           "gpmmu",
 102                           "pp0",
 103                           "ppmmu0",
 104                           "pp1",
 105                           "ppmmu1",
 106                           "pmu";
 107         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 108         clock-names = "bus", "core";
 109         resets = <&ccu RST_BUS_GPU>;
 110 };
 111