Documentation/devicetree/bindings/mmc/arasan,sdhci.txt

   1 Device Tree Bindings for the Arasan SDHCI Controller
   2
   3   The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings.
   4   Only deviations are documented here.
   5
   6   [1] Documentation/devicetree/bindings/mmc/mmc.txt
   7   [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
   8   [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
   9   [4] Documentation/devicetree/bindings/phy/phy-bindings.txt
  10
  11 Required Properties:
  12   - compatible: Compatibility string.  One of:
  13     - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY
  14     - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY
  15     - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
  16     - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
  17       For this device it is strongly suggested to include arasan,soc-ctl-syscon.
  18   - reg: From mmc bindings: Register location and length.
  19   - clocks: From clock bindings: Handles to clock inputs.
  20   - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
  21   - interrupts: Interrupt specifier
  22   - interrupt-parent: Phandle for the interrupt controller that services
  23                       interrupts for this device.
  24
  25 Required Properties for "arasan,sdhci-5.1":
  26   - phys: From PHY bindings: Phandle for the Generic PHY for arasan.
  27   - phy-names:  MUST be "phy_arasan".
  28
  29 Optional Properties:
  30   - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt)
  31     used to access core corecfg registers.  Offsets of registers in this
  32     syscon are determined based on the main compatible string for the device.
  33   - clock-output-names: If specified, this will be the name of the card clock
  34     which will be exposed by this device.  Required if #clock-cells is
  35     specified.
  36   - #clock-cells: If specified this should be the value <0>.  With this property
  37     in place we will export a clock representing the Card Clock.  This clock
  38     is expected to be consumed by our PHY.  You must also specify
  39   - xlnx,fails-without-test-cd: when present, the controller doesn't work when
  40     the CD line is not connected properly, and the line is not connected
  41     properly. Test mode can be used to force the controller to function.
  42
  43 Example:
  44         sdhci@e0100000 {
  45                 compatible = "arasan,sdhci-8.9a";
  46                 reg = <0xe0100000 0x1000>;
  47                 clock-names = "clk_xin", "clk_ahb";
  48                 clocks = <&clkc 21>, <&clkc 32>;
  49                 interrupt-parent = <&gic>;
  50                 interrupts = <0 24 4>;
  51         } ;
  52
  53         sdhci@e2800000 {
  54                 compatible = "arasan,sdhci-5.1";
  55                 reg = <0xe2800000 0x1000>;
  56                 clock-names = "clk_xin", "clk_ahb";
  57                 clocks = <&cru 8>, <&cru 18>;
  58                 interrupt-parent = <&gic>;
  59                 interrupts = <0 24 4>;
  60                 phys = <&emmc_phy>;
  61                 phy-names = "phy_arasan";
  62         } ;
  63
  64         sdhci: sdhci@fe330000 {
  65                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
  66                 reg = <0x0 0xfe330000 0x0 0x10000>;
  67                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
  68                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
  69                 clock-names = "clk_xin", "clk_ahb";
  70                 arasan,soc-ctl-syscon = <&grf>;
  71                 assigned-clocks = <&cru SCLK_EMMC>;
  72                 assigned-clock-rates = <200000000>;
  73                 clock-output-names = "emmc_cardclock";
  74                 phys = <&emmc_phy>;
  75                 phy-names = "phy_arasan";
  76                 #clock-cells = <0>;
  77         };