1 Marvell NAND Flash Controller (NFC)
4 - compatible: can be one of the following:
5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
11 Compatibles marked deprecated support only the old bindings described
13 - reg: NAND flash controller memory area.
14 - #address-cells: shall be set to 1. Encode the NAND CS.
15 - #size-cells: shall be set to 0.
16 - interrupts: shall define the NAND controller interrupt.
17 - clocks: shall reference the NAND controller clock.
18 - marvell,system-controller: Set to retrieve the syscon node that handles
19 NAND controller related registers (only required with the
20 "marvell,armada-8k-nand[-controller]" compatibles).
23 - label: see partition.txt. New platforms shall omit this property.
24 - dmas: shall reference DMA channel associated to the NAND controller.
25 This property is only used with "marvell,pxa3xx-nand[-controller]"
27 - dma-names: shall be "rxtx".
28 This property is only used with "marvell,pxa3xx-nand[-controller]"
31 Optional children nodes:
32 Children nodes represent the available NAND chips.
35 - reg: shall contain the native Chip Select ids (0-3).
36 - nand-rb: see nand.txt (0-1).
39 - marvell,nand-keep-config: orders the driver not to take the timings
40 from the core and leaving them completely untouched. Bootloader
41 timings will then be used.
43 - nand-on-flash-bbt: see nand.txt.
44 - nand-ecc-mode: see nand.txt. Will use hardware ECC if not specified.
45 - nand-ecc-algo: see nand.txt. This property is essentially useful when
46 not using hardware ECC. Howerver, it may be added when using hardware
47 ECC for clarification but will be ignored by the driver because ECC
48 mode is chosen depending on the page size and the strength required by
49 the NAND chip. This value may be overwritten with nand-ecc-strength
51 - nand-ecc-strength: see nand.txt.
52 - nand-ecc-step-size: see nand.txt. Marvell's NAND flash controller does
53 use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
54 step size will shrink or grow in order to fit the required strength.
55 Step sizes are not completely random for all and follow certain
56 patterns described in AN-379, "Marvell SoC NFC ECC".
58 See Documentation/devicetree/bindings/mtd/nand.txt for more details on
63 nand_controller: nand-controller@d0000 {
64 compatible = "marvell,armada370-nand-controller";
68 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&coredivclk 0>;
73 label = "main-storage";
76 marvell,nand-keep-config;
78 nand-ecc-strength = <4>;
79 nand-ecc-step-size = <512>;
82 compatible = "fixed-partitions";
88 reg = <0x00000000 0x40000000>;
95 Note on legacy bindings: One can find, in not-updated device trees,
96 bindings slightly different than described above with other properties
97 described below as well as the partitions node at the root of a so
98 called "nand" node (without clear controller/chip separation).
101 - marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
102 used it, this bit was set by the bootloader for many boards and even if
103 it is marked reserved in several datasheets, it might be needed to set
104 it (otherwise it is harmless) so whether or not this property is set,
105 the bit is selected by the driver.
106 - num-cs: Number of chip-select lines to use, all boards blindly set 1
107 to this and for a reason, other values would have failed. The value of
108 this property is ignored.
112 nand0: nand@43100000 {
113 compatible = "marvell,pxa3xx-nand";
114 reg = <0x43100000 90>;
118 #address-cells = <1>;
119 marvell,nand-keep-config;
120 marvell,nand-enable-arbiter;
122 /* Partitions (optional) */