| blob | 3a6ce55dd310b1a2e2ba2ff572a8692a65bf8e35 |
1 MediaTek Gen2 PCIe controller
3 Required properties:
4 - compatible: Should contain one of the following strings:
5 "mediatek,mt2701-pcie"
6 "mediatek,mt2712-pcie"
7 "mediatek,mt7622-pcie"
8 "mediatek,mt7623-pcie"
9 - device_type: Must be "pci"
10 - reg: Base addresses and lengths of the PCIe subsys and root ports.
11 - reg-names: Names of the above areas to use during resource lookup.
12 - #address-cells: Address representation for root ports (must be 3)
13 - #size-cells: Size representation for root ports (must be 2)
14 - clocks: Must contain an entry for each entry in clock-names.
15 See ../clocks/clock-bindings.txt for details.
16 - clock-names:
17 Mandatory entries:
18 - sys_ckN :transaction layer and data link layer clock
19 Required entries for MT2701/MT7623:
20 - free_ck :for reference clock of PCIe subsys
21 Required entries for MT2712/MT7622:
22 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
23 initiated MMIO access
24 Required entries for MT7622:
25 - axi_ckN :application layer MMIO channel operating clock
26 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
27 pcie_mac_ck/pcie_pipe_ck is turned off
28 - obff_ckN :OBFF functional block operating clock
29 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
30 where N starting from 0 to one less than the number of root ports.
31 - phys: List of PHY specifiers (used by generic PHY framework).
32 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
33 number of PHYs as specified in *phys* property.
34 - power-domains: A phandle and power domain specifier pair to the power domain
35 which is responsible for collapsing and restoring power to the peripheral.
36 - bus-range: Range of bus numbers associated with this controller.
37 - ranges: Ranges for the PCI memory and I/O regions.
39 Required properties for MT7623/MT2701:
40 - #interrupt-cells: Size representation for interrupts (must be 1)
41 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
42 Please refer to the standard PCI bus binding document for a more detailed
43 explanation.
44 - resets: Must contain an entry for each entry in reset-names.
45 See ../reset/reset.txt for details.
46 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
47 number of root ports.
49 Required properties for MT2712/MT7622:
50 -interrupts: A list of interrupt outputs of the controller, must have one
51 entry for each PCIe port
53 In addition, the device tree node must have sub-nodes describing each
54 PCIe port interface, having the following mandatory properties:
56 Required properties:
57 - device_type: Must be "pci"
58 - reg: Only the first four bytes are used to refer to the correct bus number
59 and device number.
60 - #address-cells: Must be 3
61 - #size-cells: Must be 2
62 - #interrupt-cells: Must be 1
63 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
64 Please refer to the standard PCI bus binding document for a more detailed
65 explanation.
66 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
67 property is sufficient.
68 - num-lanes: Number of lanes to use for this port.
70 Examples for MT7623:
72 hifsys: syscon@1a000000 {
73 compatible = "mediatek,mt7623-hifsys",
74 "mediatek,mt2701-hifsys",
75 "syscon";
76 reg = <0 0x1a000000 0 0x1000>;
77 #clock-cells = <1>;
78 #reset-cells = <1>;
79 };
81 pcie: pcie-controller@1a140000 {
82 compatible = "mediatek,mt7623-pcie";
83 device_type = "pci";
84 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
85 <0 0x1a142000 0 0x1000>, /* Port0 registers */
86 <0 0x1a143000 0 0x1000>, /* Port1 registers */
87 <0 0x1a144000 0 0x1000>; /* Port2 registers */
88 reg-names = "subsys", "port0", "port1", "port2";
89 #address-cells = <3>;
90 #size-cells = <2>;
91 #interrupt-cells = <1>;
92 interrupt-map-mask = <0xf800 0 0 0>;
93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
94 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
95 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
96 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
97 <&hifsys CLK_HIFSYS_PCIE0>,
98 <&hifsys CLK_HIFSYS_PCIE1>,
99 <&hifsys CLK_HIFSYS_PCIE2>;
100 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
101 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
102 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
103 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
104 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
105 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
106 <&pcie2_phy PHY_TYPE_PCIE>;
107 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
108 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
109 bus-range = <0x00 0xff>;
110 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
111 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
113 pcie@0,0 {
114 device_type = "pci";
115 reg = <0x0000 0 0 0 0>;
116 #address-cells = <3>;
117 #size-cells = <2>;
118 #interrupt-cells = <1>;
119 interrupt-map-mask = <0 0 0 0>;
120 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
121 ranges;
122 num-lanes = <1>;
123 };
125 pcie@1,0 {
126 device_type = "pci";
127 reg = <0x0800 0 0 0 0>;
128 #address-cells = <3>;
129 #size-cells = <2>;
130 #interrupt-cells = <1>;
131 interrupt-map-mask = <0 0 0 0>;
132 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
133 ranges;
134 num-lanes = <1>;
135 };
137 pcie@2,0 {
138 device_type = "pci";
139 reg = <0x1000 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 interrupt-map-mask = <0 0 0 0>;
144 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
145 ranges;
146 num-lanes = <1>;
147 };
148 };
150 Examples for MT2712:
151 pcie: pcie@11700000 {
152 compatible = "mediatek,mt2712-pcie";
153 device_type = "pci";
154 reg = <0 0x11700000 0 0x1000>,
155 <0 0x112ff000 0 0x1000>;
156 reg-names = "port0", "port1";
157 #address-cells = <3>;
158 #size-cells = <2>;
159 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
162 <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
163 <&pericfg CLK_PERI_PCIE0>,
164 <&pericfg CLK_PERI_PCIE1>;
165 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
166 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
167 phy-names = "pcie-phy0", "pcie-phy1";
168 bus-range = <0x00 0xff>;
169 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
171 pcie0: pcie@0,0 {
172 device_type = "pci";
173 reg = <0x0000 0 0 0 0>;
174 #address-cells = <3>;
175 #size-cells = <2>;
176 #interrupt-cells = <1>;
177 ranges;
178 num-lanes = <1>;
179 interrupt-map-mask = <0 0 0 7>;
180 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
181 <0 0 0 2 &pcie_intc0 1>,
182 <0 0 0 3 &pcie_intc0 2>,
183 <0 0 0 4 &pcie_intc0 3>;
184 pcie_intc0: interrupt-controller {
185 interrupt-controller;
186 #address-cells = <0>;
187 #interrupt-cells = <1>;
188 };
189 };
191 pcie1: pcie@1,0 {
192 device_type = "pci";
193 reg = <0x0800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 num-lanes = <1>;
199 interrupt-map-mask = <0 0 0 7>;
200 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
201 <0 0 0 2 &pcie_intc1 1>,
202 <0 0 0 3 &pcie_intc1 2>,
203 <0 0 0 4 &pcie_intc1 3>;
204 pcie_intc1: interrupt-controller {
205 interrupt-controller;
206 #address-cells = <0>;
207 #interrupt-cells = <1>;
208 };
209 };
210 };
212 Examples for MT7622:
213 pcie: pcie@1a140000 {
214 compatible = "mediatek,mt7622-pcie";
215 device_type = "pci";
216 reg = <0 0x1a140000 0 0x1000>,
217 <0 0x1a143000 0 0x1000>,
218 <0 0x1a145000 0 0x1000>;
219 reg-names = "subsys", "port0", "port1";
220 #address-cells = <3>;
221 #size-cells = <2>;
222 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
223 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
224 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
225 <&pciesys CLK_PCIE_P1_MAC_EN>,
226 <&pciesys CLK_PCIE_P0_AHB_EN>,
227 <&pciesys CLK_PCIE_P1_AHB_EN>,
228 <&pciesys CLK_PCIE_P0_AUX_EN>,
229 <&pciesys CLK_PCIE_P1_AUX_EN>,
230 <&pciesys CLK_PCIE_P0_AXI_EN>,
231 <&pciesys CLK_PCIE_P1_AXI_EN>,
232 <&pciesys CLK_PCIE_P0_OBFF_EN>,
233 <&pciesys CLK_PCIE_P1_OBFF_EN>,
234 <&pciesys CLK_PCIE_P0_PIPE_EN>,
235 <&pciesys CLK_PCIE_P1_PIPE_EN>;
236 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
237 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
238 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
239 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>;
240 phy-names = "pcie-phy0", "pcie-phy1";
241 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
242 bus-range = <0x00 0xff>;
243 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
245 pcie0: pcie@0,0 {
246 device_type = "pci";
247 reg = <0x0000 0 0 0 0>;
248 #address-cells = <3>;
249 #size-cells = <2>;
250 #interrupt-cells = <1>;
251 ranges;
252 num-lanes = <1>;
253 interrupt-map-mask = <0 0 0 7>;
254 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
255 <0 0 0 2 &pcie_intc0 1>,
256 <0 0 0 3 &pcie_intc0 2>,
257 <0 0 0 4 &pcie_intc0 3>;
258 pcie_intc0: interrupt-controller {
259 interrupt-controller;
260 #address-cells = <0>;
261 #interrupt-cells = <1>;
262 };
263 };
265 pcie1: pcie@1,0 {
266 device_type = "pci";
267 reg = <0x0800 0 0 0 0>;
268 #address-cells = <3>;
269 #size-cells = <2>;
270 #interrupt-cells = <1>;
271 ranges;
272 num-lanes = <1>;
273 interrupt-map-mask = <0 0 0 7>;
274 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
275 <0 0 0 2 &pcie_intc1 1>,
276 <0 0 0 3 &pcie_intc1 2>,
277 <0 0 0 4 &pcie_intc1 3>;
278 pcie_intc1: interrupt-controller {
279 interrupt-controller;
280 #address-cells = <0>;
281 #interrupt-cells = <1>;
282 };
283 };
284 };