1 ARM Freescale DSPI controller
4 - compatible : "fsl,vf610-dspi", "fsl,ls1021a-v1.0-dspi",
7 "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
8 "fsl,ls1012a-dspi" followed by "fsl,ls1021a-v1.0-dspi"
9 - reg : Offset and length of the register set for the device
10 - interrupts : Should contain SPI controller interrupt
11 - clocks: from common clock binding: handle to dspi clock.
12 - clock-names: from common clock binding: Shall be "dspi".
13 - pinctrl-0: pin control group to be used for this controller.
14 - pinctrl-names: must contain a "default" entry.
15 - spi-num-chipselects : the number of the chipselect signals.
16 - bus-num : the slave chip chipselect signal number.
19 - big-endian: If present the dspi device's registers are implemented
22 Optional SPI slave node properties:
23 - fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
24 select and the start of clock signal, at the start of a transfer.
25 - fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
26 signal and deactivating chip select, at the end of a transfer.
33 compatible = "fsl,vf610-dspi";
34 reg = <0x4002c000 0x1000>;
35 interrupts = <0 67 0x04>;
36 clocks = <&clks VF610_CLK_DSPI0>;
38 spi-num-chipselects = <5>;
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_dspi0_1>;
44 sflash: at26df081a@0 {
47 compatible = "atmel,at26df081a";
48 spi-max-frequency = <16000000>;
52 linux,modalias = "m25p80";
54 fsl,spi-cs-sck-delay = <100>;
55 fsl,spi-sck-cs-delay = <50>;