Documentation/devicetree/bindings/usb/qcom,dwc3.txt

   1 Qualcomm SuperSpeed DWC3 USB SoC controller
   2
   3 Required properties:
   4 - compatible:   should contain "qcom,dwc3"
   5 - clocks:               A list of phandle + clock-specifier pairs for the
   6                                 clocks listed in clock-names
   7 - clock-names:  Should contain the following:
   8   "core"                Master/Core clock, have to be >= 125 MHz for SS
   9                                 operation and >= 60MHz for HS operation
  10
  11 Optional clocks:
  12   "iface"               System bus AXI clock.  Not present on all platforms
  13   "sleep"               Sleep clock, used when USB3 core goes into low
  14                                 power mode (U3).
  15
  16 Required child node:
  17 A child node must exist to represent the core DWC3 IP block. The name of
  18 the node is not important. The content of the node is defined in dwc3.txt.
  19
  20 Phy documentation is provided in the following places:
  21 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
  22
  23 Example device nodes:
  24
  25                 hs_phy: phy@100f8800 {
  26                         compatible = "qcom,dwc3-hs-usb-phy";
  27                         reg = <0x100f8800 0x30>;
  28                         clocks = <&gcc USB30_0_UTMI_CLK>;
  29                         clock-names = "ref";
  30                         #phy-cells = <0>;
  31
  32                 };
  33
  34                 ss_phy: phy@100f8830 {
  35                         compatible = "qcom,dwc3-ss-usb-phy";
  36                         reg = <0x100f8830 0x30>;
  37                         clocks = <&gcc USB30_0_MASTER_CLK>;
  38                         clock-names = "ref";
  39                         #phy-cells = <0>;
  40
  41                 };
  42
  43                 usb3_0: usb30@0 {
  44                         compatible = "qcom,dwc3";
  45                         #address-cells = <1>;
  46                         #size-cells = <1>;
  47                         clocks = <&gcc USB30_0_MASTER_CLK>;
  48                         clock-names = "core";
  49
  50                         ranges;
  51
  52
  53                         dwc3@10000000 {
  54                                 compatible = "snps,dwc3";
  55                                 reg = <0x10000000 0xcd00>;
  56                                 interrupts = <0 205 0x4>;
  57                                 phys = <&hs_phy>, <&ss_phy>;
  58                                 phy-names = "usb2-phy", "usb3-phy";
  59                                 dr_mode = "host";
  60                         };
  61                 };
  62