arch/ia64/include/asm/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef _ASM_IA64_PCI_H
   3 #define _ASM_IA64_PCI_H
   4
   5 #include <linux/mm.h>
   6 #include <linux/slab.h>
   7 #include <linux/spinlock.h>
   8 #include <linux/string.h>
   9 #include <linux/types.h>
  10 #include <linux/scatterlist.h>
  11
  12 #include <asm/io.h>
  13 #include <asm/hw_irq.h>
  14
  15 struct pci_vector_struct {
  16         __u16 segment;  /* PCI Segment number */
  17         __u16 bus;      /* PCI Bus number */
  18         __u32 pci_id;   /* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
  19         __u8 pin;       /* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
  20         __u32 irq;      /* IRQ assigned */
  21 };
  22
  23 /*
  24  * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
  25  * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
  26  * loader.
  27  */
  28 #define pcibios_assign_all_busses()     0
  29
  30 #define PCIBIOS_MIN_IO          0x1000
  31 #define PCIBIOS_MIN_MEM         0x10000000
  32
  33 /*
  34  * PCI_DMA_BUS_IS_PHYS should be set to 1 if there is _necessarily_ a direct
  35  * correspondence between device bus addresses and CPU physical addresses.
  36  * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
  37  * bounce buffer handling code in the block and network device layers.
  38  * Platforms with separate bus address spaces _must_ turn this off and provide
  39  * a device DMA mapping implementation that takes care of the necessary
  40  * address translation.
  41  *
  42  * For now, the ia64 platforms which may have separate/multiple bus address
  43  * spaces all have I/O MMUs which support the merging of physically
  44  * discontiguous buffers, so we can use that as the sole factor to determine
  45  * the setting of PCI_DMA_BUS_IS_PHYS.
  46  */
  47 extern unsigned long ia64_max_iommu_merge_mask;
  48 #define PCI_DMA_BUS_IS_PHYS     (ia64_max_iommu_merge_mask == ~0UL)
  49
  50 #define HAVE_PCI_MMAP
  51 #define ARCH_GENERIC_PCI_MMAP_RESOURCE
  52 #define arch_can_pci_mmap_wc()  1
  53
  54 #define HAVE_PCI_LEGACY
  55 extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
  56                                       struct vm_area_struct *vma,
  57                                       enum pci_mmap_state mmap_state);
  58
  59 #define pci_get_legacy_mem platform_pci_get_legacy_mem
  60 #define pci_legacy_read platform_pci_legacy_read
  61 #define pci_legacy_write platform_pci_legacy_write
  62
  63 struct pci_controller {
  64         struct acpi_device *companion;
  65         void *iommu;
  66         int segment;
  67         int node;               /* nearest node with memory or NUMA_NO_NODE for global allocation */
  68
  69         void *platform_data;
  70 };
  71
  72
  73 #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
  74 #define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
  75
  76 extern struct pci_ops pci_root_ops;
  77
  78 static inline int pci_proc_domain(struct pci_bus *bus)
  79 {
  80         return (pci_domain_nr(bus) != 0);
  81 }
  82
  83 #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
  84 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
  85 {
  86         return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
  87 }
  88
  89 #ifdef CONFIG_INTEL_IOMMU
  90 extern void pci_iommu_alloc(void);
  91 #endif
  92 #endif /* _ASM_IA64_PCI_H */