arch/powerpc/mm/mmu_context_book3s64.c

   1 /*
   2  *  MMU context allocation for 64-bit kernels.
   3  *
   4  *  Copyright (C) 2004 Anton Blanchard, IBM Corp. <anton@samba.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/sched.h>
  14 #include <linux/kernel.h>
  15 #include <linux/errno.h>
  16 #include <linux/string.h>
  17 #include <linux/types.h>
  18 #include <linux/mm.h>
  19 #include <linux/pkeys.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/idr.h>
  22 #include <linux/export.h>
  23 #include <linux/gfp.h>
  24 #include <linux/slab.h>
  25
  26 #include <asm/mmu_context.h>
  27 #include <asm/pgalloc.h>
  28
  29 static DEFINE_SPINLOCK(mmu_context_lock);
  30 static DEFINE_IDA(mmu_context_ida);
  31
  32 static int alloc_context_id(int min_id, int max_id)
  33 {
  34         int index, err;
  35
  36 again:
  37         if (!ida_pre_get(&mmu_context_ida, GFP_KERNEL))
  38                 return -ENOMEM;
  39
  40         spin_lock(&mmu_context_lock);
  41         err = ida_get_new_above(&mmu_context_ida, min_id, &index);
  42         spin_unlock(&mmu_context_lock);
  43
  44         if (err == -EAGAIN)
  45                 goto again;
  46         else if (err)
  47                 return err;
  48
  49         if (index > max_id) {
  50                 spin_lock(&mmu_context_lock);
  51                 ida_remove(&mmu_context_ida, index);
  52                 spin_unlock(&mmu_context_lock);
  53                 return -ENOMEM;
  54         }
  55
  56         return index;
  57 }
  58
  59 void hash__reserve_context_id(int id)
  60 {
  61         int rc, result = 0;
  62
  63         do {
  64                 if (!ida_pre_get(&mmu_context_ida, GFP_KERNEL))
  65                         break;
  66
  67                 spin_lock(&mmu_context_lock);
  68                 rc = ida_get_new_above(&mmu_context_ida, id, &result);
  69                 spin_unlock(&mmu_context_lock);
  70         } while (rc == -EAGAIN);
  71
  72         WARN(result != id, "mmu: Failed to reserve context id %d (rc %d)\n", id, result);
  73 }
  74
  75 int hash__alloc_context_id(void)
  76 {
  77         unsigned long max;
  78
  79         if (mmu_has_feature(MMU_FTR_68_BIT_VA))
  80                 max = MAX_USER_CONTEXT;
  81         else
  82                 max = MAX_USER_CONTEXT_65BIT_VA;
  83
  84         return alloc_context_id(MIN_USER_CONTEXT, max);
  85 }
  86 EXPORT_SYMBOL_GPL(hash__alloc_context_id);
  87
  88 static int hash__init_new_context(struct mm_struct *mm)
  89 {
  90         int index;
  91
  92         index = hash__alloc_context_id();
  93         if (index < 0)
  94                 return index;
  95
  96         /*
  97          * In the case of exec, use the default limit,
  98          * otherwise inherit it from the mm we are duplicating.
  99          */
 100         if (!mm->context.slb_addr_limit)
 101                 mm->context.slb_addr_limit = DEFAULT_MAP_WINDOW_USER64;
 102
 103         /*
 104          * The old code would re-promote on fork, we don't do that when using
 105          * slices as it could cause problem promoting slices that have been
 106          * forced down to 4K.
 107          *
 108          * For book3s we have MMU_NO_CONTEXT set to be ~0. Hence check
 109          * explicitly against context.id == 0. This ensures that we properly
 110          * initialize context slice details for newly allocated mm's (which will
 111          * have id == 0) and don't alter context slice inherited via fork (which
 112          * will have id != 0).
 113          *
 114          * We should not be calling init_new_context() on init_mm. Hence a
 115          * check against 0 is OK.
 116          */
 117         if (mm->context.id == 0)
 118                 slice_set_user_psize(mm, mmu_virtual_psize);
 119
 120         subpage_prot_init_new_context(mm);
 121
 122         pkey_mm_init(mm);
 123         return index;
 124 }
 125
 126 static int radix__init_new_context(struct mm_struct *mm)
 127 {
 128         unsigned long rts_field;
 129         int index, max_id;
 130
 131         max_id = (1 << mmu_pid_bits) - 1;
 132         index = alloc_context_id(mmu_base_pid, max_id);
 133         if (index < 0)
 134                 return index;
 135
 136         /*
 137          * set the process table entry,
 138          */
 139         rts_field = radix__get_tree_size();
 140         process_tb[index].prtb0 = cpu_to_be64(rts_field | __pa(mm->pgd) | RADIX_PGD_INDEX_SIZE);
 141
 142         /*
 143          * Order the above store with subsequent update of the PID
 144          * register (at which point HW can start loading/caching
 145          * the entry) and the corresponding load by the MMU from
 146          * the L2 cache.
 147          */
 148         asm volatile("ptesync;isync" : : : "memory");
 149
 150         mm->context.npu_context = NULL;
 151
 152         return index;
 153 }
 154
 155 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 156 {
 157         int index;
 158
 159         if (radix_enabled())
 160                 index = radix__init_new_context(mm);
 161         else
 162                 index = hash__init_new_context(mm);
 163
 164         if (index < 0)
 165                 return index;
 166
 167         mm->context.id = index;
 168
 169 #ifdef CONFIG_PPC_64K_PAGES
 170         mm->context.pte_frag = NULL;
 171 #endif
 172 #ifdef CONFIG_SPAPR_TCE_IOMMU
 173         mm_iommu_init(mm);
 174 #endif
 175         atomic_set(&mm->context.active_cpus, 0);
 176
 177         return 0;
 178 }
 179
 180 void __destroy_context(int context_id)
 181 {
 182         spin_lock(&mmu_context_lock);
 183         ida_remove(&mmu_context_ida, context_id);
 184         spin_unlock(&mmu_context_lock);
 185 }
 186 EXPORT_SYMBOL_GPL(__destroy_context);
 187
 188 #ifdef CONFIG_PPC_64K_PAGES
 189 static void destroy_pagetable_page(struct mm_struct *mm)
 190 {
 191         int count;
 192         void *pte_frag;
 193         struct page *page;
 194
 195         pte_frag = mm->context.pte_frag;
 196         if (!pte_frag)
 197                 return;
 198
 199         page = virt_to_page(pte_frag);
 200         /* drop all the pending references */
 201         count = ((unsigned long)pte_frag & ~PAGE_MASK) >> PTE_FRAG_SIZE_SHIFT;
 202         /* We allow PTE_FRAG_NR fragments from a PTE page */
 203         if (page_ref_sub_and_test(page, PTE_FRAG_NR - count)) {
 204                 pgtable_page_dtor(page);
 205                 free_unref_page(page);
 206         }
 207 }
 208
 209 #else
 210 static inline void destroy_pagetable_page(struct mm_struct *mm)
 211 {
 212         return;
 213 }
 214 #endif
 215
 216 void destroy_context(struct mm_struct *mm)
 217 {
 218 #ifdef CONFIG_SPAPR_TCE_IOMMU
 219         WARN_ON_ONCE(!list_empty(&mm->context.iommu_group_mem_list));
 220 #endif
 221         if (radix_enabled())
 222                 WARN_ON(process_tb[mm->context.id].prtb0 != 0);
 223         else
 224                 subpage_prot_free(mm);
 225         destroy_pagetable_page(mm);
 226         __destroy_context(mm->context.id);
 227         mm->context.id = MMU_NO_CONTEXT;
 228 }
 229
 230 void arch_exit_mmap(struct mm_struct *mm)
 231 {
 232         if (radix_enabled()) {
 233                 /*
 234                  * Radix doesn't have a valid bit in the process table
 235                  * entries. However we know that at least P9 implementation
 236                  * will avoid caching an entry with an invalid RTS field,
 237                  * and 0 is invalid. So this will do.
 238                  *
 239                  * This runs before the "fullmm" tlb flush in exit_mmap,
 240                  * which does a RIC=2 tlbie to clear the process table
 241                  * entry. See the "fullmm" comments in tlb-radix.c.
 242                  *
 243                  * No barrier required here after the store because
 244                  * this process will do the invalidate, which starts with
 245                  * ptesync.
 246                  */
 247                 process_tb[mm->context.id].prtb0 = 0;
 248         }
 249 }
 250
 251 #ifdef CONFIG_PPC_RADIX_MMU
 252 void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 253 {
 254
 255         if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 256                 isync();
 257                 mtspr(SPRN_PID, next->context.id);
 258                 isync();
 259                 asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
 260         } else {
 261                 mtspr(SPRN_PID, next->context.id);
 262                 isync();
 263         }
 264 }
 265 #endif