arch/powerpc/mm/pgtable-radix.c

   1 /*
   2  * Page table handling routines for radix page table.
   3  *
   4  * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #define pr_fmt(fmt) "radix-mmu: " fmt
  13
  14 #include <linux/kernel.h>
  15 #include <linux/sched/mm.h>
  16 #include <linux/memblock.h>
  17 #include <linux/of_fdt.h>
  18 #include <linux/mm.h>
  19 #include <linux/string_helpers.h>
  20 #include <linux/stop_machine.h>
  21
  22 #include <asm/pgtable.h>
  23 #include <asm/pgalloc.h>
  24 #include <asm/mmu_context.h>
  25 #include <asm/dma.h>
  26 #include <asm/machdep.h>
  27 #include <asm/mmu.h>
  28 #include <asm/firmware.h>
  29 #include <asm/powernv.h>
  30 #include <asm/sections.h>
  31 #include <asm/trace.h>
  32
  33 #include <trace/events/thp.h>
  34
  35 unsigned int mmu_pid_bits;
  36 unsigned int mmu_base_pid;
  37
  38 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
  39                                          unsigned long table_size)
  40 {
  41         unsigned long patb0, patb1;
  42
  43         patb0 = be64_to_cpu(partition_tb[0].patb0);
  44         patb1 = base | table_size | PATB_GR;
  45
  46         mmu_partition_table_set_entry(0, patb0, patb1);
  47
  48         return 0;
  49 }
  50
  51 static __ref void *early_alloc_pgtable(unsigned long size)
  52 {
  53         void *pt;
  54
  55         pt = __va(memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE));
  56         memset(pt, 0, size);
  57
  58         return pt;
  59 }
  60
  61 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
  62                           pgprot_t flags,
  63                           unsigned int map_page_size)
  64 {
  65         pgd_t *pgdp;
  66         pud_t *pudp;
  67         pmd_t *pmdp;
  68         pte_t *ptep;
  69         /*
  70          * Make sure task size is correct as per the max adddr
  71          */
  72         BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
  73         if (slab_is_available()) {
  74                 pgdp = pgd_offset_k(ea);
  75                 pudp = pud_alloc(&init_mm, pgdp, ea);
  76                 if (!pudp)
  77                         return -ENOMEM;
  78                 if (map_page_size == PUD_SIZE) {
  79                         ptep = (pte_t *)pudp;
  80                         goto set_the_pte;
  81                 }
  82                 pmdp = pmd_alloc(&init_mm, pudp, ea);
  83                 if (!pmdp)
  84                         return -ENOMEM;
  85                 if (map_page_size == PMD_SIZE) {
  86                         ptep = pmdp_ptep(pmdp);
  87                         goto set_the_pte;
  88                 }
  89                 ptep = pte_alloc_kernel(pmdp, ea);
  90                 if (!ptep)
  91                         return -ENOMEM;
  92         } else {
  93                 pgdp = pgd_offset_k(ea);
  94                 if (pgd_none(*pgdp)) {
  95                         pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
  96                         BUG_ON(pudp == NULL);
  97                         pgd_populate(&init_mm, pgdp, pudp);
  98                 }
  99                 pudp = pud_offset(pgdp, ea);
 100                 if (map_page_size == PUD_SIZE) {
 101                         ptep = (pte_t *)pudp;
 102                         goto set_the_pte;
 103                 }
 104                 if (pud_none(*pudp)) {
 105                         pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
 106                         BUG_ON(pmdp == NULL);
 107                         pud_populate(&init_mm, pudp, pmdp);
 108                 }
 109                 pmdp = pmd_offset(pudp, ea);
 110                 if (map_page_size == PMD_SIZE) {
 111                         ptep = pmdp_ptep(pmdp);
 112                         goto set_the_pte;
 113                 }
 114                 if (!pmd_present(*pmdp)) {
 115                         ptep = early_alloc_pgtable(PAGE_SIZE);
 116                         BUG_ON(ptep == NULL);
 117                         pmd_populate_kernel(&init_mm, pmdp, ptep);
 118                 }
 119                 ptep = pte_offset_kernel(pmdp, ea);
 120         }
 121
 122 set_the_pte:
 123         set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT, flags));
 124         smp_wmb();
 125         return 0;
 126 }
 127
 128 #ifdef CONFIG_STRICT_KERNEL_RWX
 129 void radix__change_memory_range(unsigned long start, unsigned long end,
 130                                 unsigned long clear)
 131 {
 132         unsigned long idx;
 133         pgd_t *pgdp;
 134         pud_t *pudp;
 135         pmd_t *pmdp;
 136         pte_t *ptep;
 137
 138         start = ALIGN_DOWN(start, PAGE_SIZE);
 139         end = PAGE_ALIGN(end); // aligns up
 140
 141         pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
 142                  start, end, clear);
 143
 144         for (idx = start; idx < end; idx += PAGE_SIZE) {
 145                 pgdp = pgd_offset_k(idx);
 146                 pudp = pud_alloc(&init_mm, pgdp, idx);
 147                 if (!pudp)
 148                         continue;
 149                 if (pud_huge(*pudp)) {
 150                         ptep = (pte_t *)pudp;
 151                         goto update_the_pte;
 152                 }
 153                 pmdp = pmd_alloc(&init_mm, pudp, idx);
 154                 if (!pmdp)
 155                         continue;
 156                 if (pmd_huge(*pmdp)) {
 157                         ptep = pmdp_ptep(pmdp);
 158                         goto update_the_pte;
 159                 }
 160                 ptep = pte_alloc_kernel(pmdp, idx);
 161                 if (!ptep)
 162                         continue;
 163 update_the_pte:
 164                 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
 165         }
 166
 167         radix__flush_tlb_kernel_range(start, end);
 168 }
 169
 170 void radix__mark_rodata_ro(void)
 171 {
 172         unsigned long start, end;
 173
 174         /*
 175          * mark_rodata_ro() will mark itself as !writable at some point.
 176          * Due to DD1 workaround in radix__pte_update(), we'll end up with
 177          * an invalid pte and the system will crash quite severly.
 178          */
 179         if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
 180                 pr_warn("Warning: Unable to mark rodata read only on P9 DD1\n");
 181                 return;
 182         }
 183
 184         start = (unsigned long)_stext;
 185         end = (unsigned long)__init_begin;
 186
 187         radix__change_memory_range(start, end, _PAGE_WRITE);
 188 }
 189
 190 void radix__mark_initmem_nx(void)
 191 {
 192         unsigned long start = (unsigned long)__init_begin;
 193         unsigned long end = (unsigned long)__init_end;
 194
 195         radix__change_memory_range(start, end, _PAGE_EXEC);
 196 }
 197 #endif /* CONFIG_STRICT_KERNEL_RWX */
 198
 199 static inline void __meminit print_mapping(unsigned long start,
 200                                            unsigned long end,
 201                                            unsigned long size)
 202 {
 203         char buf[10];
 204
 205         if (end <= start)
 206                 return;
 207
 208         string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
 209
 210         pr_info("Mapped 0x%016lx-0x%016lx with %s pages\n", start, end, buf);
 211 }
 212
 213 static int __meminit create_physical_mapping(unsigned long start,
 214                                              unsigned long end)
 215 {
 216         unsigned long vaddr, addr, mapping_size = 0;
 217         pgprot_t prot;
 218         unsigned long max_mapping_size;
 219 #ifdef CONFIG_STRICT_KERNEL_RWX
 220         int split_text_mapping = 1;
 221 #else
 222         int split_text_mapping = 0;
 223 #endif
 224
 225         start = _ALIGN_UP(start, PAGE_SIZE);
 226         for (addr = start; addr < end; addr += mapping_size) {
 227                 unsigned long gap, previous_size;
 228                 int rc;
 229
 230                 gap = end - addr;
 231                 previous_size = mapping_size;
 232                 max_mapping_size = PUD_SIZE;
 233
 234 retry:
 235                 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
 236                     mmu_psize_defs[MMU_PAGE_1G].shift &&
 237                     PUD_SIZE <= max_mapping_size)
 238                         mapping_size = PUD_SIZE;
 239                 else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
 240                          mmu_psize_defs[MMU_PAGE_2M].shift)
 241                         mapping_size = PMD_SIZE;
 242                 else
 243                         mapping_size = PAGE_SIZE;
 244
 245                 if (split_text_mapping && (mapping_size == PUD_SIZE) &&
 246                         (addr <= __pa_symbol(__init_begin)) &&
 247                         (addr + mapping_size) >= __pa_symbol(_stext)) {
 248                         max_mapping_size = PMD_SIZE;
 249                         goto retry;
 250                 }
 251
 252                 if (split_text_mapping && (mapping_size == PMD_SIZE) &&
 253                     (addr <= __pa_symbol(__init_begin)) &&
 254                     (addr + mapping_size) >= __pa_symbol(_stext))
 255                         mapping_size = PAGE_SIZE;
 256
 257                 if (mapping_size != previous_size) {
 258                         print_mapping(start, addr, previous_size);
 259                         start = addr;
 260                 }
 261
 262                 vaddr = (unsigned long)__va(addr);
 263
 264                 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
 265                     overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size))
 266                         prot = PAGE_KERNEL_X;
 267                 else
 268                         prot = PAGE_KERNEL;
 269
 270                 rc = radix__map_kernel_page(vaddr, addr, prot, mapping_size);
 271                 if (rc)
 272                         return rc;
 273         }
 274
 275         print_mapping(start, addr, mapping_size);
 276         return 0;
 277 }
 278
 279 static void __init radix_init_pgtable(void)
 280 {
 281         unsigned long rts_field;
 282         struct memblock_region *reg;
 283
 284         /* We don't support slb for radix */
 285         mmu_slb_size = 0;
 286         /*
 287          * Create the linear mapping, using standard page size for now
 288          */
 289         for_each_memblock(memory, reg)
 290                 WARN_ON(create_physical_mapping(reg->base,
 291                                                 reg->base + reg->size));
 292
 293         /* Find out how many PID bits are supported */
 294         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 295                 if (!mmu_pid_bits)
 296                         mmu_pid_bits = 20;
 297 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 298                 /*
 299                  * When KVM is possible, we only use the top half of the
 300                  * PID space to avoid collisions between host and guest PIDs
 301                  * which can cause problems due to prefetch when exiting the
 302                  * guest with AIL=3
 303                  */
 304                 mmu_base_pid = 1 << (mmu_pid_bits - 1);
 305 #else
 306                 mmu_base_pid = 1;
 307 #endif
 308         } else {
 309                 /* The guest uses the bottom half of the PID space */
 310                 if (!mmu_pid_bits)
 311                         mmu_pid_bits = 19;
 312                 mmu_base_pid = 1;
 313         }
 314
 315         /*
 316          * Allocate Partition table and process table for the
 317          * host.
 318          */
 319         BUG_ON(PRTB_SIZE_SHIFT > 36);
 320         process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT);
 321         /*
 322          * Fill in the process table.
 323          */
 324         rts_field = radix__get_tree_size();
 325         process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
 326         /*
 327          * Fill in the partition table. We are suppose to use effective address
 328          * of process table here. But our linear mapping also enable us to use
 329          * physical address here.
 330          */
 331         register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
 332         pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
 333         asm volatile("ptesync" : : : "memory");
 334         asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
 335                      "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
 336         asm volatile("eieio; tlbsync; ptesync" : : : "memory");
 337         trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
 338
 339         /*
 340          * The init_mm context is given the first available (non-zero) PID,
 341          * which is the "guard PID" and contains no page table. PIDR should
 342          * never be set to zero because that duplicates the kernel address
 343          * space at the 0x0... offset (quadrant 0)!
 344          *
 345          * An arbitrary PID that may later be allocated by the PID allocator
 346          * for userspace processes must not be used either, because that
 347          * would cause stale user mappings for that PID on CPUs outside of
 348          * the TLB invalidation scheme (because it won't be in mm_cpumask).
 349          *
 350          * So permanently carve out one PID for the purpose of a guard PID.
 351          */
 352         init_mm.context.id = mmu_base_pid;
 353         mmu_base_pid++;
 354 }
 355
 356 static void __init radix_init_partition_table(void)
 357 {
 358         unsigned long rts_field, dw0;
 359
 360         mmu_partition_table_init();
 361         rts_field = radix__get_tree_size();
 362         dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
 363         mmu_partition_table_set_entry(0, dw0, 0);
 364
 365         pr_info("Initializing Radix MMU\n");
 366         pr_info("Partition table %p\n", partition_tb);
 367 }
 368
 369 void __init radix_init_native(void)
 370 {
 371         register_process_table = native_register_process_table;
 372 }
 373
 374 static int __init get_idx_from_shift(unsigned int shift)
 375 {
 376         int idx = -1;
 377
 378         switch (shift) {
 379         case 0xc:
 380                 idx = MMU_PAGE_4K;
 381                 break;
 382         case 0x10:
 383                 idx = MMU_PAGE_64K;
 384                 break;
 385         case 0x15:
 386                 idx = MMU_PAGE_2M;
 387                 break;
 388         case 0x1e:
 389                 idx = MMU_PAGE_1G;
 390                 break;
 391         }
 392         return idx;
 393 }
 394
 395 static int __init radix_dt_scan_page_sizes(unsigned long node,
 396                                            const char *uname, int depth,
 397                                            void *data)
 398 {
 399         int size = 0;
 400         int shift, idx;
 401         unsigned int ap;
 402         const __be32 *prop;
 403         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 404
 405         /* We are scanning "cpu" nodes only */
 406         if (type == NULL || strcmp(type, "cpu") != 0)
 407                 return 0;
 408
 409         /* Find MMU PID size */
 410         prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
 411         if (prop && size == 4)
 412                 mmu_pid_bits = be32_to_cpup(prop);
 413
 414         /* Grab page size encodings */
 415         prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
 416         if (!prop)
 417                 return 0;
 418
 419         pr_info("Page sizes from device-tree:\n");
 420         for (; size >= 4; size -= 4, ++prop) {
 421
 422                 struct mmu_psize_def *def;
 423
 424                 /* top 3 bit is AP encoding */
 425                 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
 426                 ap = be32_to_cpu(prop[0]) >> 29;
 427                 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
 428
 429                 idx = get_idx_from_shift(shift);
 430                 if (idx < 0)
 431                         continue;
 432
 433                 def = &mmu_psize_defs[idx];
 434                 def->shift = shift;
 435                 def->ap  = ap;
 436         }
 437
 438         /* needed ? */
 439         cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
 440         return 1;
 441 }
 442
 443 void __init radix__early_init_devtree(void)
 444 {
 445         int rc;
 446
 447         /*
 448          * Try to find the available page sizes in the device-tree
 449          */
 450         rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
 451         if (rc != 0)  /* Found */
 452                 goto found;
 453         /*
 454          * let's assume we have page 4k and 64k support
 455          */
 456         mmu_psize_defs[MMU_PAGE_4K].shift = 12;
 457         mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
 458
 459         mmu_psize_defs[MMU_PAGE_64K].shift = 16;
 460         mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
 461 found:
 462 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 463         if (mmu_psize_defs[MMU_PAGE_2M].shift) {
 464                 /*
 465                  * map vmemmap using 2M if available
 466                  */
 467                 mmu_vmemmap_psize = MMU_PAGE_2M;
 468         }
 469 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 470         return;
 471 }
 472
 473 static void update_hid_for_radix(void)
 474 {
 475         unsigned long hid0;
 476         unsigned long rb = 3UL << PPC_BITLSHIFT(53); /* IS = 3 */
 477
 478         asm volatile("ptesync": : :"memory");
 479         /* prs = 0, ric = 2, rs = 0, r = 1 is = 3 */
 480         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 481                      : : "r"(rb), "i"(1), "i"(0), "i"(2), "r"(0) : "memory");
 482         /* prs = 1, ric = 2, rs = 0, r = 1 is = 3 */
 483         asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 484                      : : "r"(rb), "i"(1), "i"(1), "i"(2), "r"(0) : "memory");
 485         asm volatile("eieio; tlbsync; ptesync; isync; slbia": : :"memory");
 486         trace_tlbie(0, 0, rb, 0, 2, 0, 1);
 487         trace_tlbie(0, 0, rb, 0, 2, 1, 1);
 488
 489         /*
 490          * now switch the HID
 491          */
 492         hid0  = mfspr(SPRN_HID0);
 493         hid0 |= HID0_POWER9_RADIX;
 494         mtspr(SPRN_HID0, hid0);
 495         asm volatile("isync": : :"memory");
 496
 497         /* Wait for it to happen */
 498         while (!(mfspr(SPRN_HID0) & HID0_POWER9_RADIX))
 499                 cpu_relax();
 500 }
 501
 502 static void radix_init_amor(void)
 503 {
 504         /*
 505         * In HV mode, we init AMOR (Authority Mask Override Register) so that
 506         * the hypervisor and guest can setup IAMR (Instruction Authority Mask
 507         * Register), enable key 0 and set it to 1.
 508         *
 509         * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
 510         */
 511         mtspr(SPRN_AMOR, (3ul << 62));
 512 }
 513
 514 static void radix_init_iamr(void)
 515 {
 516         unsigned long iamr;
 517
 518         /*
 519          * The IAMR should set to 0 on DD1.
 520          */
 521         if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 522                 iamr = 0;
 523         else
 524                 iamr = (1ul << 62);
 525
 526         /*
 527          * Radix always uses key0 of the IAMR to determine if an access is
 528          * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
 529          * fetch.
 530          */
 531         mtspr(SPRN_IAMR, iamr);
 532 }
 533
 534 void __init radix__early_init_mmu(void)
 535 {
 536         unsigned long lpcr;
 537
 538 #ifdef CONFIG_PPC_64K_PAGES
 539         /* PAGE_SIZE mappings */
 540         mmu_virtual_psize = MMU_PAGE_64K;
 541 #else
 542         mmu_virtual_psize = MMU_PAGE_4K;
 543 #endif
 544
 545 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 546         /* vmemmap mapping */
 547         mmu_vmemmap_psize = mmu_virtual_psize;
 548 #endif
 549         /*
 550          * initialize page table size
 551          */
 552         __pte_index_size = RADIX_PTE_INDEX_SIZE;
 553         __pmd_index_size = RADIX_PMD_INDEX_SIZE;
 554         __pud_index_size = RADIX_PUD_INDEX_SIZE;
 555         __pgd_index_size = RADIX_PGD_INDEX_SIZE;
 556         __pud_cache_index = RADIX_PUD_INDEX_SIZE;
 557         __pmd_cache_index = RADIX_PMD_INDEX_SIZE;
 558         __pte_table_size = RADIX_PTE_TABLE_SIZE;
 559         __pmd_table_size = RADIX_PMD_TABLE_SIZE;
 560         __pud_table_size = RADIX_PUD_TABLE_SIZE;
 561         __pgd_table_size = RADIX_PGD_TABLE_SIZE;
 562
 563         __pmd_val_bits = RADIX_PMD_VAL_BITS;
 564         __pud_val_bits = RADIX_PUD_VAL_BITS;
 565         __pgd_val_bits = RADIX_PGD_VAL_BITS;
 566
 567         __kernel_virt_start = RADIX_KERN_VIRT_START;
 568         __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
 569         __vmalloc_start = RADIX_VMALLOC_START;
 570         __vmalloc_end = RADIX_VMALLOC_END;
 571         __kernel_io_start = RADIX_KERN_IO_START;
 572         vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
 573         ioremap_bot = IOREMAP_BASE;
 574
 575 #ifdef CONFIG_PCI
 576         pci_io_base = ISA_IO_BASE;
 577 #endif
 578
 579         /*
 580          * For now radix also use the same frag size
 581          */
 582         __pte_frag_nr = H_PTE_FRAG_NR;
 583         __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
 584
 585         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 586                 radix_init_native();
 587                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 588                         update_hid_for_radix();
 589                 lpcr = mfspr(SPRN_LPCR);
 590                 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
 591                 radix_init_partition_table();
 592                 radix_init_amor();
 593         } else {
 594                 radix_init_pseries();
 595         }
 596
 597         memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
 598
 599         radix_init_iamr();
 600         radix_init_pgtable();
 601         /* Switch to the guard PID before turning on MMU */
 602         radix__switch_mmu_context(NULL, &init_mm);
 603         if (cpu_has_feature(CPU_FTR_HVMODE))
 604                 tlbiel_all();
 605 }
 606
 607 void radix__early_init_mmu_secondary(void)
 608 {
 609         unsigned long lpcr;
 610         /*
 611          * update partition table control register and UPRT
 612          */
 613         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 614
 615                 if (cpu_has_feature(CPU_FTR_POWER9_DD1))
 616                         update_hid_for_radix();
 617
 618                 lpcr = mfspr(SPRN_LPCR);
 619                 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
 620
 621                 mtspr(SPRN_PTCR,
 622                       __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
 623                 radix_init_amor();
 624         }
 625         radix_init_iamr();
 626
 627         radix__switch_mmu_context(NULL, &init_mm);
 628         if (cpu_has_feature(CPU_FTR_HVMODE))
 629                 tlbiel_all();
 630 }
 631
 632 void radix__mmu_cleanup_all(void)
 633 {
 634         unsigned long lpcr;
 635
 636         if (!firmware_has_feature(FW_FEATURE_LPAR)) {
 637                 lpcr = mfspr(SPRN_LPCR);
 638                 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
 639                 mtspr(SPRN_PTCR, 0);
 640                 powernv_set_nmmu_ptcr(0);
 641                 radix__flush_tlb_all();
 642         }
 643 }
 644
 645 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
 646                                 phys_addr_t first_memblock_size)
 647 {
 648         /* We don't currently support the first MEMBLOCK not mapping 0
 649          * physical on those processors
 650          */
 651         BUG_ON(first_memblock_base != 0);
 652
 653         /*
 654          * Radix mode is not limited by RMA / VRMA addressing.
 655          */
 656         ppc64_rma_size = ULONG_MAX;
 657 }
 658
 659 #ifdef CONFIG_MEMORY_HOTPLUG
 660 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
 661 {
 662         pte_t *pte;
 663         int i;
 664
 665         for (i = 0; i < PTRS_PER_PTE; i++) {
 666                 pte = pte_start + i;
 667                 if (!pte_none(*pte))
 668                         return;
 669         }
 670
 671         pte_free_kernel(&init_mm, pte_start);
 672         pmd_clear(pmd);
 673 }
 674
 675 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
 676 {
 677         pmd_t *pmd;
 678         int i;
 679
 680         for (i = 0; i < PTRS_PER_PMD; i++) {
 681                 pmd = pmd_start + i;
 682                 if (!pmd_none(*pmd))
 683                         return;
 684         }
 685
 686         pmd_free(&init_mm, pmd_start);
 687         pud_clear(pud);
 688 }
 689
 690 struct change_mapping_params {
 691         pte_t *pte;
 692         unsigned long start;
 693         unsigned long end;
 694         unsigned long aligned_start;
 695         unsigned long aligned_end;
 696 };
 697
 698 static int stop_machine_change_mapping(void *data)
 699 {
 700         struct change_mapping_params *params =
 701                         (struct change_mapping_params *)data;
 702
 703         if (!data)
 704                 return -1;
 705
 706         spin_unlock(&init_mm.page_table_lock);
 707         pte_clear(&init_mm, params->aligned_start, params->pte);
 708         create_physical_mapping(params->aligned_start, params->start);
 709         create_physical_mapping(params->end, params->aligned_end);
 710         spin_lock(&init_mm.page_table_lock);
 711         return 0;
 712 }
 713
 714 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
 715                              unsigned long end)
 716 {
 717         unsigned long next;
 718         pte_t *pte;
 719
 720         pte = pte_start + pte_index(addr);
 721         for (; addr < end; addr = next, pte++) {
 722                 next = (addr + PAGE_SIZE) & PAGE_MASK;
 723                 if (next > end)
 724                         next = end;
 725
 726                 if (!pte_present(*pte))
 727                         continue;
 728
 729                 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
 730                         /*
 731                          * The vmemmap_free() and remove_section_mapping()
 732                          * codepaths call us with aligned addresses.
 733                          */
 734                         WARN_ONCE(1, "%s: unaligned range\n", __func__);
 735                         continue;
 736                 }
 737
 738                 pte_clear(&init_mm, addr, pte);
 739         }
 740 }
 741
 742 /*
 743  * clear the pte and potentially split the mapping helper
 744  */
 745 static void split_kernel_mapping(unsigned long addr, unsigned long end,
 746                                 unsigned long size, pte_t *pte)
 747 {
 748         unsigned long mask = ~(size - 1);
 749         unsigned long aligned_start = addr & mask;
 750         unsigned long aligned_end = addr + size;
 751         struct change_mapping_params params;
 752         bool split_region = false;
 753
 754         if ((end - addr) < size) {
 755                 /*
 756                  * We're going to clear the PTE, but not flushed
 757                  * the mapping, time to remap and flush. The
 758                  * effects if visible outside the processor or
 759                  * if we are running in code close to the
 760                  * mapping we cleared, we are in trouble.
 761                  */
 762                 if (overlaps_kernel_text(aligned_start, addr) ||
 763                         overlaps_kernel_text(end, aligned_end)) {
 764                         /*
 765                          * Hack, just return, don't pte_clear
 766                          */
 767                         WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
 768                                   "text, not splitting\n", addr, end);
 769                         return;
 770                 }
 771                 split_region = true;
 772         }
 773
 774         if (split_region) {
 775                 params.pte = pte;
 776                 params.start = addr;
 777                 params.end = end;
 778                 params.aligned_start = addr & ~(size - 1);
 779                 params.aligned_end = min_t(unsigned long, aligned_end,
 780                                 (unsigned long)__va(memblock_end_of_DRAM()));
 781                 stop_machine(stop_machine_change_mapping, &params, NULL);
 782                 return;
 783         }
 784
 785         pte_clear(&init_mm, addr, pte);
 786 }
 787
 788 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
 789                              unsigned long end)
 790 {
 791         unsigned long next;
 792         pte_t *pte_base;
 793         pmd_t *pmd;
 794
 795         pmd = pmd_start + pmd_index(addr);
 796         for (; addr < end; addr = next, pmd++) {
 797                 next = pmd_addr_end(addr, end);
 798
 799                 if (!pmd_present(*pmd))
 800                         continue;
 801
 802                 if (pmd_huge(*pmd)) {
 803                         split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
 804                         continue;
 805                 }
 806
 807                 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
 808                 remove_pte_table(pte_base, addr, next);
 809                 free_pte_table(pte_base, pmd);
 810         }
 811 }
 812
 813 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
 814                              unsigned long end)
 815 {
 816         unsigned long next;
 817         pmd_t *pmd_base;
 818         pud_t *pud;
 819
 820         pud = pud_start + pud_index(addr);
 821         for (; addr < end; addr = next, pud++) {
 822                 next = pud_addr_end(addr, end);
 823
 824                 if (!pud_present(*pud))
 825                         continue;
 826
 827                 if (pud_huge(*pud)) {
 828                         split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
 829                         continue;
 830                 }
 831
 832                 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
 833                 remove_pmd_table(pmd_base, addr, next);
 834                 free_pmd_table(pmd_base, pud);
 835         }
 836 }
 837
 838 static void remove_pagetable(unsigned long start, unsigned long end)
 839 {
 840         unsigned long addr, next;
 841         pud_t *pud_base;
 842         pgd_t *pgd;
 843
 844         spin_lock(&init_mm.page_table_lock);
 845
 846         for (addr = start; addr < end; addr = next) {
 847                 next = pgd_addr_end(addr, end);
 848
 849                 pgd = pgd_offset_k(addr);
 850                 if (!pgd_present(*pgd))
 851                         continue;
 852
 853                 if (pgd_huge(*pgd)) {
 854                         split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
 855                         continue;
 856                 }
 857
 858                 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
 859                 remove_pud_table(pud_base, addr, next);
 860         }
 861
 862         spin_unlock(&init_mm.page_table_lock);
 863         radix__flush_tlb_kernel_range(start, end);
 864 }
 865
 866 int __ref radix__create_section_mapping(unsigned long start, unsigned long end)
 867 {
 868         return create_physical_mapping(start, end);
 869 }
 870
 871 int radix__remove_section_mapping(unsigned long start, unsigned long end)
 872 {
 873         remove_pagetable(start, end);
 874         return 0;
 875 }
 876 #endif /* CONFIG_MEMORY_HOTPLUG */
 877
 878 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 879 int __meminit radix__vmemmap_create_mapping(unsigned long start,
 880                                       unsigned long page_size,
 881                                       unsigned long phys)
 882 {
 883         /* Create a PTE encoding */
 884         unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
 885
 886         BUG_ON(radix__map_kernel_page(start, phys, __pgprot(flags), page_size));
 887         return 0;
 888 }
 889
 890 #ifdef CONFIG_MEMORY_HOTPLUG
 891 void radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
 892 {
 893         remove_pagetable(start, start + page_size);
 894 }
 895 #endif
 896 #endif
 897
 898 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 899
 900 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
 901                                   pmd_t *pmdp, unsigned long clr,
 902                                   unsigned long set)
 903 {
 904         unsigned long old;
 905
 906 #ifdef CONFIG_DEBUG_VM
 907         WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
 908         assert_spin_locked(&mm->page_table_lock);
 909 #endif
 910
 911         old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
 912         trace_hugepage_update(addr, old, clr, set);
 913
 914         return old;
 915 }
 916
 917 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
 918                         pmd_t *pmdp)
 919
 920 {
 921         pmd_t pmd;
 922
 923         VM_BUG_ON(address & ~HPAGE_PMD_MASK);
 924         VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
 925         VM_BUG_ON(pmd_devmap(*pmdp));
 926         /*
 927          * khugepaged calls this for normal pmd
 928          */
 929         pmd = *pmdp;
 930         pmd_clear(pmdp);
 931
 932         /*FIXME!!  Verify whether we need this kick below */
 933         serialize_against_pte_lookup(vma->vm_mm);
 934
 935         radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
 936
 937         return pmd;
 938 }
 939
 940 /*
 941  * For us pgtable_t is pte_t *. Inorder to save the deposisted
 942  * page table, we consider the allocated page table as a list
 943  * head. On withdraw we need to make sure we zero out the used
 944  * list_head memory area.
 945  */
 946 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
 947                                  pgtable_t pgtable)
 948 {
 949         struct list_head *lh = (struct list_head *) pgtable;
 950
 951         assert_spin_locked(pmd_lockptr(mm, pmdp));
 952
 953         /* FIFO */
 954         if (!pmd_huge_pte(mm, pmdp))
 955                 INIT_LIST_HEAD(lh);
 956         else
 957                 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
 958         pmd_huge_pte(mm, pmdp) = pgtable;
 959 }
 960
 961 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
 962 {
 963         pte_t *ptep;
 964         pgtable_t pgtable;
 965         struct list_head *lh;
 966
 967         assert_spin_locked(pmd_lockptr(mm, pmdp));
 968
 969         /* FIFO */
 970         pgtable = pmd_huge_pte(mm, pmdp);
 971         lh = (struct list_head *) pgtable;
 972         if (list_empty(lh))
 973                 pmd_huge_pte(mm, pmdp) = NULL;
 974         else {
 975                 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
 976                 list_del(lh);
 977         }
 978         ptep = (pte_t *) pgtable;
 979         *ptep = __pte(0);
 980         ptep++;
 981         *ptep = __pte(0);
 982         return pgtable;
 983 }
 984
 985
 986 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
 987                                unsigned long addr, pmd_t *pmdp)
 988 {
 989         pmd_t old_pmd;
 990         unsigned long old;
 991
 992         old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
 993         old_pmd = __pmd(old);
 994         /*
 995          * Serialize against find_current_mm_pte which does lock-less
 996          * lookup in page tables with local interrupts disabled. For huge pages
 997          * it casts pmd_t to pte_t. Since format of pte_t is different from
 998          * pmd_t we want to prevent transit from pmd pointing to page table
 999          * to pmd pointing to huge page (and back) while interrupts are disabled.
1000          * We clear pmd to possibly replace it with page table pointer in
1001          * different code paths. So make sure we wait for the parallel
1002          * find_current_mm_pte to finish.
1003          */
1004         serialize_against_pte_lookup(mm);
1005         return old_pmd;
1006 }
1007
1008 int radix__has_transparent_hugepage(void)
1009 {
1010         /* For radix 2M at PMD level means thp */
1011         if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
1012                 return 1;
1013         return 0;
1014 }
1015 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */