?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / gpu / drm / etnaviv / etnaviv_gpu.c
blob21d0d22f11688fbaf7606faa8e7011e6ba82a932
1 /*
2 * Copyright (C) 2015 Etnaviv Project
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2 as published by
6 * the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17 #include <linux/component.h>
18 #include <linux/dma-fence.h>
19 #include <linux/moduleparam.h>
20 #include <linux/of_device.h>
21 #include <linux/thermal.h>
22
23 #include "etnaviv_cmdbuf.h"
24 #include "etnaviv_dump.h"
25 #include "etnaviv_gpu.h"
26 #include "etnaviv_gem.h"
27 #include "etnaviv_mmu.h"
28 #include "etnaviv_perfmon.h"
29 #include "common.xml.h"
30 #include "state.xml.h"
31 #include "state_hi.xml.h"
32 #include "cmdstream.xml.h"
33
34 static const struct platform_device_id gpu_ids[] = {
35 { .name = "etnaviv-gpu,2d" },
36 { },
37 };
38
39 static bool etnaviv_dump_core = true;
40 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
41
42 /*
43 * Driver functions:
44 */
45
46 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
47 {
48 switch (param) {
49 case ETNAVIV_PARAM_GPU_MODEL:
50 *value = gpu->identity.model;
51 break;
52
53 case ETNAVIV_PARAM_GPU_REVISION:
54 *value = gpu->identity.revision;
55 break;
56
57 case ETNAVIV_PARAM_GPU_FEATURES_0:
58 *value = gpu->identity.features;
59 break;
60
61 case ETNAVIV_PARAM_GPU_FEATURES_1:
62 *value = gpu->identity.minor_features0;
63 break;
64
65 case ETNAVIV_PARAM_GPU_FEATURES_2:
66 *value = gpu->identity.minor_features1;
67 break;
68
69 case ETNAVIV_PARAM_GPU_FEATURES_3:
70 *value = gpu->identity.minor_features2;
71 break;
72
73 case ETNAVIV_PARAM_GPU_FEATURES_4:
74 *value = gpu->identity.minor_features3;
75 break;
76
77 case ETNAVIV_PARAM_GPU_FEATURES_5:
78 *value = gpu->identity.minor_features4;
79 break;
80
81 case ETNAVIV_PARAM_GPU_FEATURES_6:
82 *value = gpu->identity.minor_features5;
83 break;
84
85 case ETNAVIV_PARAM_GPU_STREAM_COUNT:
86 *value = gpu->identity.stream_count;
87 break;
88
89 case ETNAVIV_PARAM_GPU_REGISTER_MAX:
90 *value = gpu->identity.register_max;
91 break;
92
93 case ETNAVIV_PARAM_GPU_THREAD_COUNT:
94 *value = gpu->identity.thread_count;
95 break;
96
97 case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
98 *value = gpu->identity.vertex_cache_size;
99 break;
100
101 case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
102 *value = gpu->identity.shader_core_count;
103 break;
104
105 case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
106 *value = gpu->identity.pixel_pipes;
107 break;
108
109 case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
110 *value = gpu->identity.vertex_output_buffer_size;
111 break;
112
113 case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
114 *value = gpu->identity.buffer_size;
115 break;
116
117 case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
118 *value = gpu->identity.instruction_count;
119 break;
120
121 case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
122 *value = gpu->identity.num_constants;
123 break;
124
125 case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
126 *value = gpu->identity.varyings_count;
127 break;
128
129 default:
130 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
131 return -EINVAL;
132 }
133
134 return 0;
135 }
136
137
138 #define etnaviv_is_model_rev(gpu, mod, rev) \
139 ((gpu)->identity.model == chipModel_##mod && \
140 (gpu)->identity.revision == rev)
141 #define etnaviv_field(val, field) \
142 (((val) & field##__MASK) >> field##__SHIFT)
143
144 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
145 {
146 if (gpu->identity.minor_features0 &
147 chipMinorFeatures0_MORE_MINOR_FEATURES) {
148 u32 specs[4];
149 unsigned int streams;
150
151 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
152 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
153 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
154 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
155
156 gpu->identity.stream_count = etnaviv_field(specs[0],
157 VIVS_HI_CHIP_SPECS_STREAM_COUNT);
158 gpu->identity.register_max = etnaviv_field(specs[0],
159 VIVS_HI_CHIP_SPECS_REGISTER_MAX);
160 gpu->identity.thread_count = etnaviv_field(specs[0],
161 VIVS_HI_CHIP_SPECS_THREAD_COUNT);
162 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
163 VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
164 gpu->identity.shader_core_count = etnaviv_field(specs[0],
165 VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
166 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
167 VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
168 gpu->identity.vertex_output_buffer_size =
169 etnaviv_field(specs[0],
170 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
171
172 gpu->identity.buffer_size = etnaviv_field(specs[1],
173 VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
174 gpu->identity.instruction_count = etnaviv_field(specs[1],
175 VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
176 gpu->identity.num_constants = etnaviv_field(specs[1],
177 VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
178
179 gpu->identity.varyings_count = etnaviv_field(specs[2],
180 VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
181
182 /* This overrides the value from older register if non-zero */
183 streams = etnaviv_field(specs[3],
184 VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
185 if (streams)
186 gpu->identity.stream_count = streams;
187 }
188
189 /* Fill in the stream count if not specified */
190 if (gpu->identity.stream_count == 0) {
191 if (gpu->identity.model >= 0x1000)
192 gpu->identity.stream_count = 4;
193 else
194 gpu->identity.stream_count = 1;
195 }
196
197 /* Convert the register max value */
198 if (gpu->identity.register_max)
199 gpu->identity.register_max = 1 << gpu->identity.register_max;
200 else if (gpu->identity.model == chipModel_GC400)
201 gpu->identity.register_max = 32;
202 else
203 gpu->identity.register_max = 64;
204
205 /* Convert thread count */
206 if (gpu->identity.thread_count)
207 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
208 else if (gpu->identity.model == chipModel_GC400)
209 gpu->identity.thread_count = 64;
210 else if (gpu->identity.model == chipModel_GC500 ||
211 gpu->identity.model == chipModel_GC530)
212 gpu->identity.thread_count = 128;
213 else
214 gpu->identity.thread_count = 256;
215
216 if (gpu->identity.vertex_cache_size == 0)
217 gpu->identity.vertex_cache_size = 8;
218
219 if (gpu->identity.shader_core_count == 0) {
220 if (gpu->identity.model >= 0x1000)
221 gpu->identity.shader_core_count = 2;
222 else
223 gpu->identity.shader_core_count = 1;
224 }
225
226 if (gpu->identity.pixel_pipes == 0)
227 gpu->identity.pixel_pipes = 1;
228
229 /* Convert virtex buffer size */
230 if (gpu->identity.vertex_output_buffer_size) {
231 gpu->identity.vertex_output_buffer_size =
232 1 << gpu->identity.vertex_output_buffer_size;
233 } else if (gpu->identity.model == chipModel_GC400) {
234 if (gpu->identity.revision < 0x4000)
235 gpu->identity.vertex_output_buffer_size = 512;
236 else if (gpu->identity.revision < 0x4200)
237 gpu->identity.vertex_output_buffer_size = 256;
238 else
239 gpu->identity.vertex_output_buffer_size = 128;
240 } else {
241 gpu->identity.vertex_output_buffer_size = 512;
242 }
243
244 switch (gpu->identity.instruction_count) {
245 case 0:
246 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
247 gpu->identity.model == chipModel_GC880)
248 gpu->identity.instruction_count = 512;
249 else
250 gpu->identity.instruction_count = 256;
251 break;
252
253 case 1:
254 gpu->identity.instruction_count = 1024;
255 break;
256
257 case 2:
258 gpu->identity.instruction_count = 2048;
259 break;
260
261 default:
262 gpu->identity.instruction_count = 256;
263 break;
264 }
265
266 if (gpu->identity.num_constants == 0)
267 gpu->identity.num_constants = 168;
268
269 if (gpu->identity.varyings_count == 0) {
270 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
271 gpu->identity.varyings_count = 12;
272 else
273 gpu->identity.varyings_count = 8;
274 }
275
276 /*
277 * For some cores, two varyings are consumed for position, so the
278 * maximum varying count needs to be reduced by one.
279 */
280 if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
281 etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
282 etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
283 etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
284 etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
285 etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
286 etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
287 etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
288 etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
289 etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
290 etnaviv_is_model_rev(gpu, GC880, 0x5106))
291 gpu->identity.varyings_count -= 1;
292 }
293
294 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
295 {
296 u32 chipIdentity;
297
298 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
299
300 /* Special case for older graphic cores. */
301 if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
302 gpu->identity.model = chipModel_GC500;
303 gpu->identity.revision = etnaviv_field(chipIdentity,
304 VIVS_HI_CHIP_IDENTITY_REVISION);
305 } else {
306
307 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
308 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
309
310 /*
311 * !!!! HACK ALERT !!!!
312 * Because people change device IDs without letting software
313 * know about it - here is the hack to make it all look the
314 * same. Only for GC400 family.
315 */
316 if ((gpu->identity.model & 0xff00) == 0x0400 &&
317 gpu->identity.model != chipModel_GC420) {
318 gpu->identity.model = gpu->identity.model & 0x0400;
319 }
320
321 /* Another special case */
322 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
323 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
324 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
325
326 if (chipDate == 0x20080814 && chipTime == 0x12051100) {
327 /*
328 * This IP has an ECO; put the correct
329 * revision in it.
330 */
331 gpu->identity.revision = 0x1051;
332 }
333 }
334
335 /*
336 * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
337 * reality it's just a re-branded GC3000. We can identify this
338 * core by the upper half of the revision register being all 1.
339 * Fix model/rev here, so all other places can refer to this
340 * core by its real identity.
341 */
342 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
343 gpu->identity.model = chipModel_GC3000;
344 gpu->identity.revision &= 0xffff;
345 }
346 }
347
348 dev_info(gpu->dev, "model: GC%x, revision: %x\n",
349 gpu->identity.model, gpu->identity.revision);
350
351 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
352
353 /* Disable fast clear on GC700. */
354 if (gpu->identity.model == chipModel_GC700)
355 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
356
357 if ((gpu->identity.model == chipModel_GC500 &&
358 gpu->identity.revision < 2) ||
359 (gpu->identity.model == chipModel_GC300 &&
360 gpu->identity.revision < 0x2000)) {
361
362 /*
363 * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
364 * registers.
365 */
366 gpu->identity.minor_features0 = 0;
367 gpu->identity.minor_features1 = 0;
368 gpu->identity.minor_features2 = 0;
369 gpu->identity.minor_features3 = 0;
370 gpu->identity.minor_features4 = 0;
371 gpu->identity.minor_features5 = 0;
372 } else
373 gpu->identity.minor_features0 =
374 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
375
376 if (gpu->identity.minor_features0 &
377 chipMinorFeatures0_MORE_MINOR_FEATURES) {
378 gpu->identity.minor_features1 =
379 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
380 gpu->identity.minor_features2 =
381 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
382 gpu->identity.minor_features3 =
383 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
384 gpu->identity.minor_features4 =
385 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
386 gpu->identity.minor_features5 =
387 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
388 }
389
390 /* GC600 idle register reports zero bits where modules aren't present */
391 if (gpu->identity.model == chipModel_GC600) {
392 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
393 VIVS_HI_IDLE_STATE_RA |
394 VIVS_HI_IDLE_STATE_SE |
395 VIVS_HI_IDLE_STATE_PA |
396 VIVS_HI_IDLE_STATE_SH |
397 VIVS_HI_IDLE_STATE_PE |
398 VIVS_HI_IDLE_STATE_DE |
399 VIVS_HI_IDLE_STATE_FE;
400 } else {
401 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
402 }
403
404 etnaviv_hw_specs(gpu);
405 }
406
407 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
408 {
409 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
410 VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
411 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
412 }
413
414 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
415 {
416 if (gpu->identity.minor_features2 &
417 chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
418 clk_set_rate(gpu->clk_core,
419 gpu->base_rate_core >> gpu->freq_scale);
420 clk_set_rate(gpu->clk_shader,
421 gpu->base_rate_shader >> gpu->freq_scale);
422 } else {
423 unsigned int fscale = 1 << (6 - gpu->freq_scale);
424 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
425
426 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
427 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
428 etnaviv_gpu_load_clock(gpu, clock);
429 }
430 }
431
432 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
433 {
434 u32 control, idle;
435 unsigned long timeout;
436 bool failed = true;
437
438 /* We hope that the GPU resets in under one second */
439 timeout = jiffies + msecs_to_jiffies(1000);
440
441 while (time_is_after_jiffies(timeout)) {
442 /* enable clock */
443 unsigned int fscale = 1 << (6 - gpu->freq_scale);
444 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
445 etnaviv_gpu_load_clock(gpu, control);
446
447 /* isolate the GPU. */
448 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
449 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
450
451 /* set soft reset. */
452 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
453 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
454
455 /* wait for reset. */
456 usleep_range(10, 20);
457
458 /* reset soft reset bit. */
459 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
460 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
461
462 /* reset GPU isolation. */
463 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
464 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
465
466 /* read idle register. */
467 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
468
469 /* try reseting again if FE it not idle */
470 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
471 dev_dbg(gpu->dev, "FE is not idle\n");
472 continue;
473 }
474
475 /* read reset register. */
476 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
477
478 /* is the GPU idle? */
479 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
480 ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
481 dev_dbg(gpu->dev, "GPU is not idle\n");
482 continue;
483 }
484
485 /* disable debug registers, as they are not normally needed */
486 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
487 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
488
489 failed = false;
490 break;
491 }
492
493 if (failed) {
494 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
495 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
496
497 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
498 idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
499 control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
500 control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
501
502 return -EBUSY;
503 }
504
505 /* We rely on the GPU running, so program the clock */
506 etnaviv_gpu_update_clock(gpu);
507
508 return 0;
509 }
510
511 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
512 {
513 u32 pmc, ppc;
514
515 /* enable clock gating */
516 ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
517 ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
518
519 /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
520 if (gpu->identity.revision == 0x4301 ||
521 gpu->identity.revision == 0x4302)
522 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
523
524 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
525
526 pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
527
528 /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
529 if (gpu->identity.model >= chipModel_GC400 &&
530 gpu->identity.model != chipModel_GC420 &&
531 !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
532 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
533
534 /*
535 * Disable PE clock gating on revs < 5.0.0.0 when HZ is
536 * present without a bug fix.
537 */
538 if (gpu->identity.revision < 0x5000 &&
539 gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
540 !(gpu->identity.minor_features1 &
541 chipMinorFeatures1_DISABLE_PE_GATING))
542 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
543
544 if (gpu->identity.revision < 0x5422)
545 pmc |= BIT(15); /* Unknown bit */
546
547 /* Disable TX clock gating on affected core revisions. */
548 if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
549 etnaviv_is_model_rev(gpu, GC2000, 0x5108))
550 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
551
552 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
553 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
554
555 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
556 }
557
558 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
559 {
560 gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
561 gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
562 VIVS_FE_COMMAND_CONTROL_ENABLE |
563 VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
564 }
565
566 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
567 {
568 /*
569 * Base value for VIVS_PM_PULSE_EATER register on models where it
570 * cannot be read, extracted from vivante kernel driver.
571 */
572 u32 pulse_eater = 0x01590880;
573
574 if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
575 etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
576 pulse_eater |= BIT(23);
577
578 }
579
580 if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
581 etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
582 pulse_eater &= ~BIT(16);
583 pulse_eater |= BIT(17);
584 }
585
586 if ((gpu->identity.revision > 0x5420) &&
587 (gpu->identity.features & chipFeatures_PIPE_3D))
588 {
589 /* Performance fix: disable internal DFS */
590 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
591 pulse_eater |= BIT(18);
592 }
593
594 gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
595 }
596
597 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
598 {
599 u16 prefetch;
600
601 if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
602 etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
603 gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
604 u32 mc_memory_debug;
605
606 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
607
608 if (gpu->identity.revision == 0x5007)
609 mc_memory_debug |= 0x0c;
610 else
611 mc_memory_debug |= 0x08;
612
613 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
614 }
615
616 /* enable module-level clock gating */
617 etnaviv_gpu_enable_mlcg(gpu);
618
619 /*
620 * Update GPU AXI cache atttribute to "cacheable, no allocate".
621 * This is necessary to prevent the iMX6 SoC locking up.
622 */
623 gpu_write(gpu, VIVS_HI_AXI_CONFIG,
624 VIVS_HI_AXI_CONFIG_AWCACHE(2) |
625 VIVS_HI_AXI_CONFIG_ARCACHE(2));
626
627 /* GC2000 rev 5108 needs a special bus config */
628 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
629 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
630 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
631 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
632 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
633 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
634 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
635 }
636
637 /* setup the pulse eater */
638 etnaviv_gpu_setup_pulse_eater(gpu);
639
640 /* setup the MMU */
641 etnaviv_iommu_restore(gpu);
642
643 /* Start command processor */
644 prefetch = etnaviv_buffer_init(gpu);
645
646 gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
647 etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
648 prefetch);
649 }
650
651 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
652 {
653 int ret, i;
654
655 ret = pm_runtime_get_sync(gpu->dev);
656 if (ret < 0) {
657 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
658 return ret;
659 }
660
661 etnaviv_hw_identify(gpu);
662
663 if (gpu->identity.model == 0) {
664 dev_err(gpu->dev, "Unknown GPU model\n");
665 ret = -ENXIO;
666 goto fail;
667 }
668
669 /* Exclude VG cores with FE2.0 */
670 if (gpu->identity.features & chipFeatures_PIPE_VG &&
671 gpu->identity.features & chipFeatures_FE20) {
672 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
673 ret = -ENXIO;
674 goto fail;
675 }
676
677 /*
678 * Set the GPU linear window to be at the end of the DMA window, where
679 * the CMA area is likely to reside. This ensures that we are able to
680 * map the command buffers while having the linear window overlap as
681 * much RAM as possible, so we can optimize mappings for other buffers.
682 *
683 * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
684 * to different views of the memory on the individual engines.
685 */
686 if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
687 (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
688 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
689 if (dma_mask < PHYS_OFFSET + SZ_2G)
690 gpu->memory_base = PHYS_OFFSET;
691 else
692 gpu->memory_base = dma_mask - SZ_2G + 1;
693 } else if (PHYS_OFFSET >= SZ_2G) {
694 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
695 gpu->memory_base = PHYS_OFFSET;
696 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
697 }
698
699 ret = etnaviv_hw_reset(gpu);
700 if (ret) {
701 dev_err(gpu->dev, "GPU reset failed\n");
702 goto fail;
703 }
704
705 gpu->mmu = etnaviv_iommu_new(gpu);
706 if (IS_ERR(gpu->mmu)) {
707 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
708 ret = PTR_ERR(gpu->mmu);
709 goto fail;
710 }
711
712 gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
713 if (IS_ERR(gpu->cmdbuf_suballoc)) {
714 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
715 ret = PTR_ERR(gpu->cmdbuf_suballoc);
716 goto fail;
717 }
718
719 /* Create buffer: */
720 ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
721 PAGE_SIZE);
722 if (ret) {
723 dev_err(gpu->dev, "could not create command buffer\n");
724 goto destroy_iommu;
725 }
726
727 if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
728 etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
729 ret = -EINVAL;
730 dev_err(gpu->dev,
731 "command buffer outside valid memory window\n");
732 goto free_buffer;
733 }
734
735 /* Setup event management */
736 spin_lock_init(&gpu->event_spinlock);
737 init_completion(&gpu->event_free);
738 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
739 for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
740 complete(&gpu->event_free);
741
742 /* Now program the hardware */
743 mutex_lock(&gpu->lock);
744 etnaviv_gpu_hw_init(gpu);
745 gpu->exec_state = -1;
746 mutex_unlock(&gpu->lock);
747
748 pm_runtime_mark_last_busy(gpu->dev);
749 pm_runtime_put_autosuspend(gpu->dev);
750
751 return 0;
752
753 free_buffer:
754 etnaviv_cmdbuf_free(&gpu->buffer);
755 destroy_iommu:
756 etnaviv_iommu_destroy(gpu->mmu);
757 gpu->mmu = NULL;
758 fail:
759 pm_runtime_mark_last_busy(gpu->dev);
760 pm_runtime_put_autosuspend(gpu->dev);
761
762 return ret;
763 }
764
765 #ifdef CONFIG_DEBUG_FS
766 struct dma_debug {
767 u32 address[2];
768 u32 state[2];
769 };
770
771 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
772 {
773 u32 i;
774
775 debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
776 debug->state[0] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
777
778 for (i = 0; i < 500; i++) {
779 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
780 debug->state[1] = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
781
782 if (debug->address[0] != debug->address[1])
783 break;
784
785 if (debug->state[0] != debug->state[1])
786 break;
787 }
788 }
789
790 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
791 {
792 struct dma_debug debug;
793 u32 dma_lo, dma_hi, axi, idle;
794 int ret;
795
796 seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
797
798 ret = pm_runtime_get_sync(gpu->dev);
799 if (ret < 0)
800 return ret;
801
802 dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
803 dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
804 axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
805 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
806
807 verify_dma(gpu, &debug);
808
809 seq_puts(m, "\tfeatures\n");
810 seq_printf(m, "\t minor_features0: 0x%08x\n",
811 gpu->identity.minor_features0);
812 seq_printf(m, "\t minor_features1: 0x%08x\n",
813 gpu->identity.minor_features1);
814 seq_printf(m, "\t minor_features2: 0x%08x\n",
815 gpu->identity.minor_features2);
816 seq_printf(m, "\t minor_features3: 0x%08x\n",
817 gpu->identity.minor_features3);
818 seq_printf(m, "\t minor_features4: 0x%08x\n",
819 gpu->identity.minor_features4);
820 seq_printf(m, "\t minor_features5: 0x%08x\n",
821 gpu->identity.minor_features5);
822
823 seq_puts(m, "\tspecs\n");
824 seq_printf(m, "\t stream_count: %d\n",
825 gpu->identity.stream_count);
826 seq_printf(m, "\t register_max: %d\n",
827 gpu->identity.register_max);
828 seq_printf(m, "\t thread_count: %d\n",
829 gpu->identity.thread_count);
830 seq_printf(m, "\t vertex_cache_size: %d\n",
831 gpu->identity.vertex_cache_size);
832 seq_printf(m, "\t shader_core_count: %d\n",
833 gpu->identity.shader_core_count);
834 seq_printf(m, "\t pixel_pipes: %d\n",
835 gpu->identity.pixel_pipes);
836 seq_printf(m, "\t vertex_output_buffer_size: %d\n",
837 gpu->identity.vertex_output_buffer_size);
838 seq_printf(m, "\t buffer_size: %d\n",
839 gpu->identity.buffer_size);
840 seq_printf(m, "\t instruction_count: %d\n",
841 gpu->identity.instruction_count);
842 seq_printf(m, "\t num_constants: %d\n",
843 gpu->identity.num_constants);
844 seq_printf(m, "\t varyings_count: %d\n",
845 gpu->identity.varyings_count);
846
847 seq_printf(m, "\taxi: 0x%08x\n", axi);
848 seq_printf(m, "\tidle: 0x%08x\n", idle);
849 idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
850 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
851 seq_puts(m, "\t FE is not idle\n");
852 if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
853 seq_puts(m, "\t DE is not idle\n");
854 if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
855 seq_puts(m, "\t PE is not idle\n");
856 if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
857 seq_puts(m, "\t SH is not idle\n");
858 if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
859 seq_puts(m, "\t PA is not idle\n");
860 if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
861 seq_puts(m, "\t SE is not idle\n");
862 if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
863 seq_puts(m, "\t RA is not idle\n");
864 if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
865 seq_puts(m, "\t TX is not idle\n");
866 if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
867 seq_puts(m, "\t VG is not idle\n");
868 if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
869 seq_puts(m, "\t IM is not idle\n");
870 if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
871 seq_puts(m, "\t FP is not idle\n");
872 if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
873 seq_puts(m, "\t TS is not idle\n");
874 if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
875 seq_puts(m, "\t AXI low power mode\n");
876
877 if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
878 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
879 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
880 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
881
882 seq_puts(m, "\tMC\n");
883 seq_printf(m, "\t read0: 0x%08x\n", read0);
884 seq_printf(m, "\t read1: 0x%08x\n", read1);
885 seq_printf(m, "\t write: 0x%08x\n", write);
886 }
887
888 seq_puts(m, "\tDMA ");
889
890 if (debug.address[0] == debug.address[1] &&
891 debug.state[0] == debug.state[1]) {
892 seq_puts(m, "seems to be stuck\n");
893 } else if (debug.address[0] == debug.address[1]) {
894 seq_puts(m, "address is constant\n");
895 } else {
896 seq_puts(m, "is running\n");
897 }
898
899 seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
900 seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
901 seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
902 seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
903 seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
904 dma_lo, dma_hi);
905
906 ret = 0;
907
908 pm_runtime_mark_last_busy(gpu->dev);
909 pm_runtime_put_autosuspend(gpu->dev);
910
911 return ret;
912 }
913 #endif
914
915 /*
916 * Hangcheck detection for locked gpu:
917 */
918 static void recover_worker(struct work_struct *work)
919 {
920 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
921 recover_work);
922 unsigned long flags;
923 unsigned int i = 0;
924
925 dev_err(gpu->dev, "hangcheck recover!\n");
926
927 if (pm_runtime_get_sync(gpu->dev) < 0)
928 return;
929
930 mutex_lock(&gpu->lock);
931
932 /* Only catch the first event, or when manually re-armed */
933 if (etnaviv_dump_core) {
934 etnaviv_core_dump(gpu);
935 etnaviv_dump_core = false;
936 }
937
938 etnaviv_hw_reset(gpu);
939
940 /* complete all events, the GPU won't do it after the reset */
941 spin_lock_irqsave(&gpu->event_spinlock, flags);
942 for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS) {
943 dma_fence_signal(gpu->event[i].fence);
944 gpu->event[i].fence = NULL;
945 complete(&gpu->event_free);
946 }
947 bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
948 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
949 gpu->completed_fence = gpu->active_fence;
950
951 etnaviv_gpu_hw_init(gpu);
952 gpu->lastctx = NULL;
953 gpu->exec_state = -1;
954
955 mutex_unlock(&gpu->lock);
956 pm_runtime_mark_last_busy(gpu->dev);
957 pm_runtime_put_autosuspend(gpu->dev);
958
959 /* Retire the buffer objects in a work */
960 queue_work(gpu->wq, &gpu->retire_work);
961 }
962
963 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
964 {
965 DBG("%s", dev_name(gpu->dev));
966 mod_timer(&gpu->hangcheck_timer,
967 round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
968 }
969
970 static void hangcheck_handler(struct timer_list *t)
971 {
972 struct etnaviv_gpu *gpu = from_timer(gpu, t, hangcheck_timer);
973 u32 fence = gpu->completed_fence;
974 bool progress = false;
975
976 if (fence != gpu->hangcheck_fence) {
977 gpu->hangcheck_fence = fence;
978 progress = true;
979 }
980
981 if (!progress) {
982 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
983 int change = dma_addr - gpu->hangcheck_dma_addr;
984
985 if (change < 0 || change > 16) {
986 gpu->hangcheck_dma_addr = dma_addr;
987 progress = true;
988 }
989 }
990
991 if (!progress && fence_after(gpu->active_fence, fence)) {
992 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
993 dev_err(gpu->dev, " completed fence: %u\n", fence);
994 dev_err(gpu->dev, " active fence: %u\n",
995 gpu->active_fence);
996 queue_work(gpu->wq, &gpu->recover_work);
997 }
998
999 /* if still more pending work, reset the hangcheck timer: */
1000 if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
1001 hangcheck_timer_reset(gpu);
1002 }
1003
1004 static void hangcheck_disable(struct etnaviv_gpu *gpu)
1005 {
1006 del_timer_sync(&gpu->hangcheck_timer);
1007 cancel_work_sync(&gpu->recover_work);
1008 }
1009
1010 /* fence object management */
1011 struct etnaviv_fence {
1012 struct etnaviv_gpu *gpu;
1013 struct dma_fence base;
1014 };
1015
1016 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1017 {
1018 return container_of(fence, struct etnaviv_fence, base);
1019 }
1020
1021 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1022 {
1023 return "etnaviv";
1024 }
1025
1026 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1027 {
1028 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1029
1030 return dev_name(f->gpu->dev);
1031 }
1032
1033 static bool etnaviv_fence_enable_signaling(struct dma_fence *fence)
1034 {
1035 return true;
1036 }
1037
1038 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1039 {
1040 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1041
1042 return fence_completed(f->gpu, f->base.seqno);
1043 }
1044
1045 static void etnaviv_fence_release(struct dma_fence *fence)
1046 {
1047 struct etnaviv_fence *f = to_etnaviv_fence(fence);
1048
1049 kfree_rcu(f, base.rcu);
1050 }
1051
1052 static const struct dma_fence_ops etnaviv_fence_ops = {
1053 .get_driver_name = etnaviv_fence_get_driver_name,
1054 .get_timeline_name = etnaviv_fence_get_timeline_name,
1055 .enable_signaling = etnaviv_fence_enable_signaling,
1056 .signaled = etnaviv_fence_signaled,
1057 .wait = dma_fence_default_wait,
1058 .release = etnaviv_fence_release,
1059 };
1060
1061 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1062 {
1063 struct etnaviv_fence *f;
1064
1065 /*
1066 * GPU lock must already be held, otherwise fence completion order might
1067 * not match the seqno order assigned here.
1068 */
1069 lockdep_assert_held(&gpu->lock);
1070
1071 f = kzalloc(sizeof(*f), GFP_KERNEL);
1072 if (!f)
1073 return NULL;
1074
1075 f->gpu = gpu;
1076
1077 dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1078 gpu->fence_context, ++gpu->next_fence);
1079
1080 return &f->base;
1081 }
1082
1083 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1084 unsigned int context, bool exclusive, bool explicit)
1085 {
1086 struct reservation_object *robj = etnaviv_obj->resv;
1087 struct reservation_object_list *fobj;
1088 struct dma_fence *fence;
1089 int i, ret;
1090
1091 if (!exclusive) {
1092 ret = reservation_object_reserve_shared(robj);
1093 if (ret)
1094 return ret;
1095 }
1096
1097 if (explicit)
1098 return 0;
1099
1100 /*
1101 * If we have any shared fences, then the exclusive fence
1102 * should be ignored as it will already have been signalled.
1103 */
1104 fobj = reservation_object_get_list(robj);
1105 if (!fobj || fobj->shared_count == 0) {
1106 /* Wait on any existing exclusive fence which isn't our own */
1107 fence = reservation_object_get_excl(robj);
1108 if (fence && fence->context != context) {
1109 ret = dma_fence_wait(fence, true);
1110 if (ret)
1111 return ret;
1112 }
1113 }
1114
1115 if (!exclusive || !fobj)
1116 return 0;
1117
1118 for (i = 0; i < fobj->shared_count; i++) {
1119 fence = rcu_dereference_protected(fobj->shared[i],
1120 reservation_object_held(robj));
1121 if (fence->context != context) {
1122 ret = dma_fence_wait(fence, true);
1123 if (ret)
1124 return ret;
1125 }
1126 }
1127
1128 return 0;
1129 }
1130
1131 /*
1132 * event management:
1133 */
1134
1135 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1136 unsigned int *events)
1137 {
1138 unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
1139 unsigned i, acquired = 0;
1140
1141 for (i = 0; i < nr_events; i++) {
1142 unsigned long ret;
1143
1144 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1145
1146 if (!ret) {
1147 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1148 goto out;
1149 }
1150
1151 acquired++;
1152 timeout = ret;
1153 }
1154
1155 spin_lock_irqsave(&gpu->event_spinlock, flags);
1156
1157 for (i = 0; i < nr_events; i++) {
1158 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1159
1160 events[i] = event;
1161 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1162 set_bit(event, gpu->event_bitmap);
1163 }
1164
1165 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1166
1167 return 0;
1168
1169 out:
1170 for (i = 0; i < acquired; i++)
1171 complete(&gpu->event_free);
1172
1173 return -EBUSY;
1174 }
1175
1176 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1177 {
1178 unsigned long flags;
1179
1180 spin_lock_irqsave(&gpu->event_spinlock, flags);
1181
1182 if (!test_bit(event, gpu->event_bitmap)) {
1183 dev_warn(gpu->dev, "event %u is already marked as free",
1184 event);
1185 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1186 } else {
1187 clear_bit(event, gpu->event_bitmap);
1188 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1189
1190 complete(&gpu->event_free);
1191 }
1192 }
1193
1194 /*
1195 * Cmdstream submission/retirement:
1196 */
1197
1198 static void retire_worker(struct work_struct *work)
1199 {
1200 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1201 retire_work);
1202 u32 fence = gpu->completed_fence;
1203 struct etnaviv_gem_submit *submit, *tmp;
1204 LIST_HEAD(retire_list);
1205
1206 mutex_lock(&gpu->lock);
1207 list_for_each_entry_safe(submit, tmp, &gpu->active_submit_list, node) {
1208 if (!dma_fence_is_signaled(submit->out_fence))
1209 break;
1210
1211 list_move(&submit->node, &retire_list);
1212 }
1213
1214 gpu->retired_fence = fence;
1215
1216 mutex_unlock(&gpu->lock);
1217
1218 list_for_each_entry_safe(submit, tmp, &retire_list, node)
1219 etnaviv_submit_put(submit);
1220 }
1221
1222 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1223 u32 fence, struct timespec *timeout)
1224 {
1225 int ret;
1226
1227 if (fence_after(fence, gpu->next_fence)) {
1228 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1229 fence, gpu->next_fence);
1230 return -EINVAL;
1231 }
1232
1233 if (!timeout) {
1234 /* No timeout was requested: just test for completion */
1235 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1236 } else {
1237 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1238
1239 ret = wait_event_interruptible_timeout(gpu->fence_event,
1240 fence_completed(gpu, fence),
1241 remaining);
1242 if (ret == 0) {
1243 DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1244 fence, gpu->retired_fence,
1245 gpu->completed_fence);
1246 ret = -ETIMEDOUT;
1247 } else if (ret != -ERESTARTSYS) {
1248 ret = 0;
1249 }
1250 }
1251
1252 return ret;
1253 }
1254
1255 /*
1256 * Wait for an object to become inactive. This, on it's own, is not race
1257 * free: the object is moved by the retire worker off the active list, and
1258 * then the iova is put. Moreover, the object could be re-submitted just
1259 * after we notice that it's become inactive.
1260 *
1261 * Although the retirement happens under the gpu lock, we don't want to hold
1262 * that lock in this function while waiting.
1263 */
1264 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1265 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1266 {
1267 unsigned long remaining;
1268 long ret;
1269
1270 if (!timeout)
1271 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1272
1273 remaining = etnaviv_timeout_to_jiffies(timeout);
1274
1275 ret = wait_event_interruptible_timeout(gpu->fence_event,
1276 !is_active(etnaviv_obj),
1277 remaining);
1278 if (ret > 0)
1279 return 0;
1280 else if (ret == -ERESTARTSYS)
1281 return -ERESTARTSYS;
1282 else
1283 return -ETIMEDOUT;
1284 }
1285
1286 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1287 struct etnaviv_event *event, unsigned int flags)
1288 {
1289 const struct etnaviv_gem_submit *submit = event->submit;
1290 unsigned int i;
1291
1292 for (i = 0; i < submit->nr_pmrs; i++) {
1293 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1294
1295 if (pmr->flags == flags)
1296 etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1297 }
1298 }
1299
1300 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1301 struct etnaviv_event *event)
1302 {
1303 u32 val;
1304
1305 /* disable clock gating */
1306 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1307 val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1308 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1309
1310 /* enable debug register */
1311 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1312 val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1313 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1314
1315 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1316 }
1317
1318 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1319 struct etnaviv_event *event)
1320 {
1321 const struct etnaviv_gem_submit *submit = event->submit;
1322 unsigned int i;
1323 u32 val;
1324
1325 sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1326
1327 for (i = 0; i < submit->nr_pmrs; i++) {
1328 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1329
1330 *pmr->bo_vma = pmr->sequence;
1331 }
1332
1333 /* disable debug register */
1334 val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1335 val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1336 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1337
1338 /* enable clock gating */
1339 val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1340 val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1341 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1342 }
1343
1344
1345 /* add bo's to gpu's ring, and kick gpu: */
1346 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1347 struct etnaviv_gem_submit *submit)
1348 {
1349 unsigned int i, nr_events = 1, event[3];
1350 int ret;
1351
1352 ret = pm_runtime_get_sync(gpu->dev);
1353 if (ret < 0)
1354 return ret;
1355 submit->runtime_resumed = true;
1356
1357 /*
1358 * if there are performance monitor requests we need to have
1359 * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1360 * requests.
1361 * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1362 * and update the sequence number for userspace.
1363 */
1364 if (submit->nr_pmrs)
1365 nr_events = 3;
1366
1367 ret = event_alloc(gpu, nr_events, event);
1368 if (ret) {
1369 DRM_ERROR("no free events\n");
1370 return ret;
1371 }
1372
1373 mutex_lock(&gpu->lock);
1374
1375 submit->out_fence = etnaviv_gpu_fence_alloc(gpu);
1376 if (!submit->out_fence) {
1377 for (i = 0; i < nr_events; i++)
1378 event_free(gpu, event[i]);
1379
1380 ret = -ENOMEM;
1381 goto out_unlock;
1382 }
1383
1384 gpu->active_fence = submit->out_fence->seqno;
1385
1386 if (submit->nr_pmrs) {
1387 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1388 kref_get(&submit->refcount);
1389 gpu->event[event[1]].submit = submit;
1390 etnaviv_sync_point_queue(gpu, event[1]);
1391 }
1392
1393 kref_get(&submit->refcount);
1394 gpu->event[event[0]].fence = submit->out_fence;
1395 etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1396 &submit->cmdbuf);
1397
1398 if (submit->nr_pmrs) {
1399 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1400 kref_get(&submit->refcount);
1401 gpu->event[event[2]].submit = submit;
1402 etnaviv_sync_point_queue(gpu, event[2]);
1403 }
1404
1405 list_add_tail(&submit->node, &gpu->active_submit_list);
1406
1407 hangcheck_timer_reset(gpu);
1408 ret = 0;
1409
1410 out_unlock:
1411 mutex_unlock(&gpu->lock);
1412
1413 return ret;
1414 }
1415
1416 static void sync_point_worker(struct work_struct *work)
1417 {
1418 struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1419 sync_point_work);
1420 struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1421 u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1422
1423 event->sync_point(gpu, event);
1424 etnaviv_submit_put(event->submit);
1425 event_free(gpu, gpu->sync_point_event);
1426
1427 /* restart FE last to avoid GPU and IRQ racing against this worker */
1428 etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1429 }
1430
1431 /*
1432 * Init/Cleanup:
1433 */
1434 static irqreturn_t irq_handler(int irq, void *data)
1435 {
1436 struct etnaviv_gpu *gpu = data;
1437 irqreturn_t ret = IRQ_NONE;
1438
1439 u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1440
1441 if (intr != 0) {
1442 int event;
1443
1444 pm_runtime_mark_last_busy(gpu->dev);
1445
1446 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1447
1448 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1449 dev_err(gpu->dev, "AXI bus error\n");
1450 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1451 }
1452
1453 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1454 int i;
1455
1456 dev_err_ratelimited(gpu->dev,
1457 "MMU fault status 0x%08x\n",
1458 gpu_read(gpu, VIVS_MMUv2_STATUS));
1459 for (i = 0; i < 4; i++) {
1460 dev_err_ratelimited(gpu->dev,
1461 "MMU %d fault addr 0x%08x\n",
1462 i, gpu_read(gpu,
1463 VIVS_MMUv2_EXCEPTION_ADDR(i)));
1464 }
1465 intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1466 }
1467
1468 while ((event = ffs(intr)) != 0) {
1469 struct dma_fence *fence;
1470
1471 event -= 1;
1472
1473 intr &= ~(1 << event);
1474
1475 dev_dbg(gpu->dev, "event %u\n", event);
1476
1477 if (gpu->event[event].sync_point) {
1478 gpu->sync_point_event = event;
1479 queue_work(gpu->wq, &gpu->sync_point_work);
1480 }
1481
1482 fence = gpu->event[event].fence;
1483 if (!fence)
1484 continue;
1485
1486 gpu->event[event].fence = NULL;
1487 dma_fence_signal(fence);
1488
1489 /*
1490 * Events can be processed out of order. Eg,
1491 * - allocate and queue event 0
1492 * - allocate event 1
1493 * - event 0 completes, we process it
1494 * - allocate and queue event 0
1495 * - event 1 and event 0 complete
1496 * we can end up processing event 0 first, then 1.
1497 */
1498 if (fence_after(fence->seqno, gpu->completed_fence))
1499 gpu->completed_fence = fence->seqno;
1500
1501 event_free(gpu, event);
1502 }
1503
1504 /* Retire the buffer objects in a work */
1505 queue_work(gpu->wq, &gpu->retire_work);
1506
1507 ret = IRQ_HANDLED;
1508 }
1509
1510 return ret;
1511 }
1512
1513 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1514 {
1515 int ret;
1516
1517 if (gpu->clk_bus) {
1518 ret = clk_prepare_enable(gpu->clk_bus);
1519 if (ret)
1520 return ret;
1521 }
1522
1523 if (gpu->clk_core) {
1524 ret = clk_prepare_enable(gpu->clk_core);
1525 if (ret)
1526 goto disable_clk_bus;
1527 }
1528
1529 if (gpu->clk_shader) {
1530 ret = clk_prepare_enable(gpu->clk_shader);
1531 if (ret)
1532 goto disable_clk_core;
1533 }
1534
1535 return 0;
1536
1537 disable_clk_core:
1538 if (gpu->clk_core)
1539 clk_disable_unprepare(gpu->clk_core);
1540 disable_clk_bus:
1541 if (gpu->clk_bus)
1542 clk_disable_unprepare(gpu->clk_bus);
1543
1544 return ret;
1545 }
1546
1547 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1548 {
1549 if (gpu->clk_shader)
1550 clk_disable_unprepare(gpu->clk_shader);
1551 if (gpu->clk_core)
1552 clk_disable_unprepare(gpu->clk_core);
1553 if (gpu->clk_bus)
1554 clk_disable_unprepare(gpu->clk_bus);
1555
1556 return 0;
1557 }
1558
1559 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1560 {
1561 unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1562
1563 do {
1564 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1565
1566 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1567 return 0;
1568
1569 if (time_is_before_jiffies(timeout)) {
1570 dev_warn(gpu->dev,
1571 "timed out waiting for idle: idle=0x%x\n",
1572 idle);
1573 return -ETIMEDOUT;
1574 }
1575
1576 udelay(5);
1577 } while (1);
1578 }
1579
1580 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1581 {
1582 if (gpu->buffer.suballoc) {
1583 /* Replace the last WAIT with END */
1584 mutex_lock(&gpu->lock);
1585 etnaviv_buffer_end(gpu);
1586 mutex_unlock(&gpu->lock);
1587
1588 /*
1589 * We know that only the FE is busy here, this should
1590 * happen quickly (as the WAIT is only 200 cycles). If
1591 * we fail, just warn and continue.
1592 */
1593 etnaviv_gpu_wait_idle(gpu, 100);
1594 }
1595
1596 return etnaviv_gpu_clk_disable(gpu);
1597 }
1598
1599 #ifdef CONFIG_PM
1600 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1601 {
1602 int ret;
1603
1604 ret = mutex_lock_killable(&gpu->lock);
1605 if (ret)
1606 return ret;
1607
1608 etnaviv_gpu_update_clock(gpu);
1609 etnaviv_gpu_hw_init(gpu);
1610
1611 gpu->lastctx = NULL;
1612 gpu->exec_state = -1;
1613
1614 mutex_unlock(&gpu->lock);
1615
1616 return 0;
1617 }
1618 #endif
1619
1620 static int
1621 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1622 unsigned long *state)
1623 {
1624 *state = 6;
1625
1626 return 0;
1627 }
1628
1629 static int
1630 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1631 unsigned long *state)
1632 {
1633 struct etnaviv_gpu *gpu = cdev->devdata;
1634
1635 *state = gpu->freq_scale;
1636
1637 return 0;
1638 }
1639
1640 static int
1641 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1642 unsigned long state)
1643 {
1644 struct etnaviv_gpu *gpu = cdev->devdata;
1645
1646 mutex_lock(&gpu->lock);
1647 gpu->freq_scale = state;
1648 if (!pm_runtime_suspended(gpu->dev))
1649 etnaviv_gpu_update_clock(gpu);
1650 mutex_unlock(&gpu->lock);
1651
1652 return 0;
1653 }
1654
1655 static struct thermal_cooling_device_ops cooling_ops = {
1656 .get_max_state = etnaviv_gpu_cooling_get_max_state,
1657 .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1658 .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1659 };
1660
1661 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1662 void *data)
1663 {
1664 struct drm_device *drm = data;
1665 struct etnaviv_drm_private *priv = drm->dev_private;
1666 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1667 int ret;
1668
1669 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1670 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1671 (char *)dev_name(dev), gpu, &cooling_ops);
1672 if (IS_ERR(gpu->cooling))
1673 return PTR_ERR(gpu->cooling);
1674 }
1675
1676 gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1677 if (!gpu->wq) {
1678 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1679 thermal_cooling_device_unregister(gpu->cooling);
1680 return -ENOMEM;
1681 }
1682
1683 #ifdef CONFIG_PM
1684 ret = pm_runtime_get_sync(gpu->dev);
1685 #else
1686 ret = etnaviv_gpu_clk_enable(gpu);
1687 #endif
1688 if (ret < 0) {
1689 destroy_workqueue(gpu->wq);
1690 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1691 thermal_cooling_device_unregister(gpu->cooling);
1692 return ret;
1693 }
1694
1695 gpu->drm = drm;
1696 gpu->fence_context = dma_fence_context_alloc(1);
1697 spin_lock_init(&gpu->fence_spinlock);
1698
1699 INIT_LIST_HEAD(&gpu->active_submit_list);
1700 INIT_WORK(&gpu->retire_work, retire_worker);
1701 INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1702 INIT_WORK(&gpu->recover_work, recover_worker);
1703 init_waitqueue_head(&gpu->fence_event);
1704
1705 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, TIMER_DEFERRABLE);
1706
1707 priv->gpu[priv->num_gpus++] = gpu;
1708
1709 pm_runtime_mark_last_busy(gpu->dev);
1710 pm_runtime_put_autosuspend(gpu->dev);
1711
1712 return 0;
1713 }
1714
1715 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1716 void *data)
1717 {
1718 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1719
1720 DBG("%s", dev_name(gpu->dev));
1721
1722 hangcheck_disable(gpu);
1723
1724 flush_workqueue(gpu->wq);
1725 destroy_workqueue(gpu->wq);
1726
1727 #ifdef CONFIG_PM
1728 pm_runtime_get_sync(gpu->dev);
1729 pm_runtime_put_sync_suspend(gpu->dev);
1730 #else
1731 etnaviv_gpu_hw_suspend(gpu);
1732 #endif
1733
1734 if (gpu->buffer.suballoc)
1735 etnaviv_cmdbuf_free(&gpu->buffer);
1736
1737 if (gpu->cmdbuf_suballoc) {
1738 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1739 gpu->cmdbuf_suballoc = NULL;
1740 }
1741
1742 if (gpu->mmu) {
1743 etnaviv_iommu_destroy(gpu->mmu);
1744 gpu->mmu = NULL;
1745 }
1746
1747 gpu->drm = NULL;
1748
1749 if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1750 thermal_cooling_device_unregister(gpu->cooling);
1751 gpu->cooling = NULL;
1752 }
1753
1754 static const struct component_ops gpu_ops = {
1755 .bind = etnaviv_gpu_bind,
1756 .unbind = etnaviv_gpu_unbind,
1757 };
1758
1759 static const struct of_device_id etnaviv_gpu_match[] = {
1760 {
1761 .compatible = "vivante,gc"
1762 },
1763 { /* sentinel */ }
1764 };
1765
1766 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1767 {
1768 struct device *dev = &pdev->dev;
1769 struct etnaviv_gpu *gpu;
1770 int err;
1771
1772 gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1773 if (!gpu)
1774 return -ENOMEM;
1775
1776 gpu->dev = &pdev->dev;
1777 mutex_init(&gpu->lock);
1778
1779 /* Map registers: */
1780 gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1781 if (IS_ERR(gpu->mmio))
1782 return PTR_ERR(gpu->mmio);
1783
1784 /* Get Interrupt: */
1785 gpu->irq = platform_get_irq(pdev, 0);
1786 if (gpu->irq < 0) {
1787 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1788 return gpu->irq;
1789 }
1790
1791 err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1792 dev_name(gpu->dev), gpu);
1793 if (err) {
1794 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1795 return err;
1796 }
1797
1798 /* Get Clocks: */
1799 gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1800 DBG("clk_bus: %p", gpu->clk_bus);
1801 if (IS_ERR(gpu->clk_bus))
1802 gpu->clk_bus = NULL;
1803
1804 gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1805 DBG("clk_core: %p", gpu->clk_core);
1806 if (IS_ERR(gpu->clk_core))
1807 gpu->clk_core = NULL;
1808 gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1809
1810 gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1811 DBG("clk_shader: %p", gpu->clk_shader);
1812 if (IS_ERR(gpu->clk_shader))
1813 gpu->clk_shader = NULL;
1814 gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1815
1816 /* TODO: figure out max mapped size */
1817 dev_set_drvdata(dev, gpu);
1818
1819 /*
1820 * We treat the device as initially suspended. The runtime PM
1821 * autosuspend delay is rather arbitary: no measurements have
1822 * yet been performed to determine an appropriate value.
1823 */
1824 pm_runtime_use_autosuspend(gpu->dev);
1825 pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1826 pm_runtime_enable(gpu->dev);
1827
1828 err = component_add(&pdev->dev, &gpu_ops);
1829 if (err < 0) {
1830 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1831 return err;
1832 }
1833
1834 return 0;
1835 }
1836
1837 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1838 {
1839 component_del(&pdev->dev, &gpu_ops);
1840 pm_runtime_disable(&pdev->dev);
1841 return 0;
1842 }
1843
1844 #ifdef CONFIG_PM
1845 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1846 {
1847 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1848 u32 idle, mask;
1849
1850 /* If we have outstanding fences, we're not idle */
1851 if (gpu->completed_fence != gpu->active_fence)
1852 return -EBUSY;
1853
1854 /* Check whether the hardware (except FE) is idle */
1855 mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1856 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1857 if (idle != mask)
1858 return -EBUSY;
1859
1860 return etnaviv_gpu_hw_suspend(gpu);
1861 }
1862
1863 static int etnaviv_gpu_rpm_resume(struct device *dev)
1864 {
1865 struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1866 int ret;
1867
1868 ret = etnaviv_gpu_clk_enable(gpu);
1869 if (ret)
1870 return ret;
1871
1872 /* Re-initialise the basic hardware state */
1873 if (gpu->drm && gpu->buffer.suballoc) {
1874 ret = etnaviv_gpu_hw_resume(gpu);
1875 if (ret) {
1876 etnaviv_gpu_clk_disable(gpu);
1877 return ret;
1878 }
1879 }
1880
1881 return 0;
1882 }
1883 #endif
1884
1885 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1886 SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1887 NULL)
1888 };
1889
1890 struct platform_driver etnaviv_gpu_driver = {
1891 .driver = {
1892 .name = "etnaviv-gpu",
1893 .owner = THIS_MODULE,
1894 .pm = &etnaviv_gpu_pm_ops,
1895 .of_match_table = etnaviv_gpu_match,
1896 },
1897 .probe = etnaviv_gpu_platform_probe,
1898 .remove = etnaviv_gpu_platform_remove,
1899 .id_table = gpu_ids,
1900 };
CRIS linux kernel tree