drivers/gpu/drm/i915/gvt/cfg_space.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eddie Dong <eddie.dong@intel.com>
  25  *    Jike Song <jike.song@intel.com>
  26  *
  27  * Contributors:
  28  *    Zhi Wang <zhi.a.wang@intel.com>
  29  *    Min He <min.he@intel.com>
  30  *    Bing Niu <bing.niu@intel.com>
  31  *
  32  */
  33
  34 #include "i915_drv.h"
  35 #include "gvt.h"
  36
  37 enum {
  38         INTEL_GVT_PCI_BAR_GTTMMIO = 0,
  39         INTEL_GVT_PCI_BAR_APERTURE,
  40         INTEL_GVT_PCI_BAR_PIO,
  41         INTEL_GVT_PCI_BAR_MAX,
  42 };
  43
  44 /* bitmap for writable bits (RW or RW1C bits, but cannot co-exist in one
  45  * byte) byte by byte in standard pci configuration space. (not the full
  46  * 256 bytes.)
  47  */
  48 static const u8 pci_cfg_space_rw_bmp[PCI_INTERRUPT_LINE + 4] = {
  49         [PCI_COMMAND]           = 0xff, 0x07,
  50         [PCI_STATUS]            = 0x00, 0xf9, /* the only one RW1C byte */
  51         [PCI_CACHE_LINE_SIZE]   = 0xff,
  52         [PCI_BASE_ADDRESS_0 ... PCI_CARDBUS_CIS - 1] = 0xff,
  53         [PCI_ROM_ADDRESS]       = 0x01, 0xf8, 0xff, 0xff,
  54         [PCI_INTERRUPT_LINE]    = 0xff,
  55 };
  56
  57 /**
  58  * vgpu_pci_cfg_mem_write - write virtual cfg space memory
  59  *
  60  * Use this function to write virtual cfg space memory.
  61  * For standard cfg space, only RW bits can be changed,
  62  * and we emulates the RW1C behavior of PCI_STATUS register.
  63  */
  64 static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off,
  65                                    u8 *src, unsigned int bytes)
  66 {
  67         u8 *cfg_base = vgpu_cfg_space(vgpu);
  68         u8 mask, new, old;
  69         int i = 0;
  70
  71         for (; i < bytes && (off + i < sizeof(pci_cfg_space_rw_bmp)); i++) {
  72                 mask = pci_cfg_space_rw_bmp[off + i];
  73                 old = cfg_base[off + i];
  74                 new = src[i] & mask;
  75
  76                 /**
  77                  * The PCI_STATUS high byte has RW1C bits, here
  78                  * emulates clear by writing 1 for these bits.
  79                  * Writing a 0b to RW1C bits has no effect.
  80                  */
  81                 if (off + i == PCI_STATUS + 1)
  82                         new = (~new & old) & mask;
  83
  84                 cfg_base[off + i] = (old & ~mask) | new;
  85         }
  86
  87         /* For other configuration space directly copy as it is. */
  88         if (i < bytes)
  89                 memcpy(cfg_base + off + i, src + i, bytes - i);
  90 }
  91
  92 /**
  93  * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space read
  94  *
  95  * Returns:
  96  * Zero on success, negative error code if failed.
  97  */
  98 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
  99         void *p_data, unsigned int bytes)
 100 {
 101         if (WARN_ON(bytes > 4))
 102                 return -EINVAL;
 103
 104         if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
 105                 return -EINVAL;
 106
 107         memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
 108         return 0;
 109 }
 110
 111 static int map_aperture(struct intel_vgpu *vgpu, bool map)
 112 {
 113         phys_addr_t aperture_pa = vgpu_aperture_pa_base(vgpu);
 114         unsigned long aperture_sz = vgpu_aperture_sz(vgpu);
 115         u64 first_gfn;
 116         u64 val;
 117         int ret;
 118
 119         if (map == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked)
 120                 return 0;
 121
 122         val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_2];
 123         if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
 124                 val = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
 125         else
 126                 val = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_2);
 127
 128         first_gfn = (val + vgpu_aperture_offset(vgpu)) >> PAGE_SHIFT;
 129
 130         ret = intel_gvt_hypervisor_map_gfn_to_mfn(vgpu, first_gfn,
 131                                                   aperture_pa >> PAGE_SHIFT,
 132                                                   aperture_sz >> PAGE_SHIFT,
 133                                                   map);
 134         if (ret)
 135                 return ret;
 136
 137         vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].tracked = map;
 138         return 0;
 139 }
 140
 141 static int trap_gttmmio(struct intel_vgpu *vgpu, bool trap)
 142 {
 143         u64 start, end;
 144         u64 val;
 145         int ret;
 146
 147         if (trap == vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked)
 148                 return 0;
 149
 150         val = vgpu_cfg_space(vgpu)[PCI_BASE_ADDRESS_0];
 151         if (val & PCI_BASE_ADDRESS_MEM_TYPE_64)
 152                 start = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
 153         else
 154                 start = *(u32 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0);
 155
 156         start &= ~GENMASK(3, 0);
 157         end = start + vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size - 1;
 158
 159         ret = intel_gvt_hypervisor_set_trap_area(vgpu, start, end, trap);
 160         if (ret)
 161                 return ret;
 162
 163         vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].tracked = trap;
 164         return 0;
 165 }
 166
 167 static int emulate_pci_command_write(struct intel_vgpu *vgpu,
 168         unsigned int offset, void *p_data, unsigned int bytes)
 169 {
 170         u8 old = vgpu_cfg_space(vgpu)[offset];
 171         u8 new = *(u8 *)p_data;
 172         u8 changed = old ^ new;
 173         int ret;
 174
 175         vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
 176         if (!(changed & PCI_COMMAND_MEMORY))
 177                 return 0;
 178
 179         if (old & PCI_COMMAND_MEMORY) {
 180                 ret = trap_gttmmio(vgpu, false);
 181                 if (ret)
 182                         return ret;
 183                 ret = map_aperture(vgpu, false);
 184                 if (ret)
 185                         return ret;
 186         } else {
 187                 ret = trap_gttmmio(vgpu, true);
 188                 if (ret)
 189                         return ret;
 190                 ret = map_aperture(vgpu, true);
 191                 if (ret)
 192                         return ret;
 193         }
 194
 195         return 0;
 196 }
 197
 198 static int emulate_pci_rom_bar_write(struct intel_vgpu *vgpu,
 199         unsigned int offset, void *p_data, unsigned int bytes)
 200 {
 201         u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
 202         u32 new = *(u32 *)(p_data);
 203
 204         if ((new & PCI_ROM_ADDRESS_MASK) == PCI_ROM_ADDRESS_MASK)
 205                 /* We don't have rom, return size of 0. */
 206                 *pval = 0;
 207         else
 208                 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
 209         return 0;
 210 }
 211
 212 static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset,
 213         void *p_data, unsigned int bytes)
 214 {
 215         u32 new = *(u32 *)(p_data);
 216         bool lo = IS_ALIGNED(offset, 8);
 217         u64 size;
 218         int ret = 0;
 219         bool mmio_enabled =
 220                 vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;
 221         struct intel_vgpu_pci_bar *bars = vgpu->cfg_space.bar;
 222
 223         /*
 224          * Power-up software can determine how much address
 225          * space the device requires by writing a value of
 226          * all 1's to the register and then reading the value
 227          * back. The device will return 0's in all don't-care
 228          * address bits.
 229          */
 230         if (new == 0xffffffff) {
 231                 switch (offset) {
 232                 case PCI_BASE_ADDRESS_0:
 233                 case PCI_BASE_ADDRESS_1:
 234                         size = ~(bars[INTEL_GVT_PCI_BAR_GTTMMIO].size -1);
 235                         intel_vgpu_write_pci_bar(vgpu, offset,
 236                                                 size >> (lo ? 0 : 32), lo);
 237                         /*
 238                          * Untrap the BAR, since guest hasn't configured a
 239                          * valid GPA
 240                          */
 241                         ret = trap_gttmmio(vgpu, false);
 242                         break;
 243                 case PCI_BASE_ADDRESS_2:
 244                 case PCI_BASE_ADDRESS_3:
 245                         size = ~(bars[INTEL_GVT_PCI_BAR_APERTURE].size -1);
 246                         intel_vgpu_write_pci_bar(vgpu, offset,
 247                                                 size >> (lo ? 0 : 32), lo);
 248                         ret = map_aperture(vgpu, false);
 249                         break;
 250                 default:
 251                         /* Unimplemented BARs */
 252                         intel_vgpu_write_pci_bar(vgpu, offset, 0x0, false);
 253                 }
 254         } else {
 255                 switch (offset) {
 256                 case PCI_BASE_ADDRESS_0:
 257                 case PCI_BASE_ADDRESS_1:
 258                         /*
 259                          * Untrap the old BAR first, since guest has
 260                          * re-configured the BAR
 261                          */
 262                         trap_gttmmio(vgpu, false);
 263                         intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
 264                         ret = trap_gttmmio(vgpu, mmio_enabled);
 265                         break;
 266                 case PCI_BASE_ADDRESS_2:
 267                 case PCI_BASE_ADDRESS_3:
 268                         map_aperture(vgpu, false);
 269                         intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
 270                         ret = map_aperture(vgpu, mmio_enabled);
 271                         break;
 272                 default:
 273                         intel_vgpu_write_pci_bar(vgpu, offset, new, lo);
 274                 }
 275         }
 276         return ret;
 277 }
 278
 279 /**
 280  * intel_vgpu_emulate_cfg_read - emulate vGPU configuration space write
 281  *
 282  * Returns:
 283  * Zero on success, negative error code if failed.
 284  */
 285 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
 286         void *p_data, unsigned int bytes)
 287 {
 288         int ret;
 289
 290         if (WARN_ON(bytes > 4))
 291                 return -EINVAL;
 292
 293         if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))
 294                 return -EINVAL;
 295
 296         /* First check if it's PCI_COMMAND */
 297         if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {
 298                 if (WARN_ON(bytes > 2))
 299                         return -EINVAL;
 300                 return emulate_pci_command_write(vgpu, offset, p_data, bytes);
 301         }
 302
 303         switch (rounddown(offset, 4)) {
 304         case PCI_ROM_ADDRESS:
 305                 if (WARN_ON(!IS_ALIGNED(offset, 4)))
 306                         return -EINVAL;
 307                 return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);
 308
 309         case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:
 310                 if (WARN_ON(!IS_ALIGNED(offset, 4)))
 311                         return -EINVAL;
 312                 return emulate_pci_bar_write(vgpu, offset, p_data, bytes);
 313
 314         case INTEL_GVT_PCI_SWSCI:
 315                 if (WARN_ON(!IS_ALIGNED(offset, 4)))
 316                         return -EINVAL;
 317                 ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);
 318                 if (ret)
 319                         return ret;
 320                 break;
 321
 322         case INTEL_GVT_PCI_OPREGION:
 323                 if (WARN_ON(!IS_ALIGNED(offset, 4)))
 324                         return -EINVAL;
 325                 ret = intel_vgpu_opregion_base_write_handler(vgpu,
 326                                                    *(u32 *)p_data);
 327                 if (ret)
 328                         return ret;
 329
 330                 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
 331                 break;
 332         default:
 333                 vgpu_pci_cfg_mem_write(vgpu, offset, p_data, bytes);
 334                 break;
 335         }
 336         return 0;
 337 }
 338
 339 /**
 340  * intel_vgpu_init_cfg_space - init vGPU configuration space when create vGPU
 341  *
 342  * @vgpu: a vGPU
 343  * @primary: is the vGPU presented as primary
 344  *
 345  */
 346 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
 347                                bool primary)
 348 {
 349         struct intel_gvt *gvt = vgpu->gvt;
 350         const struct intel_gvt_device_info *info = &gvt->device_info;
 351         u16 *gmch_ctl;
 352
 353         memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,
 354                info->cfg_space_size);
 355
 356         if (!primary) {
 357                 vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =
 358                         INTEL_GVT_PCI_CLASS_VGA_OTHER;
 359                 vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =
 360                         INTEL_GVT_PCI_CLASS_VGA_OTHER;
 361         }
 362
 363         /* Show guest that there isn't any stolen memory.*/
 364         gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);
 365         *gmch_ctl &= ~(BDW_GMCH_GMS_MASK << BDW_GMCH_GMS_SHIFT);
 366
 367         intel_vgpu_write_pci_bar(vgpu, PCI_BASE_ADDRESS_2,
 368                                  gvt_aperture_pa_base(gvt), true);
 369
 370         vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO
 371                                              | PCI_COMMAND_MEMORY
 372                                              | PCI_COMMAND_MASTER);
 373         /*
 374          * Clear the bar upper 32bit and let guest to assign the new value
 375          */
 376         memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);
 377         memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);
 378         memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);
 379         memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);
 380
 381         vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_GTTMMIO].size =
 382                                 pci_resource_len(gvt->dev_priv->drm.pdev, 0);
 383         vgpu->cfg_space.bar[INTEL_GVT_PCI_BAR_APERTURE].size =
 384                                 pci_resource_len(gvt->dev_priv->drm.pdev, 2);
 385
 386         memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);
 387 }
 388
 389 /**
 390  * intel_vgpu_reset_cfg_space - reset vGPU configuration space
 391  *
 392  * @vgpu: a vGPU
 393  *
 394  */
 395 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu)
 396 {
 397         u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];
 398         bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=
 399                                 INTEL_GVT_PCI_CLASS_VGA_OTHER;
 400
 401         if (cmd & PCI_COMMAND_MEMORY) {
 402                 trap_gttmmio(vgpu, false);
 403                 map_aperture(vgpu, false);
 404         }
 405
 406         /**
 407          * Currently we only do such reset when vGPU is not
 408          * owned by any VM, so we simply restore entire cfg
 409          * space to default value.
 410          */
 411         intel_vgpu_init_cfg_space(vgpu, primary);
 412 }