drivers/gpu/drm/i915/i915_sysfs.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ben Widawsky <ben@bwidawsk.net>
  25  *
  26  */
  27
  28 #include <linux/device.h>
  29 #include <linux/module.h>
  30 #include <linux/stat.h>
  31 #include <linux/sysfs.h>
  32 #include "intel_drv.h"
  33 #include "i915_drv.h"
  34
  35 static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
  36 {
  37         struct drm_minor *minor = dev_get_drvdata(kdev);
  38         return to_i915(minor->dev);
  39 }
  40
  41 #ifdef CONFIG_PM
  42 static u32 calc_residency(struct drm_i915_private *dev_priv,
  43                           i915_reg_t reg)
  44 {
  45         u64 res;
  46
  47         intel_runtime_pm_get(dev_priv);
  48         res = intel_rc6_residency_us(dev_priv, reg);
  49         intel_runtime_pm_put(dev_priv);
  50
  51         return DIV_ROUND_CLOSEST_ULL(res, 1000);
  52 }
  53
  54 static ssize_t
  55 show_rc6_mask(struct device *kdev, struct device_attribute *attr, char *buf)
  56 {
  57         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  58         unsigned int mask;
  59
  60         mask = 0;
  61         if (HAS_RC6(dev_priv))
  62                 mask |= BIT(0);
  63         if (HAS_RC6p(dev_priv))
  64                 mask |= BIT(1);
  65         if (HAS_RC6pp(dev_priv))
  66                 mask |= BIT(2);
  67
  68         return snprintf(buf, PAGE_SIZE, "%x\n", mask);
  69 }
  70
  71 static ssize_t
  72 show_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  73 {
  74         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  75         u32 rc6_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6);
  76         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
  77 }
  78
  79 static ssize_t
  80 show_rc6p_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  81 {
  82         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  83         u32 rc6p_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6p);
  84         return snprintf(buf, PAGE_SIZE, "%u\n", rc6p_residency);
  85 }
  86
  87 static ssize_t
  88 show_rc6pp_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  89 {
  90         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  91         u32 rc6pp_residency = calc_residency(dev_priv, GEN6_GT_GFX_RC6pp);
  92         return snprintf(buf, PAGE_SIZE, "%u\n", rc6pp_residency);
  93 }
  94
  95 static ssize_t
  96 show_media_rc6_ms(struct device *kdev, struct device_attribute *attr, char *buf)
  97 {
  98         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
  99         u32 rc6_residency = calc_residency(dev_priv, VLV_GT_MEDIA_RC6);
 100         return snprintf(buf, PAGE_SIZE, "%u\n", rc6_residency);
 101 }
 102
 103 static DEVICE_ATTR(rc6_enable, S_IRUGO, show_rc6_mask, NULL);
 104 static DEVICE_ATTR(rc6_residency_ms, S_IRUGO, show_rc6_ms, NULL);
 105 static DEVICE_ATTR(rc6p_residency_ms, S_IRUGO, show_rc6p_ms, NULL);
 106 static DEVICE_ATTR(rc6pp_residency_ms, S_IRUGO, show_rc6pp_ms, NULL);
 107 static DEVICE_ATTR(media_rc6_residency_ms, S_IRUGO, show_media_rc6_ms, NULL);
 108
 109 static struct attribute *rc6_attrs[] = {
 110         &dev_attr_rc6_enable.attr,
 111         &dev_attr_rc6_residency_ms.attr,
 112         NULL
 113 };
 114
 115 static const struct attribute_group rc6_attr_group = {
 116         .name = power_group_name,
 117         .attrs =  rc6_attrs
 118 };
 119
 120 static struct attribute *rc6p_attrs[] = {
 121         &dev_attr_rc6p_residency_ms.attr,
 122         &dev_attr_rc6pp_residency_ms.attr,
 123         NULL
 124 };
 125
 126 static const struct attribute_group rc6p_attr_group = {
 127         .name = power_group_name,
 128         .attrs =  rc6p_attrs
 129 };
 130
 131 static struct attribute *media_rc6_attrs[] = {
 132         &dev_attr_media_rc6_residency_ms.attr,
 133         NULL
 134 };
 135
 136 static const struct attribute_group media_rc6_attr_group = {
 137         .name = power_group_name,
 138         .attrs =  media_rc6_attrs
 139 };
 140 #endif
 141
 142 static int l3_access_valid(struct drm_i915_private *dev_priv, loff_t offset)
 143 {
 144         if (!HAS_L3_DPF(dev_priv))
 145                 return -EPERM;
 146
 147         if (offset % 4 != 0)
 148                 return -EINVAL;
 149
 150         if (offset >= GEN7_L3LOG_SIZE)
 151                 return -ENXIO;
 152
 153         return 0;
 154 }
 155
 156 static ssize_t
 157 i915_l3_read(struct file *filp, struct kobject *kobj,
 158              struct bin_attribute *attr, char *buf,
 159              loff_t offset, size_t count)
 160 {
 161         struct device *kdev = kobj_to_dev(kobj);
 162         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 163         struct drm_device *dev = &dev_priv->drm;
 164         int slice = (int)(uintptr_t)attr->private;
 165         int ret;
 166
 167         count = round_down(count, 4);
 168
 169         ret = l3_access_valid(dev_priv, offset);
 170         if (ret)
 171                 return ret;
 172
 173         count = min_t(size_t, GEN7_L3LOG_SIZE - offset, count);
 174
 175         ret = i915_mutex_lock_interruptible(dev);
 176         if (ret)
 177                 return ret;
 178
 179         if (dev_priv->l3_parity.remap_info[slice])
 180                 memcpy(buf,
 181                        dev_priv->l3_parity.remap_info[slice] + (offset/4),
 182                        count);
 183         else
 184                 memset(buf, 0, count);
 185
 186         mutex_unlock(&dev->struct_mutex);
 187
 188         return count;
 189 }
 190
 191 static ssize_t
 192 i915_l3_write(struct file *filp, struct kobject *kobj,
 193               struct bin_attribute *attr, char *buf,
 194               loff_t offset, size_t count)
 195 {
 196         struct device *kdev = kobj_to_dev(kobj);
 197         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 198         struct drm_device *dev = &dev_priv->drm;
 199         struct i915_gem_context *ctx;
 200         int slice = (int)(uintptr_t)attr->private;
 201         u32 **remap_info;
 202         int ret;
 203
 204         ret = l3_access_valid(dev_priv, offset);
 205         if (ret)
 206                 return ret;
 207
 208         ret = i915_mutex_lock_interruptible(dev);
 209         if (ret)
 210                 return ret;
 211
 212         remap_info = &dev_priv->l3_parity.remap_info[slice];
 213         if (!*remap_info) {
 214                 *remap_info = kzalloc(GEN7_L3LOG_SIZE, GFP_KERNEL);
 215                 if (!*remap_info) {
 216                         ret = -ENOMEM;
 217                         goto out;
 218                 }
 219         }
 220
 221         /* TODO: Ideally we really want a GPU reset here to make sure errors
 222          * aren't propagated. Since I cannot find a stable way to reset the GPU
 223          * at this point it is left as a TODO.
 224         */
 225         memcpy(*remap_info + (offset/4), buf, count);
 226
 227         /* NB: We defer the remapping until we switch to the context */
 228         list_for_each_entry(ctx, &dev_priv->contexts.list, link)
 229                 ctx->remap_slice |= (1<<slice);
 230
 231         ret = count;
 232
 233 out:
 234         mutex_unlock(&dev->struct_mutex);
 235
 236         return ret;
 237 }
 238
 239 static const struct bin_attribute dpf_attrs = {
 240         .attr = {.name = "l3_parity", .mode = (S_IRUSR | S_IWUSR)},
 241         .size = GEN7_L3LOG_SIZE,
 242         .read = i915_l3_read,
 243         .write = i915_l3_write,
 244         .mmap = NULL,
 245         .private = (void *)0
 246 };
 247
 248 static const struct bin_attribute dpf_attrs_1 = {
 249         .attr = {.name = "l3_parity_slice_1", .mode = (S_IRUSR | S_IWUSR)},
 250         .size = GEN7_L3LOG_SIZE,
 251         .read = i915_l3_read,
 252         .write = i915_l3_write,
 253         .mmap = NULL,
 254         .private = (void *)1
 255 };
 256
 257 static ssize_t gt_act_freq_mhz_show(struct device *kdev,
 258                                     struct device_attribute *attr, char *buf)
 259 {
 260         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 261         int ret;
 262
 263         intel_runtime_pm_get(dev_priv);
 264
 265         mutex_lock(&dev_priv->pcu_lock);
 266         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 267                 u32 freq;
 268                 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 269                 ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
 270         } else {
 271                 ret = intel_gpu_freq(dev_priv,
 272                                      intel_get_cagf(dev_priv,
 273                                                     I915_READ(GEN6_RPSTAT1)));
 274         }
 275         mutex_unlock(&dev_priv->pcu_lock);
 276
 277         intel_runtime_pm_put(dev_priv);
 278
 279         return snprintf(buf, PAGE_SIZE, "%d\n", ret);
 280 }
 281
 282 static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
 283                                     struct device_attribute *attr, char *buf)
 284 {
 285         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 286
 287         return snprintf(buf, PAGE_SIZE, "%d\n",
 288                         intel_gpu_freq(dev_priv,
 289                                        dev_priv->gt_pm.rps.cur_freq));
 290 }
 291
 292 static ssize_t gt_boost_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 293 {
 294         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 295
 296         return snprintf(buf, PAGE_SIZE, "%d\n",
 297                         intel_gpu_freq(dev_priv,
 298                                        dev_priv->gt_pm.rps.boost_freq));
 299 }
 300
 301 static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
 302                                        struct device_attribute *attr,
 303                                        const char *buf, size_t count)
 304 {
 305         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 306         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 307         u32 val;
 308         ssize_t ret;
 309
 310         ret = kstrtou32(buf, 0, &val);
 311         if (ret)
 312                 return ret;
 313
 314         /* Validate against (static) hardware limits */
 315         val = intel_freq_opcode(dev_priv, val);
 316         if (val < rps->min_freq || val > rps->max_freq)
 317                 return -EINVAL;
 318
 319         mutex_lock(&dev_priv->pcu_lock);
 320         rps->boost_freq = val;
 321         mutex_unlock(&dev_priv->pcu_lock);
 322
 323         return count;
 324 }
 325
 326 static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
 327                                      struct device_attribute *attr, char *buf)
 328 {
 329         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 330
 331         return snprintf(buf, PAGE_SIZE, "%d\n",
 332                         intel_gpu_freq(dev_priv,
 333                                        dev_priv->gt_pm.rps.efficient_freq));
 334 }
 335
 336 static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 337 {
 338         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 339
 340         return snprintf(buf, PAGE_SIZE, "%d\n",
 341                         intel_gpu_freq(dev_priv,
 342                                        dev_priv->gt_pm.rps.max_freq_softlimit));
 343 }
 344
 345 static ssize_t gt_max_freq_mhz_store(struct device *kdev,
 346                                      struct device_attribute *attr,
 347                                      const char *buf, size_t count)
 348 {
 349         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 350         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 351         u32 val;
 352         ssize_t ret;
 353
 354         ret = kstrtou32(buf, 0, &val);
 355         if (ret)
 356                 return ret;
 357
 358         intel_runtime_pm_get(dev_priv);
 359
 360         mutex_lock(&dev_priv->pcu_lock);
 361
 362         val = intel_freq_opcode(dev_priv, val);
 363
 364         if (val < rps->min_freq ||
 365             val > rps->max_freq ||
 366             val < rps->min_freq_softlimit) {
 367                 mutex_unlock(&dev_priv->pcu_lock);
 368                 intel_runtime_pm_put(dev_priv);
 369                 return -EINVAL;
 370         }
 371
 372         if (val > rps->rp0_freq)
 373                 DRM_DEBUG("User requested overclocking to %d\n",
 374                           intel_gpu_freq(dev_priv, val));
 375
 376         rps->max_freq_softlimit = val;
 377
 378         val = clamp_t(int, rps->cur_freq,
 379                       rps->min_freq_softlimit,
 380                       rps->max_freq_softlimit);
 381
 382         /* We still need *_set_rps to process the new max_delay and
 383          * update the interrupt limits and PMINTRMSK even though
 384          * frequency request may be unchanged. */
 385         ret = intel_set_rps(dev_priv, val);
 386
 387         mutex_unlock(&dev_priv->pcu_lock);
 388
 389         intel_runtime_pm_put(dev_priv);
 390
 391         return ret ?: count;
 392 }
 393
 394 static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 395 {
 396         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 397
 398         return snprintf(buf, PAGE_SIZE, "%d\n",
 399                         intel_gpu_freq(dev_priv,
 400                                        dev_priv->gt_pm.rps.min_freq_softlimit));
 401 }
 402
 403 static ssize_t gt_min_freq_mhz_store(struct device *kdev,
 404                                      struct device_attribute *attr,
 405                                      const char *buf, size_t count)
 406 {
 407         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 408         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 409         u32 val;
 410         ssize_t ret;
 411
 412         ret = kstrtou32(buf, 0, &val);
 413         if (ret)
 414                 return ret;
 415
 416         intel_runtime_pm_get(dev_priv);
 417
 418         mutex_lock(&dev_priv->pcu_lock);
 419
 420         val = intel_freq_opcode(dev_priv, val);
 421
 422         if (val < rps->min_freq ||
 423             val > rps->max_freq ||
 424             val > rps->max_freq_softlimit) {
 425                 mutex_unlock(&dev_priv->pcu_lock);
 426                 intel_runtime_pm_put(dev_priv);
 427                 return -EINVAL;
 428         }
 429
 430         rps->min_freq_softlimit = val;
 431
 432         val = clamp_t(int, rps->cur_freq,
 433                       rps->min_freq_softlimit,
 434                       rps->max_freq_softlimit);
 435
 436         /* We still need *_set_rps to process the new min_delay and
 437          * update the interrupt limits and PMINTRMSK even though
 438          * frequency request may be unchanged. */
 439         ret = intel_set_rps(dev_priv, val);
 440
 441         mutex_unlock(&dev_priv->pcu_lock);
 442
 443         intel_runtime_pm_put(dev_priv);
 444
 445         return ret ?: count;
 446 }
 447
 448 static DEVICE_ATTR_RO(gt_act_freq_mhz);
 449 static DEVICE_ATTR_RO(gt_cur_freq_mhz);
 450 static DEVICE_ATTR_RW(gt_boost_freq_mhz);
 451 static DEVICE_ATTR_RW(gt_max_freq_mhz);
 452 static DEVICE_ATTR_RW(gt_min_freq_mhz);
 453
 454 static DEVICE_ATTR_RO(vlv_rpe_freq_mhz);
 455
 456 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf);
 457 static DEVICE_ATTR(gt_RP0_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 458 static DEVICE_ATTR(gt_RP1_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 459 static DEVICE_ATTR(gt_RPn_freq_mhz, S_IRUGO, gt_rp_mhz_show, NULL);
 460
 461 /* For now we have a static number of RP states */
 462 static ssize_t gt_rp_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
 463 {
 464         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 465         struct intel_rps *rps = &dev_priv->gt_pm.rps;
 466         u32 val;
 467
 468         if (attr == &dev_attr_gt_RP0_freq_mhz)
 469                 val = intel_gpu_freq(dev_priv, rps->rp0_freq);
 470         else if (attr == &dev_attr_gt_RP1_freq_mhz)
 471                 val = intel_gpu_freq(dev_priv, rps->rp1_freq);
 472         else if (attr == &dev_attr_gt_RPn_freq_mhz)
 473                 val = intel_gpu_freq(dev_priv, rps->min_freq);
 474         else
 475                 BUG();
 476
 477         return snprintf(buf, PAGE_SIZE, "%d\n", val);
 478 }
 479
 480 static const struct attribute *gen6_attrs[] = {
 481         &dev_attr_gt_act_freq_mhz.attr,
 482         &dev_attr_gt_cur_freq_mhz.attr,
 483         &dev_attr_gt_boost_freq_mhz.attr,
 484         &dev_attr_gt_max_freq_mhz.attr,
 485         &dev_attr_gt_min_freq_mhz.attr,
 486         &dev_attr_gt_RP0_freq_mhz.attr,
 487         &dev_attr_gt_RP1_freq_mhz.attr,
 488         &dev_attr_gt_RPn_freq_mhz.attr,
 489         NULL,
 490 };
 491
 492 static const struct attribute *vlv_attrs[] = {
 493         &dev_attr_gt_act_freq_mhz.attr,
 494         &dev_attr_gt_cur_freq_mhz.attr,
 495         &dev_attr_gt_boost_freq_mhz.attr,
 496         &dev_attr_gt_max_freq_mhz.attr,
 497         &dev_attr_gt_min_freq_mhz.attr,
 498         &dev_attr_gt_RP0_freq_mhz.attr,
 499         &dev_attr_gt_RP1_freq_mhz.attr,
 500         &dev_attr_gt_RPn_freq_mhz.attr,
 501         &dev_attr_vlv_rpe_freq_mhz.attr,
 502         NULL,
 503 };
 504
 505 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 506
 507 static ssize_t error_state_read(struct file *filp, struct kobject *kobj,
 508                                 struct bin_attribute *attr, char *buf,
 509                                 loff_t off, size_t count)
 510 {
 511
 512         struct device *kdev = kobj_to_dev(kobj);
 513         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 514         struct drm_i915_error_state_buf error_str;
 515         struct i915_gpu_state *gpu;
 516         ssize_t ret;
 517
 518         ret = i915_error_state_buf_init(&error_str, dev_priv, count, off);
 519         if (ret)
 520                 return ret;
 521
 522         gpu = i915_first_error_state(dev_priv);
 523         ret = i915_error_state_to_str(&error_str, gpu);
 524         if (ret)
 525                 goto out;
 526
 527         ret = count < error_str.bytes ? count : error_str.bytes;
 528         memcpy(buf, error_str.buf, ret);
 529
 530 out:
 531         i915_gpu_state_put(gpu);
 532         i915_error_state_buf_release(&error_str);
 533
 534         return ret;
 535 }
 536
 537 static ssize_t error_state_write(struct file *file, struct kobject *kobj,
 538                                  struct bin_attribute *attr, char *buf,
 539                                  loff_t off, size_t count)
 540 {
 541         struct device *kdev = kobj_to_dev(kobj);
 542         struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
 543
 544         DRM_DEBUG_DRIVER("Resetting error state\n");
 545         i915_reset_error_state(dev_priv);
 546
 547         return count;
 548 }
 549
 550 static const struct bin_attribute error_state_attr = {
 551         .attr.name = "error",
 552         .attr.mode = S_IRUSR | S_IWUSR,
 553         .size = 0,
 554         .read = error_state_read,
 555         .write = error_state_write,
 556 };
 557
 558 static void i915_setup_error_capture(struct device *kdev)
 559 {
 560         if (sysfs_create_bin_file(&kdev->kobj, &error_state_attr))
 561                 DRM_ERROR("error_state sysfs setup failed\n");
 562 }
 563
 564 static void i915_teardown_error_capture(struct device *kdev)
 565 {
 566         sysfs_remove_bin_file(&kdev->kobj, &error_state_attr);
 567 }
 568 #else
 569 static void i915_setup_error_capture(struct device *kdev) {}
 570 static void i915_teardown_error_capture(struct device *kdev) {}
 571 #endif
 572
 573 void i915_setup_sysfs(struct drm_i915_private *dev_priv)
 574 {
 575         struct device *kdev = dev_priv->drm.primary->kdev;
 576         int ret;
 577
 578 #ifdef CONFIG_PM
 579         if (HAS_RC6(dev_priv)) {
 580                 ret = sysfs_merge_group(&kdev->kobj,
 581                                         &rc6_attr_group);
 582                 if (ret)
 583                         DRM_ERROR("RC6 residency sysfs setup failed\n");
 584         }
 585         if (HAS_RC6p(dev_priv)) {
 586                 ret = sysfs_merge_group(&kdev->kobj,
 587                                         &rc6p_attr_group);
 588                 if (ret)
 589                         DRM_ERROR("RC6p residency sysfs setup failed\n");
 590         }
 591         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 592                 ret = sysfs_merge_group(&kdev->kobj,
 593                                         &media_rc6_attr_group);
 594                 if (ret)
 595                         DRM_ERROR("Media RC6 residency sysfs setup failed\n");
 596         }
 597 #endif
 598         if (HAS_L3_DPF(dev_priv)) {
 599                 ret = device_create_bin_file(kdev, &dpf_attrs);
 600                 if (ret)
 601                         DRM_ERROR("l3 parity sysfs setup failed\n");
 602
 603                 if (NUM_L3_SLICES(dev_priv) > 1) {
 604                         ret = device_create_bin_file(kdev,
 605                                                      &dpf_attrs_1);
 606                         if (ret)
 607                                 DRM_ERROR("l3 parity slice 1 setup failed\n");
 608                 }
 609         }
 610
 611         ret = 0;
 612         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 613                 ret = sysfs_create_files(&kdev->kobj, vlv_attrs);
 614         else if (INTEL_GEN(dev_priv) >= 6)
 615                 ret = sysfs_create_files(&kdev->kobj, gen6_attrs);
 616         if (ret)
 617                 DRM_ERROR("RPS sysfs setup failed\n");
 618
 619         i915_setup_error_capture(kdev);
 620 }
 621
 622 void i915_teardown_sysfs(struct drm_i915_private *dev_priv)
 623 {
 624         struct device *kdev = dev_priv->drm.primary->kdev;
 625
 626         i915_teardown_error_capture(kdev);
 627
 628         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 629                 sysfs_remove_files(&kdev->kobj, vlv_attrs);
 630         else
 631                 sysfs_remove_files(&kdev->kobj, gen6_attrs);
 632         device_remove_bin_file(kdev,  &dpf_attrs_1);
 633         device_remove_bin_file(kdev,  &dpf_attrs);
 634 #ifdef CONFIG_PM
 635         sysfs_unmerge_group(&kdev->kobj, &rc6_attr_group);
 636         sysfs_unmerge_group(&kdev->kobj, &rc6p_attr_group);
 637 #endif
 638 }