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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[cris-mirror.git] / drivers / gpu / drm / i915 / intel_dsi.c
blobf67d321376e406660c2a2e733502725ca6452975
1 /*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26 #include <drm/drmP.h>
27 #include <drm/drm_atomic_helper.h>
28 #include <drm/drm_crtc.h>
29 #include <drm/drm_edid.h>
30 #include <drm/i915_drm.h>
31 #include <drm/drm_mipi_dsi.h>
32 #include <linux/slab.h>
33 #include <linux/gpio/consumer.h>
34 #include "i915_drv.h"
35 #include "intel_drv.h"
36 #include "intel_dsi.h"
37
38 /* return pixels in terms of txbyteclkhs */
39 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
40 u16 burst_mode_ratio)
41 {
42 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio,
43 8 * 100), lane_count);
44 }
45
46 /* return pixels equvalent to txbyteclkhs */
47 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count,
48 u16 burst_mode_ratio)
49 {
50 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
51 (bpp * burst_mode_ratio));
52 }
53
54 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)
55 {
56 /* It just so happens the VBT matches register contents. */
57 switch (fmt) {
58 case VID_MODE_FORMAT_RGB888:
59 return MIPI_DSI_FMT_RGB888;
60 case VID_MODE_FORMAT_RGB666:
61 return MIPI_DSI_FMT_RGB666;
62 case VID_MODE_FORMAT_RGB666_PACKED:
63 return MIPI_DSI_FMT_RGB666_PACKED;
64 case VID_MODE_FORMAT_RGB565:
65 return MIPI_DSI_FMT_RGB565;
66 default:
67 MISSING_CASE(fmt);
68 return MIPI_DSI_FMT_RGB666;
69 }
70 }
71
72 void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
73 {
74 struct drm_encoder *encoder = &intel_dsi->base.base;
75 struct drm_device *dev = encoder->dev;
76 struct drm_i915_private *dev_priv = to_i915(dev);
77 u32 mask;
78
79 mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
80 LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
81
82 if (intel_wait_for_register(dev_priv,
83 MIPI_GEN_FIFO_STAT(port), mask, mask,
84 100))
85 DRM_ERROR("DPI FIFOs are not empty\n");
86 }
87
88 static void write_data(struct drm_i915_private *dev_priv,
89 i915_reg_t reg,
90 const u8 *data, u32 len)
91 {
92 u32 i, j;
93
94 for (i = 0; i < len; i += 4) {
95 u32 val = 0;
96
97 for (j = 0; j < min_t(u32, len - i, 4); j++)
98 val |= *data++ << 8 * j;
99
100 I915_WRITE(reg, val);
101 }
102 }
103
104 static void read_data(struct drm_i915_private *dev_priv,
105 i915_reg_t reg,
106 u8 *data, u32 len)
107 {
108 u32 i, j;
109
110 for (i = 0; i < len; i += 4) {
111 u32 val = I915_READ(reg);
112
113 for (j = 0; j < min_t(u32, len - i, 4); j++)
114 *data++ = val >> 8 * j;
115 }
116 }
117
118 static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
119 const struct mipi_dsi_msg *msg)
120 {
121 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
122 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev;
123 struct drm_i915_private *dev_priv = to_i915(dev);
124 enum port port = intel_dsi_host->port;
125 struct mipi_dsi_packet packet;
126 ssize_t ret;
127 const u8 *header, *data;
128 i915_reg_t data_reg, ctrl_reg;
129 u32 data_mask, ctrl_mask;
130
131 ret = mipi_dsi_create_packet(&packet, msg);
132 if (ret < 0)
133 return ret;
134
135 header = packet.header;
136 data = packet.payload;
137
138 if (msg->flags & MIPI_DSI_MSG_USE_LPM) {
139 data_reg = MIPI_LP_GEN_DATA(port);
140 data_mask = LP_DATA_FIFO_FULL;
141 ctrl_reg = MIPI_LP_GEN_CTRL(port);
142 ctrl_mask = LP_CTRL_FIFO_FULL;
143 } else {
144 data_reg = MIPI_HS_GEN_DATA(port);
145 data_mask = HS_DATA_FIFO_FULL;
146 ctrl_reg = MIPI_HS_GEN_CTRL(port);
147 ctrl_mask = HS_CTRL_FIFO_FULL;
148 }
149
150 /* note: this is never true for reads */
151 if (packet.payload_length) {
152 if (intel_wait_for_register(dev_priv,
153 MIPI_GEN_FIFO_STAT(port),
154 data_mask, 0,
155 50))
156 DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
157
158 write_data(dev_priv, data_reg, packet.payload,
159 packet.payload_length);
160 }
161
162 if (msg->rx_len) {
163 I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
164 }
165
166 if (intel_wait_for_register(dev_priv,
167 MIPI_GEN_FIFO_STAT(port),
168 ctrl_mask, 0,
169 50)) {
170 DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
171 }
172
173 I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]);
174
175 /* ->rx_len is set only for reads */
176 if (msg->rx_len) {
177 data_mask = GEN_READ_DATA_AVAIL;
178 if (intel_wait_for_register(dev_priv,
179 MIPI_INTR_STAT(port),
180 data_mask, data_mask,
181 50))
182 DRM_ERROR("Timeout waiting for read data.\n");
183
184 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
185 }
186
187 /* XXX: fix for reads and writes */
188 return 4 + packet.payload_length;
189 }
190
191 static int intel_dsi_host_attach(struct mipi_dsi_host *host,
192 struct mipi_dsi_device *dsi)
193 {
194 return 0;
195 }
196
197 static int intel_dsi_host_detach(struct mipi_dsi_host *host,
198 struct mipi_dsi_device *dsi)
199 {
200 return 0;
201 }
202
203 static const struct mipi_dsi_host_ops intel_dsi_host_ops = {
204 .attach = intel_dsi_host_attach,
205 .detach = intel_dsi_host_detach,
206 .transfer = intel_dsi_host_transfer,
207 };
208
209 static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi,
210 enum port port)
211 {
212 struct intel_dsi_host *host;
213 struct mipi_dsi_device *device;
214
215 host = kzalloc(sizeof(*host), GFP_KERNEL);
216 if (!host)
217 return NULL;
218
219 host->base.ops = &intel_dsi_host_ops;
220 host->intel_dsi = intel_dsi;
221 host->port = port;
222
223 /*
224 * We should call mipi_dsi_host_register(&host->base) here, but we don't
225 * have a host->dev, and we don't have OF stuff either. So just use the
226 * dsi framework as a library and hope for the best. Create the dsi
227 * devices by ourselves here too. Need to be careful though, because we
228 * don't initialize any of the driver model devices here.
229 */
230 device = kzalloc(sizeof(*device), GFP_KERNEL);
231 if (!device) {
232 kfree(host);
233 return NULL;
234 }
235
236 device->host = &host->base;
237 host->device = device;
238
239 return host;
240 }
241
242 /*
243 * send a video mode command
244 *
245 * XXX: commands with data in MIPI_DPI_DATA?
246 */
247 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
248 enum port port)
249 {
250 struct drm_encoder *encoder = &intel_dsi->base.base;
251 struct drm_device *dev = encoder->dev;
252 struct drm_i915_private *dev_priv = to_i915(dev);
253 u32 mask;
254
255 /* XXX: pipe, hs */
256 if (hs)
257 cmd &= ~DPI_LP_MODE;
258 else
259 cmd |= DPI_LP_MODE;
260
261 /* clear bit */
262 I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT);
263
264 /* XXX: old code skips write if control unchanged */
265 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
266 DRM_DEBUG_KMS("Same special packet %02x twice in a row.\n", cmd);
267
268 I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
269
270 mask = SPL_PKT_SENT_INTERRUPT;
271 if (intel_wait_for_register(dev_priv,
272 MIPI_INTR_STAT(port), mask, mask,
273 100))
274 DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
275
276 return 0;
277 }
278
279 static void band_gap_reset(struct drm_i915_private *dev_priv)
280 {
281 mutex_lock(&dev_priv->sb_lock);
282
283 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
284 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
285 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
286 udelay(150);
287 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
288 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
289
290 mutex_unlock(&dev_priv->sb_lock);
291 }
292
293 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
294 {
295 return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE;
296 }
297
298 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
299 {
300 return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE;
301 }
302
303 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
304 struct intel_crtc_state *pipe_config,
305 struct drm_connector_state *conn_state)
306 {
307 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
308 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
309 base);
310 struct intel_connector *intel_connector = intel_dsi->attached_connector;
311 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
312 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
313 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
314 int ret;
315
316 DRM_DEBUG_KMS("\n");
317
318 if (fixed_mode) {
319 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
320
321 if (HAS_GMCH_DISPLAY(dev_priv))
322 intel_gmch_panel_fitting(crtc, pipe_config,
323 conn_state->scaling_mode);
324 else
325 intel_pch_panel_fitting(crtc, pipe_config,
326 conn_state->scaling_mode);
327 }
328
329 /* DSI uses short packets for sync events, so clear mode flags for DSI */
330 adjusted_mode->flags = 0;
331
332 if (IS_GEN9_LP(dev_priv)) {
333 /* Enable Frame time stamp based scanline reporting */
334 adjusted_mode->private_flags |=
335 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
336
337 /* Dual link goes to DSI transcoder A. */
338 if (intel_dsi->ports == BIT(PORT_C))
339 pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
340 else
341 pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
342 }
343
344 ret = intel_compute_dsi_pll(encoder, pipe_config);
345 if (ret)
346 return false;
347
348 pipe_config->clock_set = true;
349
350 return true;
351 }
352
353 static bool glk_dsi_enable_io(struct intel_encoder *encoder)
354 {
355 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
356 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
357 enum port port;
358 u32 tmp;
359 bool cold_boot = false;
360
361 /* Set the MIPI mode
362 * If MIPI_Mode is off, then writing to LP_Wake bit is not reflecting.
363 * Power ON MIPI IO first and then write into IO reset and LP wake bits
364 */
365 for_each_dsi_port(port, intel_dsi->ports) {
366 tmp = I915_READ(MIPI_CTRL(port));
367 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE);
368 }
369
370 /* Put the IO into reset */
371 tmp = I915_READ(MIPI_CTRL(PORT_A));
372 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
373 I915_WRITE(MIPI_CTRL(PORT_A), tmp);
374
375 /* Program LP Wake */
376 for_each_dsi_port(port, intel_dsi->ports) {
377 tmp = I915_READ(MIPI_CTRL(port));
378 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
379 tmp &= ~GLK_LP_WAKE;
380 else
381 tmp |= GLK_LP_WAKE;
382 I915_WRITE(MIPI_CTRL(port), tmp);
383 }
384
385 /* Wait for Pwr ACK */
386 for_each_dsi_port(port, intel_dsi->ports) {
387 if (intel_wait_for_register(dev_priv,
388 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED,
389 GLK_MIPIIO_PORT_POWERED, 20))
390 DRM_ERROR("MIPIO port is powergated\n");
391 }
392
393 /* Check for cold boot scenario */
394 for_each_dsi_port(port, intel_dsi->ports) {
395 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &
396 DEVICE_READY);
397 }
398
399 return cold_boot;
400 }
401
402 static void glk_dsi_device_ready(struct intel_encoder *encoder)
403 {
404 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
405 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
406 enum port port;
407 u32 val;
408
409 /* Wait for MIPI PHY status bit to set */
410 for_each_dsi_port(port, intel_dsi->ports) {
411 if (intel_wait_for_register(dev_priv,
412 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY,
413 GLK_PHY_STATUS_PORT_READY, 20))
414 DRM_ERROR("PHY is not ON\n");
415 }
416
417 /* Get IO out of reset */
418 val = I915_READ(MIPI_CTRL(PORT_A));
419 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED);
420
421 /* Get IO out of Low power state*/
422 for_each_dsi_port(port, intel_dsi->ports) {
423 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
424 val = I915_READ(MIPI_DEVICE_READY(port));
425 val &= ~ULPS_STATE_MASK;
426 val |= DEVICE_READY;
427 I915_WRITE(MIPI_DEVICE_READY(port), val);
428 usleep_range(10, 15);
429 } else {
430 /* Enter ULPS */
431 val = I915_READ(MIPI_DEVICE_READY(port));
432 val &= ~ULPS_STATE_MASK;
433 val |= (ULPS_STATE_ENTER | DEVICE_READY);
434 I915_WRITE(MIPI_DEVICE_READY(port), val);
435
436 /* Wait for ULPS active */
437 if (intel_wait_for_register(dev_priv,
438 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20))
439 DRM_ERROR("ULPS not active\n");
440
441 /* Exit ULPS */
442 val = I915_READ(MIPI_DEVICE_READY(port));
443 val &= ~ULPS_STATE_MASK;
444 val |= (ULPS_STATE_EXIT | DEVICE_READY);
445 I915_WRITE(MIPI_DEVICE_READY(port), val);
446
447 /* Enter Normal Mode */
448 val = I915_READ(MIPI_DEVICE_READY(port));
449 val &= ~ULPS_STATE_MASK;
450 val |= (ULPS_STATE_NORMAL_OPERATION | DEVICE_READY);
451 I915_WRITE(MIPI_DEVICE_READY(port), val);
452
453 val = I915_READ(MIPI_CTRL(port));
454 val &= ~GLK_LP_WAKE;
455 I915_WRITE(MIPI_CTRL(port), val);
456 }
457 }
458
459 /* Wait for Stop state */
460 for_each_dsi_port(port, intel_dsi->ports) {
461 if (intel_wait_for_register(dev_priv,
462 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE,
463 GLK_DATA_LANE_STOP_STATE, 20))
464 DRM_ERROR("Date lane not in STOP state\n");
465 }
466
467 /* Wait for AFE LATCH */
468 for_each_dsi_port(port, intel_dsi->ports) {
469 if (intel_wait_for_register(dev_priv,
470 BXT_MIPI_PORT_CTRL(port), AFE_LATCHOUT,
471 AFE_LATCHOUT, 20))
472 DRM_ERROR("D-PHY not entering LP-11 state\n");
473 }
474 }
475
476 static void bxt_dsi_device_ready(struct intel_encoder *encoder)
477 {
478 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
479 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
480 enum port port;
481 u32 val;
482
483 DRM_DEBUG_KMS("\n");
484
485 /* Enable MIPI PHY transparent latch */
486 for_each_dsi_port(port, intel_dsi->ports) {
487 val = I915_READ(BXT_MIPI_PORT_CTRL(port));
488 I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD);
489 usleep_range(2000, 2500);
490 }
491
492 /* Clear ULPS and set device ready */
493 for_each_dsi_port(port, intel_dsi->ports) {
494 val = I915_READ(MIPI_DEVICE_READY(port));
495 val &= ~ULPS_STATE_MASK;
496 I915_WRITE(MIPI_DEVICE_READY(port), val);
497 usleep_range(2000, 2500);
498 val |= DEVICE_READY;
499 I915_WRITE(MIPI_DEVICE_READY(port), val);
500 }
501 }
502
503 static void vlv_dsi_device_ready(struct intel_encoder *encoder)
504 {
505 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
506 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
507 enum port port;
508 u32 val;
509
510 DRM_DEBUG_KMS("\n");
511
512 mutex_lock(&dev_priv->sb_lock);
513 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
514 * needed everytime after power gate */
515 vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
516 mutex_unlock(&dev_priv->sb_lock);
517
518 /* bandgap reset is needed after everytime we do power gate */
519 band_gap_reset(dev_priv);
520
521 for_each_dsi_port(port, intel_dsi->ports) {
522
523 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER);
524 usleep_range(2500, 3000);
525
526 /* Enable MIPI PHY transparent latch
527 * Common bit for both MIPI Port A & MIPI Port C
528 * No similar bit in MIPI Port C reg
529 */
530 val = I915_READ(MIPI_PORT_CTRL(PORT_A));
531 I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD);
532 usleep_range(1000, 1500);
533
534 I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT);
535 usleep_range(2500, 3000);
536
537 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY);
538 usleep_range(2500, 3000);
539 }
540 }
541
542 static void intel_dsi_device_ready(struct intel_encoder *encoder)
543 {
544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
545
546 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
547 vlv_dsi_device_ready(encoder);
548 else if (IS_BROXTON(dev_priv))
549 bxt_dsi_device_ready(encoder);
550 else if (IS_GEMINILAKE(dev_priv))
551 glk_dsi_device_ready(encoder);
552 }
553
554 static void glk_dsi_enter_low_power_mode(struct intel_encoder *encoder)
555 {
556 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
557 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
558 enum port port;
559 u32 val;
560
561 /* Enter ULPS */
562 for_each_dsi_port(port, intel_dsi->ports) {
563 val = I915_READ(MIPI_DEVICE_READY(port));
564 val &= ~ULPS_STATE_MASK;
565 val |= (ULPS_STATE_ENTER | DEVICE_READY);
566 I915_WRITE(MIPI_DEVICE_READY(port), val);
567 }
568
569 /* Wait for MIPI PHY status bit to unset */
570 for_each_dsi_port(port, intel_dsi->ports) {
571 if (intel_wait_for_register(dev_priv,
572 MIPI_CTRL(port),
573 GLK_PHY_STATUS_PORT_READY, 0, 20))
574 DRM_ERROR("PHY is not turning OFF\n");
575 }
576
577 /* Wait for Pwr ACK bit to unset */
578 for_each_dsi_port(port, intel_dsi->ports) {
579 if (intel_wait_for_register(dev_priv,
580 MIPI_CTRL(port),
581 GLK_MIPIIO_PORT_POWERED, 0, 20))
582 DRM_ERROR("MIPI IO Port is not powergated\n");
583 }
584 }
585
586 static void glk_dsi_disable_mipi_io(struct intel_encoder *encoder)
587 {
588 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
589 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
590 enum port port;
591 u32 tmp;
592
593 /* Put the IO into reset */
594 tmp = I915_READ(MIPI_CTRL(PORT_A));
595 tmp &= ~GLK_MIPIIO_RESET_RELEASED;
596 I915_WRITE(MIPI_CTRL(PORT_A), tmp);
597
598 /* Wait for MIPI PHY status bit to unset */
599 for_each_dsi_port(port, intel_dsi->ports) {
600 if (intel_wait_for_register(dev_priv,
601 MIPI_CTRL(port),
602 GLK_PHY_STATUS_PORT_READY, 0, 20))
603 DRM_ERROR("PHY is not turning OFF\n");
604 }
605
606 /* Clear MIPI mode */
607 for_each_dsi_port(port, intel_dsi->ports) {
608 tmp = I915_READ(MIPI_CTRL(port));
609 tmp &= ~GLK_MIPIIO_ENABLE;
610 I915_WRITE(MIPI_CTRL(port), tmp);
611 }
612 }
613
614 static void glk_dsi_clear_device_ready(struct intel_encoder *encoder)
615 {
616 glk_dsi_enter_low_power_mode(encoder);
617 glk_dsi_disable_mipi_io(encoder);
618 }
619
620 static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder)
621 {
622 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
623 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
624 enum port port;
625
626 DRM_DEBUG_KMS("\n");
627 for_each_dsi_port(port, intel_dsi->ports) {
628 /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
629 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
630 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
631 u32 val;
632
633 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
634 ULPS_STATE_ENTER);
635 usleep_range(2000, 2500);
636
637 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
638 ULPS_STATE_EXIT);
639 usleep_range(2000, 2500);
640
641 I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY |
642 ULPS_STATE_ENTER);
643 usleep_range(2000, 2500);
644
645 /*
646 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI
647 * Port A only. MIPI Port C has no similar bit for checking.
648 */
649 if ((IS_GEN9_LP(dev_priv) || port == PORT_A) &&
650 intel_wait_for_register(dev_priv,
651 port_ctrl, AFE_LATCHOUT, 0,
652 30))
653 DRM_ERROR("DSI LP not going Low\n");
654
655 /* Disable MIPI PHY transparent latch */
656 val = I915_READ(port_ctrl);
657 I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
658 usleep_range(1000, 1500);
659
660 I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
661 usleep_range(2000, 2500);
662 }
663 }
664
665 static void intel_dsi_port_enable(struct intel_encoder *encoder,
666 const struct intel_crtc_state *crtc_state)
667 {
668 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
669 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
670 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
671 enum port port;
672
673 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
674 u32 temp;
675 if (IS_GEN9_LP(dev_priv)) {
676 for_each_dsi_port(port, intel_dsi->ports) {
677 temp = I915_READ(MIPI_CTRL(port));
678 temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
679 intel_dsi->pixel_overlap <<
680 BXT_PIXEL_OVERLAP_CNT_SHIFT;
681 I915_WRITE(MIPI_CTRL(port), temp);
682 }
683 } else {
684 temp = I915_READ(VLV_CHICKEN_3);
685 temp &= ~PIXEL_OVERLAP_CNT_MASK |
686 intel_dsi->pixel_overlap <<
687 PIXEL_OVERLAP_CNT_SHIFT;
688 I915_WRITE(VLV_CHICKEN_3, temp);
689 }
690 }
691
692 for_each_dsi_port(port, intel_dsi->ports) {
693 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
694 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
695 u32 temp;
696
697 temp = I915_READ(port_ctrl);
698
699 temp &= ~LANE_CONFIGURATION_MASK;
700 temp &= ~DUAL_LINK_MODE_MASK;
701
702 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
703 temp |= (intel_dsi->dual_link - 1)
704 << DUAL_LINK_MODE_SHIFT;
705 if (IS_BROXTON(dev_priv))
706 temp |= LANE_CONFIGURATION_DUAL_LINK_A;
707 else
708 temp |= crtc->pipe ?
709 LANE_CONFIGURATION_DUAL_LINK_B :
710 LANE_CONFIGURATION_DUAL_LINK_A;
711 }
712 /* assert ip_tg_enable signal */
713 I915_WRITE(port_ctrl, temp | DPI_ENABLE);
714 POSTING_READ(port_ctrl);
715 }
716 }
717
718 static void intel_dsi_port_disable(struct intel_encoder *encoder)
719 {
720 struct drm_device *dev = encoder->base.dev;
721 struct drm_i915_private *dev_priv = to_i915(dev);
722 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
723 enum port port;
724
725 for_each_dsi_port(port, intel_dsi->ports) {
726 i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ?
727 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
728 u32 temp;
729
730 /* de-assert ip_tg_enable signal */
731 temp = I915_READ(port_ctrl);
732 I915_WRITE(port_ctrl, temp & ~DPI_ENABLE);
733 POSTING_READ(port_ctrl);
734 }
735 }
736
737 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
738 const struct intel_crtc_state *pipe_config);
739 static void intel_dsi_unprepare(struct intel_encoder *encoder);
740
741 static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
742 {
743 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
744
745 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
746 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
747 return;
748
749 msleep(msec);
750 }
751
752 /*
753 * Panel enable/disable sequences from the VBT spec.
754 *
755 * Note the spec has AssertReset / DeassertReset swapped from their
756 * usual naming. We use the normal names to avoid confusion (so below
757 * they are swapped compared to the spec).
758 *
759 * Steps starting with MIPI refer to VBT sequences, note that for v2
760 * VBTs several steps which have a VBT in v2 are expected to be handled
761 * directly by the driver, by directly driving gpios for example.
762 *
763 * v2 video mode seq v3 video mode seq command mode seq
764 * - power on - MIPIPanelPowerOn - power on
765 * - wait t1+t2 - wait t1+t2
766 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
767 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
768 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
769 * - MIPITearOn
770 * - MIPIDisplayOn
771 * - turn on DPI - turn on DPI - set pipe to dsr mode
772 * - MIPIDisplayOn - MIPIDisplayOn
773 * - wait t5 - wait t5
774 * - backlight on - MIPIBacklightOn - backlight on
775 * ... ... ... issue mem cmds ...
776 * - backlight off - MIPIBacklightOff - backlight off
777 * - wait t6 - wait t6
778 * - MIPIDisplayOff
779 * - turn off DPI - turn off DPI - disable pipe dsr mode
780 * - MIPITearOff
781 * - MIPIDisplayOff - MIPIDisplayOff
782 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
783 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
784 * - wait t3 - wait t3
785 * - power off - MIPIPanelPowerOff - power off
786 * - wait t4 - wait t4
787 */
788
789 static void intel_dsi_pre_enable(struct intel_encoder *encoder,
790 const struct intel_crtc_state *pipe_config,
791 const struct drm_connector_state *conn_state)
792 {
793 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
794 struct drm_crtc *crtc = pipe_config->base.crtc;
795 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
797 int pipe = intel_crtc->pipe;
798 enum port port;
799 u32 val;
800 bool glk_cold_boot = false;
801
802 DRM_DEBUG_KMS("\n");
803
804 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
805
806 /*
807 * The BIOS may leave the PLL in a wonky state where it doesn't
808 * lock. It needs to be fully powered down to fix it.
809 */
810 intel_disable_dsi_pll(encoder);
811 intel_enable_dsi_pll(encoder, pipe_config);
812
813 if (IS_BROXTON(dev_priv)) {
814 /* Add MIPI IO reset programming for modeset */
815 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
816 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
817 val | MIPIO_RST_CTRL);
818
819 /* Power up DSI regulator */
820 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
821 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0);
822 }
823
824 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
825 u32 val;
826
827 /* Disable DPOunit clock gating, can stall pipe */
828 val = I915_READ(DSPCLK_GATE_D);
829 val |= DPOUNIT_CLOCK_GATE_DISABLE;
830 I915_WRITE(DSPCLK_GATE_D, val);
831 }
832
833 if (!IS_GEMINILAKE(dev_priv))
834 intel_dsi_prepare(encoder, pipe_config);
835
836 /* Power on, try both CRC pmic gpio and VBT */
837 if (intel_dsi->gpio_panel)
838 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
839 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
840 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
841
842 /* Deassert reset */
843 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
844
845 if (IS_GEMINILAKE(dev_priv)) {
846 glk_cold_boot = glk_dsi_enable_io(encoder);
847
848 /* Prepare port in cold boot(s3/s4) scenario */
849 if (glk_cold_boot)
850 intel_dsi_prepare(encoder, pipe_config);
851 }
852
853 /* Put device in ready state (LP-11) */
854 intel_dsi_device_ready(encoder);
855
856 /* Prepare port in normal boot scenario */
857 if (IS_GEMINILAKE(dev_priv) && !glk_cold_boot)
858 intel_dsi_prepare(encoder, pipe_config);
859
860 /* Send initialization commands in LP mode */
861 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
862
863 /* Enable port in pre-enable phase itself because as per hw team
864 * recommendation, port should be enabled befor plane & pipe */
865 if (is_cmd_mode(intel_dsi)) {
866 for_each_dsi_port(port, intel_dsi->ports)
867 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4);
868 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_ON);
869 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
870 } else {
871 msleep(20); /* XXX */
872 for_each_dsi_port(port, intel_dsi->ports)
873 dpi_send_cmd(intel_dsi, TURN_ON, false, port);
874 intel_dsi_msleep(intel_dsi, 100);
875
876 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
877
878 intel_dsi_port_enable(encoder, pipe_config);
879 }
880
881 intel_panel_enable_backlight(pipe_config, conn_state);
882 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
883 }
884
885 /*
886 * DSI port enable has to be done before pipe and plane enable, so we do it in
887 * the pre_enable hook.
888 */
889 static void intel_dsi_enable_nop(struct intel_encoder *encoder,
890 const struct intel_crtc_state *pipe_config,
891 const struct drm_connector_state *conn_state)
892 {
893 DRM_DEBUG_KMS("\n");
894 }
895
896 /*
897 * DSI port disable has to be done after pipe and plane disable, so we do it in
898 * the post_disable hook.
899 */
900 static void intel_dsi_disable(struct intel_encoder *encoder,
901 const struct intel_crtc_state *old_crtc_state,
902 const struct drm_connector_state *old_conn_state)
903 {
904 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
905 enum port port;
906
907 DRM_DEBUG_KMS("\n");
908
909 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
910 intel_panel_disable_backlight(old_conn_state);
911
912 /*
913 * According to the spec we should send SHUTDOWN before
914 * MIPI_SEQ_DISPLAY_OFF only for v3+ VBTs, but field testing
915 * has shown that the v3 sequence works for v2 VBTs too
916 */
917 if (is_vid_mode(intel_dsi)) {
918 /* Send Shutdown command to the panel in LP mode */
919 for_each_dsi_port(port, intel_dsi->ports)
920 dpi_send_cmd(intel_dsi, SHUTDOWN, false, port);
921 msleep(10);
922 }
923 }
924
925 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
926 {
927 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
928
929 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
930 IS_BROXTON(dev_priv))
931 vlv_dsi_clear_device_ready(encoder);
932 else if (IS_GEMINILAKE(dev_priv))
933 glk_dsi_clear_device_ready(encoder);
934 }
935
936 static void intel_dsi_post_disable(struct intel_encoder *encoder,
937 const struct intel_crtc_state *pipe_config,
938 const struct drm_connector_state *conn_state)
939 {
940 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
941 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
942 enum port port;
943 u32 val;
944
945 DRM_DEBUG_KMS("\n");
946
947 if (is_vid_mode(intel_dsi)) {
948 for_each_dsi_port(port, intel_dsi->ports)
949 wait_for_dsi_fifo_empty(intel_dsi, port);
950
951 intel_dsi_port_disable(encoder);
952 usleep_range(2000, 5000);
953 }
954
955 intel_dsi_unprepare(encoder);
956
957 /*
958 * if disable packets are sent before sending shutdown packet then in
959 * some next enable sequence send turn on packet error is observed
960 */
961 if (is_cmd_mode(intel_dsi))
962 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_TEAR_OFF);
963 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
964
965 /* Transition to LP-00 */
966 intel_dsi_clear_device_ready(encoder);
967
968 if (IS_BROXTON(dev_priv)) {
969 /* Power down DSI regulator to save power */
970 I915_WRITE(BXT_P_DSI_REGULATOR_CFG, STAP_SELECT);
971 I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, HS_IO_CTRL_SELECT);
972
973 /* Add MIPI IO reset programming for modeset */
974 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
975 I915_WRITE(BXT_P_CR_GT_DISP_PWRON,
976 val & ~MIPIO_RST_CTRL);
977 }
978
979 intel_disable_dsi_pll(encoder);
980
981 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
982 u32 val;
983
984 val = I915_READ(DSPCLK_GATE_D);
985 val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
986 I915_WRITE(DSPCLK_GATE_D, val);
987 }
988
989 /* Assert reset */
990 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
991
992 /* Power off, try both CRC pmic gpio and VBT */
993 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
994 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
995 if (intel_dsi->gpio_panel)
996 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
997
998 /*
999 * FIXME As we do with eDP, just make a note of the time here
1000 * and perform the wait before the next panel power on.
1001 */
1002 intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
1003 }
1004
1005 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
1006 enum pipe *pipe)
1007 {
1008 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1009 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1010 enum port port;
1011 bool active = false;
1012
1013 DRM_DEBUG_KMS("\n");
1014
1015 if (!intel_display_power_get_if_enabled(dev_priv,
1016 encoder->power_domain))
1017 return false;
1018
1019 /*
1020 * On Broxton the PLL needs to be enabled with a valid divider
1021 * configuration, otherwise accessing DSI registers will hang the
1022 * machine. See BSpec North Display Engine registers/MIPI[BXT].
1023 */
1024 if (IS_GEN9_LP(dev_priv) && !intel_dsi_pll_is_enabled(dev_priv))
1025 goto out_put_power;
1026
1027 /* XXX: this only works for one DSI output */
1028 for_each_dsi_port(port, intel_dsi->ports) {
1029 i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ?
1030 BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
1031 bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;
1032
1033 /*
1034 * Due to some hardware limitations on VLV/CHV, the DPI enable
1035 * bit in port C control register does not get set. As a
1036 * workaround, check pipe B conf instead.
1037 */
1038 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1039 port == PORT_C)
1040 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1041
1042 /* Try command mode if video mode not enabled */
1043 if (!enabled) {
1044 u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));
1045 enabled = tmp & CMD_MODE_DATA_WIDTH_MASK;
1046 }
1047
1048 if (!enabled)
1049 continue;
1050
1051 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
1052 continue;
1053
1054 if (IS_GEN9_LP(dev_priv)) {
1055 u32 tmp = I915_READ(MIPI_CTRL(port));
1056 tmp &= BXT_PIPE_SELECT_MASK;
1057 tmp >>= BXT_PIPE_SELECT_SHIFT;
1058
1059 if (WARN_ON(tmp > PIPE_C))
1060 continue;
1061
1062 *pipe = tmp;
1063 } else {
1064 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1065 }
1066
1067 active = true;
1068 break;
1069 }
1070
1071 out_put_power:
1072 intel_display_power_put(dev_priv, encoder->power_domain);
1073
1074 return active;
1075 }
1076
1077 static void bxt_dsi_get_pipe_config(struct intel_encoder *encoder,
1078 struct intel_crtc_state *pipe_config)
1079 {
1080 struct drm_device *dev = encoder->base.dev;
1081 struct drm_i915_private *dev_priv = to_i915(dev);
1082 struct drm_display_mode *adjusted_mode =
1083 &pipe_config->base.adjusted_mode;
1084 struct drm_display_mode *adjusted_mode_sw;
1085 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1086 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1087 unsigned int lane_count = intel_dsi->lane_count;
1088 unsigned int bpp, fmt;
1089 enum port port;
1090 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1091 u16 hfp_sw, hsync_sw, hbp_sw;
1092 u16 crtc_htotal_sw, crtc_hsync_start_sw, crtc_hsync_end_sw,
1093 crtc_hblank_start_sw, crtc_hblank_end_sw;
1094
1095 /* FIXME: hw readout should not depend on SW state */
1096 adjusted_mode_sw = &crtc->config->base.adjusted_mode;
1097
1098 /*
1099 * Atleast one port is active as encoder->get_config called only if
1100 * encoder->get_hw_state() returns true.
1101 */
1102 for_each_dsi_port(port, intel_dsi->ports) {
1103 if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)
1104 break;
1105 }
1106
1107 fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;
1108 pipe_config->pipe_bpp =
1109 mipi_dsi_pixel_format_to_bpp(
1110 pixel_format_from_register_bits(fmt));
1111 bpp = pipe_config->pipe_bpp;
1112
1113 /* Enable Frame time stamo based scanline reporting */
1114 adjusted_mode->private_flags |=
1115 I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP;
1116
1117 /* In terms of pixels */
1118 adjusted_mode->crtc_hdisplay =
1119 I915_READ(BXT_MIPI_TRANS_HACTIVE(port));
1120 adjusted_mode->crtc_vdisplay =
1121 I915_READ(BXT_MIPI_TRANS_VACTIVE(port));
1122 adjusted_mode->crtc_vtotal =
1123 I915_READ(BXT_MIPI_TRANS_VTOTAL(port));
1124
1125 hactive = adjusted_mode->crtc_hdisplay;
1126 hfp = I915_READ(MIPI_HFP_COUNT(port));
1127
1128 /*
1129 * Meaningful for video mode non-burst sync pulse mode only,
1130 * can be zero for non-burst sync events and burst modes
1131 */
1132 hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));
1133 hbp = I915_READ(MIPI_HBP_COUNT(port));
1134
1135 /* harizontal values are in terms of high speed byte clock */
1136 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1137 intel_dsi->burst_mode_ratio);
1138 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1139 intel_dsi->burst_mode_ratio);
1140 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1141 intel_dsi->burst_mode_ratio);
1142
1143 if (intel_dsi->dual_link) {
1144 hfp *= 2;
1145 hsync *= 2;
1146 hbp *= 2;
1147 }
1148
1149 /* vertical values are in terms of lines */
1150 vfp = I915_READ(MIPI_VFP_COUNT(port));
1151 vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));
1152 vbp = I915_READ(MIPI_VBP_COUNT(port));
1153
1154 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp;
1155 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay;
1156 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start;
1157 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1158 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1159
1160 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay;
1161 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start;
1162 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1163 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1164
1165 /*
1166 * In BXT DSI there is no regs programmed with few horizontal timings
1167 * in Pixels but txbyteclkhs.. So retrieval process adds some
1168 * ROUND_UP ERRORS in the process of PIXELS<==>txbyteclkhs.
1169 * Actually here for the given adjusted_mode, we are calculating the
1170 * value programmed to the port and then back to the horizontal timing
1171 * param in pixels. This is the expected value, including roundup errors
1172 * And if that is same as retrieved value from port, then
1173 * (HW state) adjusted_mode's horizontal timings are corrected to
1174 * match with SW state to nullify the errors.
1175 */
1176 /* Calculating the value programmed to the Port register */
1177 hfp_sw = adjusted_mode_sw->crtc_hsync_start -
1178 adjusted_mode_sw->crtc_hdisplay;
1179 hsync_sw = adjusted_mode_sw->crtc_hsync_end -
1180 adjusted_mode_sw->crtc_hsync_start;
1181 hbp_sw = adjusted_mode_sw->crtc_htotal -
1182 adjusted_mode_sw->crtc_hsync_end;
1183
1184 if (intel_dsi->dual_link) {
1185 hfp_sw /= 2;
1186 hsync_sw /= 2;
1187 hbp_sw /= 2;
1188 }
1189
1190 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1191 intel_dsi->burst_mode_ratio);
1192 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count,
1193 intel_dsi->burst_mode_ratio);
1194 hbp_sw = txbyteclkhs(hbp_sw, bpp, lane_count,
1195 intel_dsi->burst_mode_ratio);
1196
1197 /* Reverse calculating the adjusted mode parameters from port reg vals*/
1198 hfp_sw = pixels_from_txbyteclkhs(hfp_sw, bpp, lane_count,
1199 intel_dsi->burst_mode_ratio);
1200 hsync_sw = pixels_from_txbyteclkhs(hsync_sw, bpp, lane_count,
1201 intel_dsi->burst_mode_ratio);
1202 hbp_sw = pixels_from_txbyteclkhs(hbp_sw, bpp, lane_count,
1203 intel_dsi->burst_mode_ratio);
1204
1205 if (intel_dsi->dual_link) {
1206 hfp_sw *= 2;
1207 hsync_sw *= 2;
1208 hbp_sw *= 2;
1209 }
1210
1211 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw +
1212 hsync_sw + hbp_sw;
1213 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay;
1214 crtc_hsync_end_sw = hsync_sw + crtc_hsync_start_sw;
1215 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay;
1216 crtc_hblank_end_sw = crtc_htotal_sw;
1217
1218 if (adjusted_mode->crtc_htotal == crtc_htotal_sw)
1219 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal;
1220
1221 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw)
1222 adjusted_mode->crtc_hsync_start =
1223 adjusted_mode_sw->crtc_hsync_start;
1224
1225 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw)
1226 adjusted_mode->crtc_hsync_end =
1227 adjusted_mode_sw->crtc_hsync_end;
1228
1229 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw)
1230 adjusted_mode->crtc_hblank_start =
1231 adjusted_mode_sw->crtc_hblank_start;
1232
1233 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw)
1234 adjusted_mode->crtc_hblank_end =
1235 adjusted_mode_sw->crtc_hblank_end;
1236 }
1237
1238 static void intel_dsi_get_config(struct intel_encoder *encoder,
1239 struct intel_crtc_state *pipe_config)
1240 {
1241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1242 u32 pclk;
1243 DRM_DEBUG_KMS("\n");
1244
1245 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1246
1247 if (IS_GEN9_LP(dev_priv))
1248 bxt_dsi_get_pipe_config(encoder, pipe_config);
1249
1250 pclk = intel_dsi_get_pclk(encoder, pipe_config->pipe_bpp,
1251 pipe_config);
1252 if (!pclk)
1253 return;
1254
1255 pipe_config->base.adjusted_mode.crtc_clock = pclk;
1256 pipe_config->port_clock = pclk;
1257 }
1258
1259 static enum drm_mode_status
1260 intel_dsi_mode_valid(struct drm_connector *connector,
1261 struct drm_display_mode *mode)
1262 {
1263 struct intel_connector *intel_connector = to_intel_connector(connector);
1264 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
1265 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1266
1267 DRM_DEBUG_KMS("\n");
1268
1269 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
1270 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
1271 return MODE_NO_DBLESCAN;
1272 }
1273
1274 if (fixed_mode) {
1275 if (mode->hdisplay > fixed_mode->hdisplay)
1276 return MODE_PANEL;
1277 if (mode->vdisplay > fixed_mode->vdisplay)
1278 return MODE_PANEL;
1279 if (fixed_mode->clock > max_dotclk)
1280 return MODE_CLOCK_HIGH;
1281 }
1282
1283 return MODE_OK;
1284 }
1285
1286 /* return txclkesc cycles in terms of divider and duration in us */
1287 static u16 txclkesc(u32 divider, unsigned int us)
1288 {
1289 switch (divider) {
1290 case ESCAPE_CLOCK_DIVIDER_1:
1291 default:
1292 return 20 * us;
1293 case ESCAPE_CLOCK_DIVIDER_2:
1294 return 10 * us;
1295 case ESCAPE_CLOCK_DIVIDER_4:
1296 return 5 * us;
1297 }
1298 }
1299
1300 static void set_dsi_timings(struct drm_encoder *encoder,
1301 const struct drm_display_mode *adjusted_mode)
1302 {
1303 struct drm_device *dev = encoder->dev;
1304 struct drm_i915_private *dev_priv = to_i915(dev);
1305 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1306 enum port port;
1307 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1308 unsigned int lane_count = intel_dsi->lane_count;
1309
1310 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
1311
1312 hactive = adjusted_mode->crtc_hdisplay;
1313 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay;
1314 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
1315 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end;
1316
1317 if (intel_dsi->dual_link) {
1318 hactive /= 2;
1319 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1320 hactive += intel_dsi->pixel_overlap;
1321 hfp /= 2;
1322 hsync /= 2;
1323 hbp /= 2;
1324 }
1325
1326 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay;
1327 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
1328 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end;
1329
1330 /* horizontal values are in terms of high speed byte clock */
1331 hactive = txbyteclkhs(hactive, bpp, lane_count,
1332 intel_dsi->burst_mode_ratio);
1333 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1334 hsync = txbyteclkhs(hsync, bpp, lane_count,
1335 intel_dsi->burst_mode_ratio);
1336 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio);
1337
1338 for_each_dsi_port(port, intel_dsi->ports) {
1339 if (IS_GEN9_LP(dev_priv)) {
1340 /*
1341 * Program hdisplay and vdisplay on MIPI transcoder.
1342 * This is different from calculated hactive and
1343 * vactive, as they are calculated per channel basis,
1344 * whereas these values should be based on resolution.
1345 */
1346 I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port),
1347 adjusted_mode->crtc_hdisplay);
1348 I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port),
1349 adjusted_mode->crtc_vdisplay);
1350 I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port),
1351 adjusted_mode->crtc_vtotal);
1352 }
1353
1354 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive);
1355 I915_WRITE(MIPI_HFP_COUNT(port), hfp);
1356
1357 /* meaningful for video mode non-burst sync pulse mode only,
1358 * can be zero for non-burst sync events and burst modes */
1359 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync);
1360 I915_WRITE(MIPI_HBP_COUNT(port), hbp);
1361
1362 /* vertical values are in terms of lines */
1363 I915_WRITE(MIPI_VFP_COUNT(port), vfp);
1364 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync);
1365 I915_WRITE(MIPI_VBP_COUNT(port), vbp);
1366 }
1367 }
1368
1369 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)
1370 {
1371 switch (fmt) {
1372 case MIPI_DSI_FMT_RGB888:
1373 return VID_MODE_FORMAT_RGB888;
1374 case MIPI_DSI_FMT_RGB666:
1375 return VID_MODE_FORMAT_RGB666;
1376 case MIPI_DSI_FMT_RGB666_PACKED:
1377 return VID_MODE_FORMAT_RGB666_PACKED;
1378 case MIPI_DSI_FMT_RGB565:
1379 return VID_MODE_FORMAT_RGB565;
1380 default:
1381 MISSING_CASE(fmt);
1382 return VID_MODE_FORMAT_RGB666;
1383 }
1384 }
1385
1386 static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
1387 const struct intel_crtc_state *pipe_config)
1388 {
1389 struct drm_encoder *encoder = &intel_encoder->base;
1390 struct drm_device *dev = encoder->dev;
1391 struct drm_i915_private *dev_priv = to_i915(dev);
1392 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1393 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1394 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1395 enum port port;
1396 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1397 u32 val, tmp;
1398 u16 mode_hdisplay;
1399
1400 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
1401
1402 mode_hdisplay = adjusted_mode->crtc_hdisplay;
1403
1404 if (intel_dsi->dual_link) {
1405 mode_hdisplay /= 2;
1406 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1407 mode_hdisplay += intel_dsi->pixel_overlap;
1408 }
1409
1410 for_each_dsi_port(port, intel_dsi->ports) {
1411 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1412 /*
1413 * escape clock divider, 20MHz, shared for A and C.
1414 * device ready must be off when doing this! txclkesc?
1415 */
1416 tmp = I915_READ(MIPI_CTRL(PORT_A));
1417 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
1418 I915_WRITE(MIPI_CTRL(PORT_A), tmp |
1419 ESCAPE_CLOCK_DIVIDER_1);
1420
1421 /* read request priority is per pipe */
1422 tmp = I915_READ(MIPI_CTRL(port));
1423 tmp &= ~READ_REQUEST_PRIORITY_MASK;
1424 I915_WRITE(MIPI_CTRL(port), tmp |
1425 READ_REQUEST_PRIORITY_HIGH);
1426 } else if (IS_GEN9_LP(dev_priv)) {
1427 enum pipe pipe = intel_crtc->pipe;
1428
1429 tmp = I915_READ(MIPI_CTRL(port));
1430 tmp &= ~BXT_PIPE_SELECT_MASK;
1431
1432 tmp |= BXT_PIPE_SELECT(pipe);
1433 I915_WRITE(MIPI_CTRL(port), tmp);
1434 }
1435
1436 /* XXX: why here, why like this? handling in irq handler?! */
1437 I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
1438 I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
1439
1440 I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
1441
1442 I915_WRITE(MIPI_DPI_RESOLUTION(port),
1443 adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT |
1444 mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
1445 }
1446
1447 set_dsi_timings(encoder, adjusted_mode);
1448
1449 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
1450 if (is_cmd_mode(intel_dsi)) {
1451 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
1452 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
1453 } else {
1454 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
1455 val |= pixel_format_to_reg(intel_dsi->pixel_format);
1456 }
1457
1458 tmp = 0;
1459 if (intel_dsi->eotp_pkt == 0)
1460 tmp |= EOT_DISABLE;
1461 if (intel_dsi->clock_stop)
1462 tmp |= CLOCKSTOP;
1463
1464 if (IS_GEN9_LP(dev_priv)) {
1465 tmp |= BXT_DPHY_DEFEATURE_EN;
1466 if (!is_cmd_mode(intel_dsi))
1467 tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
1468 }
1469
1470 for_each_dsi_port(port, intel_dsi->ports) {
1471 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1472
1473 /* timeouts for recovery. one frame IIUC. if counter expires,
1474 * EOT and stop state. */
1475
1476 /*
1477 * In burst mode, value greater than one DPI line Time in byte
1478 * clock (txbyteclkhs) To timeout this timer 1+ of the above
1479 * said value is recommended.
1480 *
1481 * In non-burst mode, Value greater than one DPI frame time in
1482 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1483 * said value is recommended.
1484 *
1485 * In DBI only mode, value greater than one DBI frame time in
1486 * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
1487 * said value is recommended.
1488 */
1489
1490 if (is_vid_mode(intel_dsi) &&
1491 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
1492 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1493 txbyteclkhs(adjusted_mode->crtc_htotal, bpp,
1494 intel_dsi->lane_count,
1495 intel_dsi->burst_mode_ratio) + 1);
1496 } else {
1497 I915_WRITE(MIPI_HS_TX_TIMEOUT(port),
1498 txbyteclkhs(adjusted_mode->crtc_vtotal *
1499 adjusted_mode->crtc_htotal,
1500 bpp, intel_dsi->lane_count,
1501 intel_dsi->burst_mode_ratio) + 1);
1502 }
1503 I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
1504 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port),
1505 intel_dsi->turn_arnd_val);
1506 I915_WRITE(MIPI_DEVICE_RESET_TIMER(port),
1507 intel_dsi->rst_timer_val);
1508
1509 /* dphy stuff */
1510
1511 /* in terms of low power clock */
1512 I915_WRITE(MIPI_INIT_COUNT(port),
1513 txclkesc(intel_dsi->escape_clk_div, 100));
1514
1515 if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
1516 /*
1517 * BXT spec says write MIPI_INIT_COUNT for
1518 * both the ports, even if only one is
1519 * getting used. So write the other port
1520 * if not in dual link mode.
1521 */
1522 I915_WRITE(MIPI_INIT_COUNT(port ==
1523 PORT_A ? PORT_C : PORT_A),
1524 intel_dsi->init_count);
1525 }
1526
1527 /* recovery disables */
1528 I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
1529
1530 /* in terms of low power clock */
1531 I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
1532
1533 /* in terms of txbyteclkhs. actual high to low switch +
1534 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
1535 *
1536 * XXX: write MIPI_STOP_STATE_STALL?
1537 */
1538 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port),
1539 intel_dsi->hs_to_lp_count);
1540
1541 /* XXX: low power clock equivalence in terms of byte clock.
1542 * the number of byte clocks occupied in one low power clock.
1543 * based on txbyteclkhs and txclkesc.
1544 * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
1545 * ) / 105.???
1546 */
1547 I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
1548
1549 if (IS_GEMINILAKE(dev_priv)) {
1550 I915_WRITE(MIPI_TLPX_TIME_COUNT(port),
1551 intel_dsi->lp_byte_clk);
1552 /* Shadow of DPHY reg */
1553 I915_WRITE(MIPI_CLK_LANE_TIMING(port),
1554 intel_dsi->dphy_reg);
1555 }
1556
1557 /* the bw essential for transmitting 16 long packets containing
1558 * 252 bytes meant for dcs write memory command is programmed in
1559 * this register in terms of byte clocks. based on dsi transfer
1560 * rate and the number of lanes configured the time taken to
1561 * transmit 16 long packets in a dsi stream varies. */
1562 I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
1563
1564 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port),
1565 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
1566 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
1567
1568 if (is_vid_mode(intel_dsi))
1569 /* Some panels might have resolution which is not a
1570 * multiple of 64 like 1366 x 768. Enable RANDOM
1571 * resolution support for such panels by default */
1572 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port),
1573 intel_dsi->video_frmt_cfg_bits |
1574 intel_dsi->video_mode_format |
1575 IP_TG_CONFIG |
1576 RANDOM_DPI_DISPLAY_RESOLUTION);
1577 }
1578 }
1579
1580 static void intel_dsi_unprepare(struct intel_encoder *encoder)
1581 {
1582 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1583 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
1584 enum port port;
1585 u32 val;
1586
1587 if (!IS_GEMINILAKE(dev_priv)) {
1588 for_each_dsi_port(port, intel_dsi->ports) {
1589 /* Panel commands can be sent when clock is in LP11 */
1590 I915_WRITE(MIPI_DEVICE_READY(port), 0x0);
1591
1592 intel_dsi_reset_clocks(encoder, port);
1593 I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP);
1594
1595 val = I915_READ(MIPI_DSI_FUNC_PRG(port));
1596 val &= ~VID_MODE_FORMAT_MASK;
1597 I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
1598
1599 I915_WRITE(MIPI_DEVICE_READY(port), 0x1);
1600 }
1601 }
1602 }
1603
1604 static int intel_dsi_get_modes(struct drm_connector *connector)
1605 {
1606 struct intel_connector *intel_connector = to_intel_connector(connector);
1607 struct drm_display_mode *mode;
1608
1609 DRM_DEBUG_KMS("\n");
1610
1611 if (!intel_connector->panel.fixed_mode) {
1612 DRM_DEBUG_KMS("no fixed mode\n");
1613 return 0;
1614 }
1615
1616 mode = drm_mode_duplicate(connector->dev,
1617 intel_connector->panel.fixed_mode);
1618 if (!mode) {
1619 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
1620 return 0;
1621 }
1622
1623 drm_mode_probed_add(connector, mode);
1624 return 1;
1625 }
1626
1627 static void intel_dsi_connector_destroy(struct drm_connector *connector)
1628 {
1629 struct intel_connector *intel_connector = to_intel_connector(connector);
1630
1631 DRM_DEBUG_KMS("\n");
1632 intel_panel_fini(&intel_connector->panel);
1633 drm_connector_cleanup(connector);
1634 kfree(connector);
1635 }
1636
1637 static void intel_dsi_encoder_destroy(struct drm_encoder *encoder)
1638 {
1639 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1640
1641 /* dispose of the gpios */
1642 if (intel_dsi->gpio_panel)
1643 gpiod_put(intel_dsi->gpio_panel);
1644
1645 intel_encoder_destroy(encoder);
1646 }
1647
1648 static const struct drm_encoder_funcs intel_dsi_funcs = {
1649 .destroy = intel_dsi_encoder_destroy,
1650 };
1651
1652 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
1653 .get_modes = intel_dsi_get_modes,
1654 .mode_valid = intel_dsi_mode_valid,
1655 .atomic_check = intel_digital_connector_atomic_check,
1656 };
1657
1658 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
1659 .late_register = intel_connector_register,
1660 .early_unregister = intel_connector_unregister,
1661 .destroy = intel_dsi_connector_destroy,
1662 .fill_modes = drm_helper_probe_single_connector_modes,
1663 .atomic_get_property = intel_digital_connector_atomic_get_property,
1664 .atomic_set_property = intel_digital_connector_atomic_set_property,
1665 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1666 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1667 };
1668
1669 static int intel_dsi_get_panel_orientation(struct intel_connector *connector)
1670 {
1671 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1672 int orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL;
1673 enum i9xx_plane_id plane;
1674 u32 val;
1675
1676 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1677 if (connector->encoder->crtc_mask == BIT(PIPE_B))
1678 plane = PLANE_B;
1679 else
1680 plane = PLANE_A;
1681
1682 val = I915_READ(DSPCNTR(plane));
1683 if (val & DISPPLANE_ROTATE_180)
1684 orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP;
1685 }
1686
1687 return orientation;
1688 }
1689
1690 static void intel_dsi_add_properties(struct intel_connector *connector)
1691 {
1692 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1693
1694 if (connector->panel.fixed_mode) {
1695 u32 allowed_scalers;
1696
1697 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
1698 if (!HAS_GMCH_DISPLAY(dev_priv))
1699 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1700
1701 drm_connector_attach_scaling_mode_property(&connector->base,
1702 allowed_scalers);
1703
1704 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1705
1706 connector->base.display_info.panel_orientation =
1707 intel_dsi_get_panel_orientation(connector);
1708 drm_connector_init_panel_orientation_property(
1709 &connector->base,
1710 connector->panel.fixed_mode->hdisplay,
1711 connector->panel.fixed_mode->vdisplay);
1712 }
1713 }
1714
1715 void intel_dsi_init(struct drm_i915_private *dev_priv)
1716 {
1717 struct drm_device *dev = &dev_priv->drm;
1718 struct intel_dsi *intel_dsi;
1719 struct intel_encoder *intel_encoder;
1720 struct drm_encoder *encoder;
1721 struct intel_connector *intel_connector;
1722 struct drm_connector *connector;
1723 struct drm_display_mode *scan, *fixed_mode = NULL;
1724 enum port port;
1725
1726 DRM_DEBUG_KMS("\n");
1727
1728 /* There is no detection method for MIPI so rely on VBT */
1729 if (!intel_bios_is_dsi_present(dev_priv, &port))
1730 return;
1731
1732 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1733 dev_priv->mipi_mmio_base = VLV_MIPI_BASE;
1734 } else if (IS_GEN9_LP(dev_priv)) {
1735 dev_priv->mipi_mmio_base = BXT_MIPI_BASE;
1736 } else {
1737 DRM_ERROR("Unsupported Mipi device to reg base");
1738 return;
1739 }
1740
1741 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1742 if (!intel_dsi)
1743 return;
1744
1745 intel_connector = intel_connector_alloc();
1746 if (!intel_connector) {
1747 kfree(intel_dsi);
1748 return;
1749 }
1750
1751 intel_encoder = &intel_dsi->base;
1752 encoder = &intel_encoder->base;
1753 intel_dsi->attached_connector = intel_connector;
1754
1755 connector = &intel_connector->base;
1756
1757 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI,
1758 "DSI %c", port_name(port));
1759
1760 intel_encoder->compute_config = intel_dsi_compute_config;
1761 intel_encoder->pre_enable = intel_dsi_pre_enable;
1762 intel_encoder->enable = intel_dsi_enable_nop;
1763 intel_encoder->disable = intel_dsi_disable;
1764 intel_encoder->post_disable = intel_dsi_post_disable;
1765 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
1766 intel_encoder->get_config = intel_dsi_get_config;
1767
1768 intel_connector->get_hw_state = intel_connector_get_hw_state;
1769
1770 intel_encoder->port = port;
1771
1772 /*
1773 * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI
1774 * port C. BXT isn't limited like this.
1775 */
1776 if (IS_GEN9_LP(dev_priv))
1777 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C);
1778 else if (port == PORT_A)
1779 intel_encoder->crtc_mask = BIT(PIPE_A);
1780 else
1781 intel_encoder->crtc_mask = BIT(PIPE_B);
1782
1783 if (dev_priv->vbt.dsi.config->dual_link)
1784 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C);
1785 else
1786 intel_dsi->ports = BIT(port);
1787
1788 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports;
1789 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports;
1790
1791 /* Create a DSI host (and a device) for each port. */
1792 for_each_dsi_port(port, intel_dsi->ports) {
1793 struct intel_dsi_host *host;
1794
1795 host = intel_dsi_host_init(intel_dsi, port);
1796 if (!host)
1797 goto err;
1798
1799 intel_dsi->dsi_hosts[port] = host;
1800 }
1801
1802 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
1803 DRM_DEBUG_KMS("no device found\n");
1804 goto err;
1805 }
1806
1807 /*
1808 * In case of BYT with CRC PMIC, we need to use GPIO for
1809 * Panel control.
1810 */
1811 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1812 (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC)) {
1813 intel_dsi->gpio_panel =
1814 gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH);
1815
1816 if (IS_ERR(intel_dsi->gpio_panel)) {
1817 DRM_ERROR("Failed to own gpio for panel control\n");
1818 intel_dsi->gpio_panel = NULL;
1819 }
1820 }
1821
1822 intel_encoder->type = INTEL_OUTPUT_DSI;
1823 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1824 intel_encoder->cloneable = 0;
1825 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
1826 DRM_MODE_CONNECTOR_DSI);
1827
1828 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
1829
1830 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
1831 connector->interlace_allowed = false;
1832 connector->doublescan_allowed = false;
1833
1834 intel_connector_attach_encoder(intel_connector, intel_encoder);
1835
1836 mutex_lock(&dev->mode_config.mutex);
1837 intel_dsi_vbt_get_modes(intel_dsi);
1838 list_for_each_entry(scan, &connector->probed_modes, head) {
1839 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
1840 fixed_mode = drm_mode_duplicate(dev, scan);
1841 break;
1842 }
1843 }
1844 mutex_unlock(&dev->mode_config.mutex);
1845
1846 if (!fixed_mode) {
1847 DRM_DEBUG_KMS("no fixed mode\n");
1848 goto err;
1849 }
1850
1851 connector->display_info.width_mm = fixed_mode->width_mm;
1852 connector->display_info.height_mm = fixed_mode->height_mm;
1853
1854 intel_panel_init(&intel_connector->panel, fixed_mode, NULL, NULL);
1855 intel_panel_setup_backlight(connector, INVALID_PIPE);
1856
1857 intel_dsi_add_properties(intel_connector);
1858
1859 return;
1860
1861 err:
1862 drm_encoder_cleanup(&intel_encoder->base);
1863 kfree(intel_dsi);
1864 kfree(intel_connector);
1865 }
CRIS linux kernel tree