drivers/gpu/drm/i915/intel_huc.c

   1 /*
   2  * Copyright © 2016-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/types.h>
  26
  27 #include "intel_huc.h"
  28 #include "i915_drv.h"
  29
  30 /**
  31  * DOC: HuC Firmware
  32  *
  33  * Motivation:
  34  * GEN9 introduces a new dedicated firmware for usage in media HEVC (High
  35  * Efficiency Video Coding) operations. Userspace can use the firmware
  36  * capabilities by adding HuC specific commands to batch buffers.
  37  *
  38  * Implementation:
  39  * The same firmware loader is used as the GuC. However, the actual
  40  * loading to HW is deferred until GEM initialization is done.
  41  *
  42  * Note that HuC firmware loading must be done before GuC loading.
  43  */
  44
  45 #define BXT_HUC_FW_MAJOR 01
  46 #define BXT_HUC_FW_MINOR 07
  47 #define BXT_BLD_NUM 1398
  48
  49 #define SKL_HUC_FW_MAJOR 01
  50 #define SKL_HUC_FW_MINOR 07
  51 #define SKL_BLD_NUM 1398
  52
  53 #define KBL_HUC_FW_MAJOR 02
  54 #define KBL_HUC_FW_MINOR 00
  55 #define KBL_BLD_NUM 1810
  56
  57 #define HUC_FW_PATH(platform, major, minor, bld_num) \
  58         "i915/" __stringify(platform) "_huc_ver" __stringify(major) "_" \
  59         __stringify(minor) "_" __stringify(bld_num) ".bin"
  60
  61 #define I915_SKL_HUC_UCODE HUC_FW_PATH(skl, SKL_HUC_FW_MAJOR, \
  62         SKL_HUC_FW_MINOR, SKL_BLD_NUM)
  63 MODULE_FIRMWARE(I915_SKL_HUC_UCODE);
  64
  65 #define I915_BXT_HUC_UCODE HUC_FW_PATH(bxt, BXT_HUC_FW_MAJOR, \
  66         BXT_HUC_FW_MINOR, BXT_BLD_NUM)
  67 MODULE_FIRMWARE(I915_BXT_HUC_UCODE);
  68
  69 #define I915_KBL_HUC_UCODE HUC_FW_PATH(kbl, KBL_HUC_FW_MAJOR, \
  70         KBL_HUC_FW_MINOR, KBL_BLD_NUM)
  71 MODULE_FIRMWARE(I915_KBL_HUC_UCODE);
  72
  73 static void huc_fw_select(struct intel_uc_fw *huc_fw)
  74 {
  75         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
  76         struct drm_i915_private *dev_priv = huc_to_i915(huc);
  77
  78         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
  79
  80         if (!HAS_HUC(dev_priv))
  81                 return;
  82
  83         if (i915_modparams.huc_firmware_path) {
  84                 huc_fw->path = i915_modparams.huc_firmware_path;
  85                 huc_fw->major_ver_wanted = 0;
  86                 huc_fw->minor_ver_wanted = 0;
  87         } else if (IS_SKYLAKE(dev_priv)) {
  88                 huc_fw->path = I915_SKL_HUC_UCODE;
  89                 huc_fw->major_ver_wanted = SKL_HUC_FW_MAJOR;
  90                 huc_fw->minor_ver_wanted = SKL_HUC_FW_MINOR;
  91         } else if (IS_BROXTON(dev_priv)) {
  92                 huc_fw->path = I915_BXT_HUC_UCODE;
  93                 huc_fw->major_ver_wanted = BXT_HUC_FW_MAJOR;
  94                 huc_fw->minor_ver_wanted = BXT_HUC_FW_MINOR;
  95         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
  96                 huc_fw->path = I915_KBL_HUC_UCODE;
  97                 huc_fw->major_ver_wanted = KBL_HUC_FW_MAJOR;
  98                 huc_fw->minor_ver_wanted = KBL_HUC_FW_MINOR;
  99         } else {
 100                 DRM_WARN("%s: No firmware known for this platform!\n",
 101                          intel_uc_fw_type_repr(huc_fw->type));
 102         }
 103 }
 104
 105 /**
 106  * intel_huc_init_early() - initializes HuC struct
 107  * @huc: intel_huc struct
 108  *
 109  * On platforms with HuC selects firmware for uploading
 110  */
 111 void intel_huc_init_early(struct intel_huc *huc)
 112 {
 113         struct intel_uc_fw *huc_fw = &huc->fw;
 114
 115         intel_uc_fw_init(huc_fw, INTEL_UC_FW_TYPE_HUC);
 116         huc_fw_select(huc_fw);
 117 }
 118
 119 /**
 120  * huc_ucode_xfer() - DMA's the firmware
 121  * @dev_priv: the drm_i915_private device
 122  *
 123  * Transfer the firmware image to RAM for execution by the microcontroller.
 124  *
 125  * Return: 0 on success, non-zero on failure
 126  */
 127 static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
 128 {
 129         struct intel_huc *huc = container_of(huc_fw, struct intel_huc, fw);
 130         struct drm_i915_private *dev_priv = huc_to_i915(huc);
 131         unsigned long offset = 0;
 132         u32 size;
 133         int ret;
 134
 135         GEM_BUG_ON(huc_fw->type != INTEL_UC_FW_TYPE_HUC);
 136
 137         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 138
 139         /* Set the source address for the uCode */
 140         offset = guc_ggtt_offset(vma) + huc_fw->header_offset;
 141         I915_WRITE(DMA_ADDR_0_LOW, lower_32_bits(offset));
 142         I915_WRITE(DMA_ADDR_0_HIGH, upper_32_bits(offset) & 0xFFFF);
 143
 144         /* Hardware doesn't look at destination address for HuC. Set it to 0,
 145          * but still program the correct address space.
 146          */
 147         I915_WRITE(DMA_ADDR_1_LOW, 0);
 148         I915_WRITE(DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
 149
 150         size = huc_fw->header_size + huc_fw->ucode_size;
 151         I915_WRITE(DMA_COPY_SIZE, size);
 152
 153         /* Start the DMA */
 154         I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 155
 156         /* Wait for DMA to finish */
 157         ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
 158
 159         DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 160
 161         /* Disable the bits once DMA is over */
 162         I915_WRITE(DMA_CTRL, _MASKED_BIT_DISABLE(HUC_UKERNEL));
 163
 164         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 165
 166         return ret;
 167 }
 168
 169 /**
 170  * intel_huc_init_hw() - load HuC uCode to device
 171  * @huc: intel_huc structure
 172  *
 173  * Called from intel_uc_init_hw() during driver loading and also after a GPU
 174  * reset. Be note that HuC loading must be done before GuC loading.
 175  *
 176  * The firmware image should have already been fetched into memory by the
 177  * earlier call to intel_uc_init_fw(), so here we need only check that
 178  * is succeeded, and then transfer the image to the h/w.
 179  *
 180  */
 181 int intel_huc_init_hw(struct intel_huc *huc)
 182 {
 183         return intel_uc_fw_upload(&huc->fw, huc_ucode_xfer);
 184 }
 185
 186 /**
 187  * intel_huc_auth() - Authenticate HuC uCode
 188  * @huc: intel_huc structure
 189  *
 190  * Called after HuC and GuC firmware loading during intel_uc_init_hw().
 191  *
 192  * This function pins HuC firmware image object into GGTT.
 193  * Then it invokes GuC action to authenticate passing the offset to RSA
 194  * signature through intel_guc_auth_huc(). It then waits for 50ms for
 195  * firmware verification ACK and unpins the object.
 196  */
 197 int intel_huc_auth(struct intel_huc *huc)
 198 {
 199         struct drm_i915_private *i915 = huc_to_i915(huc);
 200         struct intel_guc *guc = &i915->guc;
 201         struct i915_vma *vma;
 202         int ret;
 203
 204         if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 205                 return -ENOEXEC;
 206
 207         vma = i915_gem_object_ggtt_pin(huc->fw.obj, NULL, 0, 0,
 208                                 PIN_OFFSET_BIAS | GUC_WOPCM_TOP);
 209         if (IS_ERR(vma)) {
 210                 ret = PTR_ERR(vma);
 211                 DRM_ERROR("HuC: Failed to pin huc fw object %d\n", ret);
 212                 return ret;
 213         }
 214
 215         ret = intel_guc_auth_huc(guc,
 216                                  guc_ggtt_offset(vma) + huc->fw.rsa_offset);
 217         if (ret) {
 218                 DRM_ERROR("HuC: GuC did not ack Auth request %d\n", ret);
 219                 goto out;
 220         }
 221
 222         /* Check authentication status, it should be done by now */
 223         ret = intel_wait_for_register(i915,
 224                                       HUC_STATUS2,
 225                                       HUC_FW_VERIFIED,
 226                                       HUC_FW_VERIFIED,
 227                                       50);
 228         if (ret) {
 229                 DRM_ERROR("HuC: Authentication failed %d\n", ret);
 230                 goto out;
 231         }
 232
 233 out:
 234         i915_vma_unpin(vma);
 235         return ret;
 236 }